GB2073951A - Multilayer interconnections for an integrated circuit - Google Patents
Multilayer interconnections for an integrated circuit Download PDFInfo
- Publication number
- GB2073951A GB2073951A GB8111352A GB8111352A GB2073951A GB 2073951 A GB2073951 A GB 2073951A GB 8111352 A GB8111352 A GB 8111352A GB 8111352 A GB8111352 A GB 8111352A GB 2073951 A GB2073951 A GB 2073951A
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- United Kingdom
- Prior art keywords
- interconnection
- interconnections
- layer
- layers
- integrated circuit
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
An integrated circuit is disclosed in which at least three interconnection layers are provided above a semiconductor substrate 710, with intermediate insulation layers (not shown in Figure 2). Interconnections 701,703 in the first and third layers run orthogonally to interconnections 702 in the second layer and also to interconnections 704 in a fourth layer if present. To facilitate testing and inspection of the interconnections, the parallel interconnections 701,703 in the first and third layers are staggered from each other, and likewise for the interconnections 702,704. In another embodiment, through- holes for connecting interconnections in adjacent layers are provided only at or above the intersection points of the interconnections in the first and second layers. <IMAGE>
Description
SPECIFICATION
Integrated circuit with multilayer interconnections
Background of the invention
This invention relates to an integrated circuit which has interconnections in a plurality of layers with intermediate insulating layers, and more particularly to an integrated circuit which has logic circuits.
In such an integrated circuit, each interconnection layer has a plurality of interconnections for connecting the circuit elements of the integrated circuit with one another. These interconnections are not disposed in arbitrary positions within the corresponding layer, but are disposed in a plurality of positions predetermined for the particular layer. The design of the integrated circuit is made on the supposition that virtual paths called "interconnection channels" exist in the predetermined positions, and under the condition that the interconnections can be disposed only in these paths. Usually, the interconnection channels are parallel to one another and lie regularly, for example, at equal intervals.By way of example, the interconnections of the first layer may be disposed in some of a plurality of interconnection channels which extend in the lateral direction and which are parallel to one another. On the other hand, the interconnections of the second layer are disposed in a plurality of interconnection channels which extend perpendicular to those of the first layer and which are parallel to one another. For example, in case of connecting the terminal of a first logic circuit element and that of the second logic circuit element, the former is disposed on a first interconnection channel of the first layer and the latter on the second interconnection channel of the first layer.
The first interconnection of the first layer is disposed in the first channel in a manner to be connected with the terminal of the first logic circuit element. Similarly, the second interconnection of the first layer is disposed in the second channel in a manner to be connected with the terminal of the second logic circuit element.
At the points of intersection between the first and second interconnection channels and one interconnection channel of the second layer, first and second through-holes are provided in the insulating layer which underlies the interconnection channel of the second layer. The interconnection of the second layer is disposed in the interconnection channel of the second layer so as to be connected with the first and second interconnections through the first and second through-holes respectively.
By disposing the interconnections in the appropriate interconnection channels of the first and second layers in this manner, the elements of the integrated circuit can be interconnected.
In recent years, however, the packaging density of integrated circuits has risen, and the number of logic circuit elements to be received in one integrated circuit has accordingly increased. When interconnections in two layers are employed as in the conventional manner, the number of interconnections of each layer becomes large, so that the size of the integrated circuit becomes large inevitably. In other words, the packaging density lowers. In order to eliminate this problem, it is desirable to dispose interconnections in three or more layers. In this case, however, the following problems are further posed.
In the production of the integrated circuit, it is sometimes desirable for the inspection of the produced integrated circuit to peel off the insulator overlying the interconnection, to bring a probe into contact with the interconnection and to observe the change of a signal on the interconnection. Nevertheless, where three or more interconnection layers are provided, it is feared impossible on account of the third or further interconnection layer to touch the interconnection of the first or second layer by means of the probe.
In the inspection, it is sometimes desirable to examine with a microscope if the interconnection is provided in an exact position or if it is disconnected or broken. Nevertheless, where there or more interconnection layers are provided, it is feared impossible on account of the third or further interconnection layer to observe the interconnection of the first or second layer.
Summary of the invention
According to this invention, three or more layers of interconnections are provided, and the central positions of those interconnections of the different layers which extend in an identical direction are set so as not to lie one over the other.
Brief description of the drawings
Figure 1 is a diagram showing the arrangement of four layers of interconnection channels,
Figure 2 is a perspective view of an integrated circuit which includes four layers of interconnections disposed in accordance with the arrangement of the interconnection channels in Figure 1,
Figure 3 is a sectional view of the integrated circuit in Figure 2 as taken along a plane passing through the center of the interconnection of the second layer,
Figure 4 is a sectional view of the integrated circuit in Figure 2 as taken along a plane passing through the center of the interconnection of the fourth layer,
Figure 5 is a diagram showing another arrangement of four layers of interconnection channels,
Figures 6(a) and 6(b) are diagrams each showing how to provide through-holes for inter-layer connections in an integrated circuit according to this invention, and
Figure 7 is a diagram showing another way of providing through-holes in an integrated circuit according to this invention.
Description of the preferred embodiments
Figure 1 shows the plan positions of the centers of the interconnection channels of respective layers in the case of employing four layers of interconnections. Solid lines 101 indicate the interconnection channels for the first layer of interconnections, one-dot chain lines 102 the interconnection channels of the second layer, dotted lines 103 the interconnection channels of the third layer, and two-dot chain lines 104 the interconnection channels of the fourth layer. The interconnection channels 101 and 103, and those 102 and 104 run in parallel with each other, respectively, and the interconnection channels 101 and 103 run orthogonally to those 102 and 104.According to this invention, in order to prevent the parallel interconnection channels 101 and 103, and 102 and 104 from lying one over the other when viewed from above in Figure 1, one interconnection channel 103 of the third layer runs between one pair of adjacent interconnection channels 101 of the first layer, and one interconnection channel 104 of the fourth layer runs between one pair of adjacent interconnection channels 102 of the second layer.
Figure 2 is a perspective view of an integrated circuit in which interconnections are actually made on the basis of the embodiment in Figure 1. Numerals 701 - 704 designate interconnections all formed in the interconnection channels 101 - 104 of the first fourth layers, respectively. Numeral 710 designates a semiconductor substrate. The centers of the interconnections 701 - 704 coincide with those of the interconnection channels 101 - 104 in Figure 1, respectively. In Figure 2, insulator layers for insulating the interconnections 701 - 704 from one another are not shown for the sake of clarity.Figure 3 is a sectional view of the circuit in Figure 2 as taken along a plane which extends perpendicularly to the substrate 710 in a manner to contain the center line of the interconnection 702, while Figure 4 is a sectional view of the circuit in Figure 2 as taken along a plane which extends perpendicularly to the substrate 710 in a manner to contain the center line of the interconnection 704. In these figures, numerals 601 - 603 designate insulator layers which serve to insulate the interconnections 701 and 702,702 and 703, and 703 and 704 from each other, respectively.
Shown at numeral 604 is an insulator layer which overlies the interconnection 704. Numeral 605 indicates a through-hole for connecting the interconnections 701 and 702. The interconnections 701 - 704 are formed of, for example, a metal such as aluminum, a metal compound, or a semiconductor of high conductivity such as polycrystalline silicon. The insulator layers 601 - 603 are formed of, for example, a transparent insulator such as sputtered silicon dioxide, polyimide resin or phosphosilicate glass, or a combination of such insulators.
The interconnections employing the multilayer interconnection channels as thus far described are made on the basis of the known double-layer interconnection technique as follows.
The interconnections 701 of the first layer are disposed in the positions of some interconnection channels 101 of the first layer, and the insulation layer 601 is formed thereon. On the insulator layer 601, the interconnections 702 of the second layer are disposed in the positions of some interconnection channels 102 of the second layer and the insulator layer 602 is formed thereon. On the insulator layer 602, the interconnections 703 of the third layer are disposed in the positions of some interconnection channels 103 of the third layer and the insulator layer 603 is formed thereon. On the insulator layer 603, the interconnections 704 of the fourth layer are disposed in the positions of some interconnection channels 104 of the fourth layer and are overlaid with the insulator layer 604.
In this case, the interconnections of the first layer are connected with circuit elements directly or through the through-holes, and the mutual connection of the interconnections of the adjacent layers is made through through-holes provided in the inter vening insulator layer.
As apparent from Figures 2 to 4, the interconnections 703 of the third layer do not overlie the interconnections 701 of the first layer. Therefore, when the insulator layers 601 - 604 overlying the interconnection 701 of the first layer are peeled off, the interconnection 703 of the third layer does not form an obstacle. It is accordingly possible to bring a probe into contact with the interconnection 701 of the first layer and to test a signal on this interconnection. Since the insulator layers 601 - 604 are formed of a transparent substance and the interconnections 703 of the third layer do not overlie the interconnec tions 701, these interconnections 701 of the first layer can be examined with a microscope.
Besides the ease of inspection mentioned above, the present embodiment has the following merit.
The interconnection 701 of the first layer and the interconnection 703 of the third layer which extend in the identical direction do not overlap each other, and hence, the coupling capacitance between the two interconnections is very small. As a result, noise developing on the interconnection 701 of the first layer and the interconnection 703 of the third layer due to the coupling capacitance is low.
As understood from the above description, where the interconnection 703 of the third layer lies between one pair of interconnections 701 of the first layer, it is desirable for maximizing the effects of this invention that the sum of the widths wr and w2 of the respective interconnections of the first layer and the third layer is not greater than the pitch p1 of the interconnections 701 of the first layer. In actuality, however, this invention is effective even if this condition is not met.
This applies also to the interconnections 702 of the second layer and the interconnections 704 of the fourth layer.
Regarding the interconnections 704 of the fourth layer, the following can be further said. If the interconnection 703 of the third layer overlies the interconnection 701 of the first layer, that part of the interconnection 704 of the fourth layer which intersects with the two interconnections 701 and 703 will have underneath it five layers: the interconnection 701 of the first layer, the insulator layer 601, the insulator layer 602, the interconnection layer 601, the insulator layer 602, the interconnection 703 of the third layer, and the insulator layer 603. On the other hand, in a neighbouring region, only the three insulator layers 601 - 603 will be stacked under the interconnection 704 of the fourth layer without the interconnections 701 and 703 of the first and third layers. As a result, the height of the interconnection 704 of the fourth layer will differ by an amount corresponding to the two layers between in the aforecited intersecting part and the neighbouring region. Such large difference of the height leads to the disadvantage that the interconnection 704 of the fourth layer is liable to disconnection. That is, in the ordinary multilayer interconnections, in case where interconnections of different layers extending in an identical direction are overlaid with an interconnection of another layer extending in a direction orthogonal to the above direction, the step or level difference of the last interconnection becomes large and this interconnection is prone to be disconnected.
In contrast, with the present embodiment, the interconnection 703 of the third layer does not exist underneath the part in which the interconnection 704 of the fourth layer and that 701 of the first layer intersect. As seen from Figure 4, accordingly, nowhere does the step of the interconnection 704 of the fourth layer corresponds to more than one layer.
Thus, the provision of the interconnections of the four layers as in this embodiment brings forth the effect that disconnection of the fourth layer is less likely to occur.
Figure 5 shows a second embodiment of this invention.
Due to restrictions of semiconductor manufacturing techniques, it is sometimes the case that the minimum width of the interconnection cannot help being made larger in the upper layer than in the lower layer, with the result that the pitch of the interconnections cannot help being made greater in the upper layer. In Figure 5, therefore, one interconnection channel 103 or 104 of an upper layer is disposed in correspondence with two interconnection channels 101 or 102 of a lower layer, respectively. By making the pitch of the interconnection channels of the upper layer greater than that of the interconnection channels of the lower layer in this manner, the restrictions in the semiconductor manufacturing techniques can be overcome.
Now, the way of providing through-holes for connecting the interconnections of the different layers will be described with regard to the case of
Figure 5. It is the simplest to provide the throughhole at the point of intersection between the interconnection channels in which two interconnections are respectively formed.
In Figure 6(a), interconnections 311A and 311B disposed in one adjacent pair of interconnection channels 101 of the first layer are respectively connected to two split interconnections 312A and 312B disposed in the interconnection channel 102 of the second layer, by means of through-holes 301A and 301 B provided at the points of interconnection between these interconnection channels. It is supposed that a through-hole need not be provided at the point of interconnection between the interconnection channel 103 and the interconnection channel 102 which lies between the pair of interconnection channels 101. It is usually desirable that the pitch of the interconnection channels 101 is as small as possible to the end of disposing the largest possible number of interconnections of the first layer.It is accordingly desirable that the distance between the interconnections 31 1A and 311 B is as close as possible to the minimum pattern interval consistent with the prevention of short-circuiting between the adjacent interconnections.
In the case of Figure 6(a), the spacing 321 between the interconnections 312A and 312B needs to be made equal to or greater than the allowable minimum pattern interval. When the spacing 321 is made equal to the allowable minimum pattern interval, the distance between the interconnections 311A and 311 B may be made slightly greater than the allowable minimum pattern interval, and accordingly, the pitch of the interconnection channels 101 need not be made especially great
However, when the pitch of the interconnection patterns 101 is set in this manner, it is undesirable for there to be a situation as shown in Figure 6(b), in which a through-hole is provided at the point of intersection between the interconnection channel 102 of the second layer and one interconnection channel 101 of the first layer, and also a throughhole is provided at the point of intersection between the interconnection channel 103 of the third layer adjoining that interconnection channel 101 and the same interconnection channel 102. In Figure 6(b), the interconnection 312A in the interconnection channel 102 is connected to the interconnection 311A in the interconnection channel 101 through the throughhole 301, while the interconnection 303 in the interconnection channel 103 adjoining this interconnection channel 101 is connected to the other interconnection 312B in the same interconnection channel 102 through the through-hole 302. In this case, the spacing 322 between the interconnections 312A and 312B is considerably smaller than the pitch of the interconnection channels 101 and accordingly cannot avoid becoming smaller than the allowable minimum pattern interval.Therefore, the connections of the interconnections as shown in Figure 6(b) must be prohibited when the pitch of the interconnection channels 101 is small. More specifically, when providing the through-hole 302 at the point of intersection between the interconnection 303 of the third layer and the interconnection 312B of the second layer, it is necessary to check whether or not a through-hole is provided at the point of intersection between the interconnection channel 102 to which the interconnection 31 2B belongs and the interconnection channel 101 of the first layer, this point of intersection adjoining the first-mentioned point of intersection between the interconnections 303 and 312B. If the through-hole is provided at the adjoining point of intersection, no through-hole should be provided at the first-mentioned point of intersection.
That is, the provision of the through-hole between the interconnections of the upper layers is limited by the presence of a through-hole between the interconnections of the lower layers. Therefore, when providing the through-hole at the point of intersection between the interconnection channels of the upper layers, it must be checked each time whether or not a through-hole exists at the adjoining point of intersection between the interconnection channels of the lower layers. This poses the problem that computer processing for determining the positions of the interconnections is complicated.
Figure 7 shows an embodiment which has solved the problem by restricting the positions at which through-holes are formed, to the points of intersec tion between the interconnection channels of two adjacent layers. Here, such points of intersection are illustrated as those (dots 511) of the interconnection channels 101 and 102 of the first and second layers in which the numbers of interconnection channels can be selected the largest in the vertical and lateral directions, respectively.
An interconnection 510 in the interconnection channel 101 of the first layer can be connected to an interconnection 520 in an interconnection channel 102 of the second layer by a through-hole 501 provided at the point of intersection between these interconnection channels. Where an interconnection 530 in the interconnection channel 103 of the third interconnection layer adjoining the interconnection channel 101 provided with the interconnection 510 is to be connected with an interconnection 521 in the same interconnection channel 102 as that provided with the interconnection 520, a through-hole 502 is provided at that point of intersection among points of intersection 511 on the interconnection channel 102 which is the closest to the interconnection channel 103 to be provided with the interconnection 530, and a bend portion a which leads to the through-hole 502 and which extends in the direction perpendicular to the interconnection channel 103 is disposed as a part of the interconnection 530. As a result, the spacing between the interconnections 520 and 521 lying in the identical interconnection channel 102 becomes approximately equal to the interval between the points of intersection 511 and can be made greater than the minimum allowable interval.
The bend portion a of the interconnection 530 is formed of the same material as the remaining portion thereof and at the same time as it.
When connecting an interconnection 531 disposed in the interconnection channel 103 of the third layer and an interconnection 540 disposed in the interconnection channel 104 of the fourth layer, a throughhole is provided at one point of intersection 511 which is the closest to both the interconnection channels. An example of this through-hole is a through-hole 503. The interconnection 540 is provided with a bend portion b which extends ortho gonallytothe interconnection channel 104 and which leads to the through-hole 503. On the other
hand, the interconnection 531 is provided with a
bend portion c which extends orthogonally to the interconnection channel 103 and which leads to the through-hole 503. Thus, the interconnections 531 and 540 can be connected by the through-hole 503 which is provided at the single point of intersection 511.
The bend portion b of the interconnection 540 is formed of the same material as the remaining part thereof and at the same time as it. The bend portion c of the interconnection 531 is formed of the same material as the remaining partthereof and atthe same time as it.
As described above, the through-holes are provided at the points of intersection between the interconnection channels of the two adjacent layers.
In this way, the through-holes for the interconnections of the upper layers can be realized without checking the presence or absence of the throughholes for the interconnections of the lower layers, and the computer processing for determining the interconnection positions is simplified.
In the embodiment of Figure 7, where an interconnection (not shown) is disposed in, for example, the interconnection channel 102 passing through the point of intersection at which the through-hole 503 exists, the change of the height (the step) of the interconnection at the bend portion b becomes great. Since, however, such cases seldom occur, the probability of the occurrence of a disconnection is on the whole low. Where an interconnection is disposed in the interconnection channel 101, the capacitance between this interconnection and the interconnection 540 is small because both the interconnections are superposed in only the bend portion b.
Visual testing or probing of the interconnection disposed in this interconnection channel 101 is impossible only in the bend portion, and is substantially possible.
Of course, if a fourth layer of interconnections is not employed, the step of the bent portion or the coupling capacitance is as small as in the other parts.
The preferred embodiments set forth above have the important merits (1) that the interconnections of all the layers can be visually tested and (2) that by destroying the inter-layer insulating layer, the probe can be connected with the interconnection of the lower layer so as to test it.
Claims (9)
1. An integrated circuit comprising at least three interconnection layers stacked with intermediate insulating layers, each of said interconnection layers including a plurality of interconnections, said plurality of interconnections in each layer being disposed in some of a plurality of interconnection positions predetermined for each layer and arrayed in parallel with one another, the interconnections of the first and third interconnection layers among said plurality of interconnection layers extending in a first direction, the interconnections of the second interconnection layer extending in a second direction orthogonal to said first direction central positions of the respective interconnections of said third interconnection layer being staggered from central positions of the respective interconnections of said first interconnection layer.
2. An integrated circuit according to claim 1, wherein said insulating layers are made of a transparent insulator.
3. An integrated circuit according to claim 1 or 2, wherein the pitch of said interconnections of said third interconnection layer is greater than that of said interconnections of said first interconnection layer.
4. An integrated circuit according to claim 1,2 or 3, including a forth said interconnection layer having a said plurality of interconnections extending in said second direction, the central positions thereof being staggered from central positions of said interconnections of said second interconnection layer.
5. An integrated circuit according to claim 4, wherein the pitch of said interconnections of said fourth interconnection layer is greater than that of said interconnections of said second interconnection layer.
6. An integrated circuit according to any of claims 1 to 5, wherein a through-hole for connecting two interconnections respectively belonging to two adjacent layers is provided only at a point of intersection between the interconnection channels in which said two interconnections are respectively disposed.
7. An integrated circuit according to any of claims 1 to 5, wherein a through-hole for connecting two interconnections respectively belonging to two adjacent layers is provided only at a point of intersection between the interconnection channels of one predetermined pair of adjacent layers.
8. An integrated circuit according to claim 7, wherein said predetermined pair of layers is the first layer and the second layer.
9. An integrated circuit substantially as described herein with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4826480 | 1980-04-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2073951A true GB2073951A (en) | 1981-10-21 |
| GB2073951B GB2073951B (en) | 1984-10-03 |
Family
ID=12798569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8111352A Expired GB2073951B (en) | 1980-04-11 | 1981-04-10 | Multilayer interconnections for an integrated circuit |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE3114679A1 (en) |
| GB (1) | GB2073951B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2157886A (en) * | 1984-04-18 | 1985-10-30 | Gen Electric Co Plc | Semiconductor devices |
| US4587549A (en) * | 1982-06-04 | 1986-05-06 | Tokyo Shibaura Denki Kabushiki Kaisha | Multilayer interconnection structure for semiconductor device |
| US4857987A (en) * | 1985-09-20 | 1989-08-15 | Hitachi, Ltd. | Semiconductor device |
| US5497034A (en) * | 1986-03-31 | 1996-03-05 | Hitachi, Ltd. | IC wiring connecting method and apparatus |
| WO2015160671A1 (en) * | 2014-04-15 | 2015-10-22 | Qualcomm Incorporated | Pattern between pattern for low profile substrate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3228399A1 (en) * | 1982-07-29 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED CIRCUIT |
| DE3315615A1 (en) * | 1983-04-29 | 1984-10-31 | Brown, Boveri & Cie Ag, 6800 Mannheim | METHOD FOR PRODUCING A MULTILAYER CIRCUIT |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4140967A (en) * | 1977-06-24 | 1979-02-20 | International Business Machines Corporation | Merged array PLA device, circuit, fabrication method and testing technique |
-
1981
- 1981-04-10 GB GB8111352A patent/GB2073951B/en not_active Expired
- 1981-04-10 DE DE19813114679 patent/DE3114679A1/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4587549A (en) * | 1982-06-04 | 1986-05-06 | Tokyo Shibaura Denki Kabushiki Kaisha | Multilayer interconnection structure for semiconductor device |
| GB2157886A (en) * | 1984-04-18 | 1985-10-30 | Gen Electric Co Plc | Semiconductor devices |
| US4857987A (en) * | 1985-09-20 | 1989-08-15 | Hitachi, Ltd. | Semiconductor device |
| US5497034A (en) * | 1986-03-31 | 1996-03-05 | Hitachi, Ltd. | IC wiring connecting method and apparatus |
| WO2015160671A1 (en) * | 2014-04-15 | 2015-10-22 | Qualcomm Incorporated | Pattern between pattern for low profile substrate |
| CN106575623A (en) * | 2014-04-15 | 2017-04-19 | 高通股份有限公司 | Pattern between pattern for low profile substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3114679A1 (en) | 1982-01-14 |
| GB2073951B (en) | 1984-10-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20010409 |