JPH02239658A - Wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To use only one wiring layer and to efficiently wire in a short period of time by wiring master lines on master wiring regions on wiring element rows, and wiring branch line elements between cell rows and wiring element row and in branch line element wiring regions between the rows. CONSTITUTION:Wiring elements of the same direction as a cell row direction are formed as wiring element rows 11-15, regions on the rows are formed as master line wiring regions T1-T5, and master lines 16 are wired on the regions. Branch line element wiring regions are formed between cell rows and the rows 11-15 and between the element rows, and branch elements 17 for forming branch lines with the elements 17 are wired on the regions. Further, the regions of the ends of wiring elements 7 and the lines 16 on the region on the element rows are formed as contact regions, and contact parts 19 for wiring the master lines to the branch lines are wired with the region. Thus, one wiring layer may be sufficient to wire efficiently in a short period of time.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a wiring method for a semiconductor device, and more specifically to a wiring method for a semiconductor device that requires only one wiring layer in the wiring process. With the aim of being able to perform wiring processing efficiently in a short period of time by using only one layer, a bulk structure extending in a direction perpendicular to the cell rows is formed in advance in the wiring region formed between each cell row. In a semiconductor device in which wiring elements are formed at predetermined intervals in the vertical and horizontal directions, each wiring element in the same direction as the cell column direction is defined as a wiring element column, and a region on each wiring element column is provided in the same direction as the cell column direction. wiring a main line, and wiring a branch line element that together with each wiring element constitutes a branch line provided in a direction perpendicular to the main line in a region between the cell column and the wiring element column and between each wiring element column; , a contact portion for connecting the main line and the branch line is wired in the area between the end of the wiring element and the main line in the area on each line element row. [Industrial Application Field] The present invention relates to a wiring method for a semiconductor device, and more specifically, to a wiring method for a semiconductor device that requires only one wiring layer in the wiring process. In recent years, there has been a demand for shorter development and delivery times in LSI development. Efforts are being made to improve design tools and manufacturing technology, but it is difficult to shorten development and delivery times because there are many mask layers in the post-processing and process steps that handle actual patterns. It is in. the result,
There is also a need to shorten the wiring process that follows this process. [Prior Art] Conventionally, in the arrangement technology for semiconductor devices, multi-layer wiring has been used in order to realize connections that do not cause short-circuits between wires of complicated intersecting nets. For example, the channel wiring method is often used in mask slicing LSI wiring, and in the wiring area formed between cell rows, wires (main lines) that extend parallel to the cell rows and wires that run perpendicular to the cell rows. Two-layer wiring is used in which the (branch lines) and branch lines are each made on a separate layer. When connecting a main line and a branch line, a contact hole is formed and the connection is made through the contact hole. [Problems to be Solved by the Invention] However, since the above wiring method requires two wiring layers, two or more masks are required, which takes time and effort to manufacture. There was a limit. Therefore, the present applicant has proposed a semiconductor device in which the wiring layer created in the wiring process can be formed in one layer. In this semiconductor device, wiring elements of a bulk structure extending in a direction perpendicular to the cell rows are created in advance at predetermined intervals vertically and horizontally in the wiring region formed between each cell row, and these wiring elements are used to connect the main line. This is intended to avoid short circuits with branch lines. SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring method for a semiconductor device that uses a semiconductor device with the above-mentioned special bulk structure, requires only one wiring layer, and can perform wiring processing efficiently in a short period of time. ．． [Means for Solving the Problems] In order to achieve the above object, a wiring method for a semiconductor device according to the present invention first includes a wiring region formed between each cell column, in advance in a direction perpendicular to the cell column. A semiconductor device is prepared in which extending bulk elliptical wiring elements are formed at predetermined intervals vertically and horizontally. Then, each wiring element in the same direction as the cell column direction is defined as a wiring element column, the area on each wiring element column is defined as a main line wiring area, and the main line is routed to this area. Furthermore, the area between the cell column and the wiring element column and between each wiring element column is defined as a branch line element wiring area, and the branch line element that constitutes a branch line with the wiring element is routed to this area.

Further, in the region on the wiring element row, the area between the end of the wiring element and the main line is set as a contact area, and a contact part for connecting the main line and the branch line is wired in this area. [Function] The main line is routed to the main wiring area on each wiring element column, and the branch element is routed to the branch element wiring area between the cell column and the wiring element column and between each wiring element column. and branch lines are never connected to each other. Further, when connecting the main line and the branch line, a contact portion perpendicular to the main line is formed on the wiring element, so that the main line and the branch line are connected. As a result, it becomes possible to form the trunk lines, branch lines, and contact portions on the same plane, allowing single-layer wiring. Also, main line,
By adding conditions for the wiring positions of branch lines and contacts, it is possible to use the channel wiring method that is used when wiring using design tools such as CAD, and the wiring processing work is also simplified. It can be done without any problem. [Examples] Examples that embody the present invention will be described below with reference to the drawings. FIG. 1 is a layout diagram schematically showing wiring formed by the wiring method of the present invention, FIG. 2 is an image diagram when wiring according to the invention is performed, and FIG. Figure 4 is a cross-sectional view showing wiring elements formed in the wiring area of a semiconductor device. First, the configuration of the semiconductor device will be explained with reference to FIG.

A plurality of cell rows 4 each having a large number of cells 3 are provided at the center of the substrate 2 of the semiconductor device 11, and a plurality of I/Os are provided at the outer periphery of the substrate 2 so as to surround each of the cell rows 4. The O cells 5 are arranged in a substantially square ring shape. The space between the cell rows 4 is defined as a wiring region 6. As shown in FIG. 4, wiring elements 7 made of aluminum and extending in a direction perpendicular to the cell rows 4 are formed in advance in the wiring area 6 at predetermined intervals vertically and horizontally as shown in FIG. An insulating layer 8 is formed on the substrate 2 including the wiring element 7, and both ends of the wiring element 7 are exposed by extending upward through through holes. Next, a wiring method for the semiconductor device 1 in which a large number of wiring elements 7 are formed in the wiring region 6 in a bulk elliptical manner as described above will be explained with reference to FIG. 1.2. As shown in FIG. 1, if each wiring element 7 in the same direction as the cell row 4 is defined as a wiring element row, five wiring element rows 11 to 15 are formed. The regions on each of the element rows 11 to 15 are defined as main wiring regions, that is, wiring tracks T1 to T5, as shown in FIG. In the wiring tracks T1 to T5, wiring (main line 16) is formed in a direction perpendicular to each wiring element 7 of the wiring element rows 11 to 15. Since the trunk line 16 and each wiring element 7 are electrically insulated by the insulating layer 8, short circuits will not occur.

Boundaries Bl, B2 in wiring area 6 and wiring element array 11
．． When a wiring (branch line element 17) connecting the area between 15 and each wiring element row 11 to 15 is formed, the branch line element 17
and the wiring element 7 in the direction perpendicular to the main line 16 (
A branch line 18) is formed. Since the wiring element 7 intersects the branch line 18 at the location where the branch line 18 intersects with the main line 16, the main line 16 and branch line 18 of different nets will not be short-circuited.
Next, when a region connecting the main line 16 and both ends of the wiring element 7 is wired (with one contact part), the main line 16 and the branch line 18 are connected by this contact part 19 .

Then, the net a connecting the H and K end points shown in Figure 1 is H,
Each branch line element 17 on the grid passing through the K end point, a branch line 18 consisting of each wiring element 7, and a main line 16 on the wiring track T2
and a contact portion 19. I,L
, N end points is a branch line 1 consisting of each branch line element 17 and each wiring element 7 on the grid passing through the I, L, and N end points.
8. Main line 16 and contact part 1 on wiring track T3
It is formed by two.

Further, a net C connecting the J and M end points is formed by each branch line element 17 on the grid passing through the J and M end points, a branch line 18 consisting of each wiring element 7, a main line 16 on the wiring track T2, and a contact portion 19. .

Therefore, these nets a, b, and c are wired without shorting each other. Moreover, when forming the wiring layer for this wiring, it is only necessary to consider the branch line elements 17 and contact portions 19 that constitute the main line 16 and branch lines 18, and they can be formed in the same wiring layer. This makes it possible to use one pattern, that is, one layer of wiring in the wiring process. Further, when wiring processing is performed using a design tool such as a CAD device in the semiconductor device 1 in which such wiring elements 7 are formed in advance, a channel wiring method can be used. That is, the area above each wiring element row 11 to 15 is defined as a trunk wiring area in which the trunk line 16 provided in the same direction as the cell row 4 direction is routed, and the area between the cell row 4 and the wiring element row 11.15 and each wiring The element rows 11 to 15 are defined as a branch line element wiring area for wiring the branch element 17 of the branch line 18 provided in the direction perpendicular to the main line 16, and the area connecting the end of the wiring element 7 and the main line 16 is defined as the main line 16. If it is defined as one contact part connecting the branch line 18 and the branch line 18, the wiring route of each net can be determined using the channel wiring method. After determining the wiring route, by extracting the pattern of only the main line 16, branch element 17, and contact part 19 in the route,
A wiring pattern for the first layer wiring is created. Note that each of the wiring tracks T1 to T5 does not have to be wired with only one main line 16, but may be configured to have a plurality of wires. Since each of the wiring tracks T1 to T5 has a width equal to the length of the wiring element 7, each of the tracks T1 to T5 forms a plurality of main lines 16 with different nets in parallel unless a contact line is generated. It is possible to do so. Fifth
The figure shows a case in which a net d connecting the end points o and P is formed in addition to the nets a to C, and a main line 16 is provided in the wiring track T2 on the wiring element array 12, and the main line of nets a and C is connected to the main line of nets a and C. They will be wired in parallel. In this case, when determining the wiring route using the Chiginel wiring method, it is necessary to take into account that a plurality of trunk lines are provided in each of the wiring tracks T1 to T5. [Effects of the Invention] As described in detail above, the present invention has an excellent effect in that only one wiring layer is required and wiring processing can be performed efficiently in a short period of time.

[Brief explanation of drawings]

FIG. 1 is a layout diagram schematically showing wiring formed by the wiring method of the present invention, FIG. 2 is an image diagram when wiring according to the invention is performed, and FIG. FIG. 4 is a cross-sectional view showing wiring elements formed in the wiring area of a semiconductor device, and FIG. 5 is a layout diagram schematically showing other wiring. In the figure, 1 is a semiconductor device, 4 is a cell column, 7 is a wiring element, 11 to 15 are wiring element columns, 16 is a main line, 1
7 is a branch line element, 18 is a branch line, 19 FIG. 3 is a plan view showing the schematic structure of the semiconductor device #4 is a sectional view showing the wiring element formed in the wiring area of the semiconductor device #4

Claims (1)

[Scope of Claims] 1. In a semiconductor device in which wiring elements of a bulk structure extending in a direction orthogonal to the cell rows are formed in advance at predetermined intervals vertically and horizontally in a wiring region formed between each cell row, the cell rows include: Each wiring element in the same direction as the cell row is defined as a wiring element row, and a trunk line provided in the same direction as the cell row direction is wired in an area on each wiring element row, and between the cell row and the wiring element row, A branch line element that together with each wiring element constitutes a branch line provided in a direction perpendicular to the main line is wired in a region between each wiring element row, and further, in a region above each wiring element row, an end of the wiring element and the A wiring method for a semiconductor device, characterized in that a contact portion for connecting a main line and a branch line is wired in a region between the main line and the branch line.