JPS63250151A - Manufacture of wafer integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the reliability of a wiring part by a method wherein crossing circuit extraction wiring parts are formed in a definite manner, points to be connected in order to constitute a desired circuit structure are selected from said crossing points and an interlayer connection is executed at these points so that circuit blocks are wired. CONSTITUTION:It is supposed that circuit blocks A-F arranged in a row are identical ones and that arbitrary four blocks out of them are selected as objects where the circuit blocks are connected with one another. For example, after the circuit blocks A-F have been tested, the circuit blocks A, B, D, F to be used are selected; if external connection terminals (i) and (j) of the blocks are to be connected in the following manner; (i) of A and (i) of B; (i) of D and (i) of F; (j) of A and (j) of D; (j) of B and (j) of F. These connections are realized if an interlayer connection is executed at points indicated by black round marks out of crossing points between interblock wiring parts 1(2a)-1(6A) and circuit extraction wiring parts 3. By this setup, a process is simplified and the reliability of a wiring part is enhanced as compared with a conventional method where, after formation of a wiring part, the wiring part is made to differ according to a difference of a circuit block to be used.

Description

[Detailed Description of the Invention] [Summary] In the wiring method between the circuit pro-7 lines in the manufacture of wafer integrated circuits, the wiring is along the circuit blocks arranged in a row and is different from the circuit derivation wiring from the circuit blocks. A plurality of interblock wirings that intersect with each other are provided so that each is divided into an appropriate number of circuit blocks, and interlayer connections are formed at appropriate points from among the intersecting points to perform wiring between circuit blocks. This aims to simplify the process and increase the reliability of the wiring.

[Industrial application field]

The present invention relates to a method for manufacturing a wafer integrated circuit, and in particular,
Concerning the wiring method between circuit blocks.

To increase speed by eliminating the phenomenon of signal delays outside the logic 5-product circuit (off-chip delay), to reduce costs by omitting the wafer scribing process and assembly process, and to use the scribing area as an effective pattern area. As shown in the plan view of FIG. 3, for the purpose of group 13, and wiring group 1
The circuit block 1 has an external connection end 14 which is the termination of the circuit block
There is a wafer integrated circuit that forms a desired circuit configuration by a combination of the two.

In order to improve the yield in manufacturing wafer integrated circuits, generally the number of circuit blocks to be formed is made redundant, good circuit blocks are selected from among them through testing, and the selected circuit blocks are connected appropriately. carried out by Therefore, the wiring method is important.

[Conventional technology]

The wiring connecting selected circuit blocks in the above-mentioned wafer integrated circuit has a two-layer structure with an interlayer dielectric film interposed in order to prevent interference between vertical wiring and horizontal wiring, for example. It is common to make interlayer connections using contact holes.

There are two conventional wiring methods:

The first method is to select a circuit block to be used to form a desired circuit configuration from among a plurality of circuit blocks formed by providing appropriate wiring areas on a wafer, and then form the desired circuit configuration. This method involves designing and forming the wiring that connects the circuit blocks so that the circuit blocks are connected to each other.

The second method is to design the wiring in advance so that the desired circuit configuration can be formed by cutting the wiring according to the selection of the circuit block, and then cut the wiring in the circuit block formed on the wafer. Select the circuit block to be used from the list and use, for example, a laser or cut mask to
This is a method of performing wiring by performing the above-mentioned wiring cutting number on the formed wiring.

[Problem that the invention seeks to solve]

However, with the first method, it is necessary to design the wiring for each different circuit block to be used, and the wiring back-up is different each time, which makes the process extremely complicated and the manufacturing cost extremely high. There is.

On the other hand, the second method has the advantage that the wiring pattern remains the same regardless of the selection of the circuit blocks used, but the cut points of the circuit differ depending on the circuit blocks used. Although the process is simpler than the first method, it is still complicated, and there is a problem that the reliability of the wiring is reduced because the reliability of the cutting location tends to become unstable.

[Means for solving problems]

The above-mentioned problem is caused by a plurality of inter-block wirings that run along the circuit blocks arranged in a row and are each divided into an appropriate number of circuit blocks, and a layer that is different from the inter-block wiring that is led out from the external connection end of the circuit block. forming a constant number of intersecting circuit lead-out wiring lines, selecting a point from the intersecting points that requires a connection to form a desired circuit configuration, and forming an interlayer connection at that point; This problem is solved by the manufacturing method of the present invention that performs wiring between circuit blocks.

[Effect]

Connections between circuit blocks arranged in a row are a combination of connections from external connection ends of circuit blocks therein to external connection ends of other circuit blocks.

Therefore, according to the present wiring method, the plurality of inter-block wirings are appropriately provided, and from among them, an inter-block wiring having a portion spanning between circuit blocks where adjacent divided points are connected to each other is selected, If an interlayer connection is formed between that part and the circuit lead-out wiring from the circuit block to be mutually connected,
That connection is achieved. By combining such connections, it is possible to form wiring that makes a desired connection.

In that case, if you use the dividing point, it is possible to use one inter-block wiring for multiple connections without cutting the wiring. Since the selection of the formation location corresponds to the selection of the formation location, the wiring pattern may be constant.

Therefore, this wiring method simplifies the process and improves the reliability of the wiring compared to the second conventional method, which requires cutting the wiring differently for each different circuit block to be used after forming the wiring. make it higher. It goes without saying that the process is simpler than the first conventional method.

〔Example〕

Embodiments of the present invention will be described below using the plan view of FIG. 1, and interlayer connections will be explained using the plan view and side view of FIG. 2.

In FIG. 1, it is assumed that the circuit blocks A to F arranged in a row are the same, and any four of them are to be connected. Furthermore, although the circuit blocks A to F have a large number of external connection terminals, the external connection terminals are shown as two, i and j, respectively, for convenience of explanation in the figure.

On the other hand, if the wiring layer is shared, circuit blocks A-F
Inter-block wiring 1 (2a) along the rows of and each having dividing points 2 for an appropriate number of circuit blocks A to F.
, H2b) , H3a) , H3b), 1(4a) ,
1 (4b), and 1 (6a), and each external connection terminal l,
Derived from each of j etc., the above inter-block wiring 1
(2a) to 1 (6a) and intersecting circuit lead-out wirings 3 are formed in different wiring layers, and a glabellar insulating film 4 (shown in FIG. 2) is interposed between the restoring line layers.

Here, the numbers in parentheses of the inter-block wiring symbols indicate the number of circuit blocks spanned by the parts partitioned by adjacent dividing points 2 (a and b indicate that the dividing points 2 are shifted from each other). shows.

Therefore, when no interlayer connection is formed between the inter-block wirings 1 (2a) to 1 (6a) and the circuit lead-out wiring 3, the circuit blocks A to F become as shown in FIG. 1 (al).
They are not connected to each other at all.

For example, A, B, D, and F are selected as circuit blocks to be used by testing circuit blocks A to F, and between their external connection terminals i and j, the i of A, the i of B, and the i of D are and F is j of A and j of D and j of B and j of F,
If the connection is to be made, the connection will be made at the point indicated by the mark in FIG. This can be achieved by forming interlayer connections.

The intersection point forming the interlayer connection is the interblock wiring 1 (2
a) to 1 (6a) are selected so as to achieve the desired connection while taking into consideration the arrangement of the dividing points 2.

In the above example, interblock wiring 1 (2a) is used for the connection between A's i and 801, but interblock wiring 1
(3a) may also be used. In that case, the interblock wiring 1 (3a) will be shared for the connection between A's i and 801 and the reconnection between D's i and FO1, but the separation between the two will be at the disconnection point that exists between them. 2, and does not require wire cutting as in the conventional second method.

The above interlayer connections for making such connections are shown in Figure 2 (
As shown in the plan view of al and the side view of the same figure (b). The figure shows inter-block wiring 1 (2a) to 1 (6a)
A case is shown in which the layer of the circuit lead-out wiring 3 is placed on the lower side and the layer of the circuit lead-out wiring 3 is placed on the upper side.

That is, first, the inter-block wiring 1 (2a
) to 1 (6a) and the glabellar insulating film 4 are formed thereon. Next, inter-block wiring 1 (2a) to 1 (6a)
A contact hole 5 is formed at an intersection selected from among the intersections between the wafer and the circuit lead-out wiring 3 to form an interlayer connection. In the figure, a point where the inter-block wiring 1 (3a) intersects with the circuit lead-out wiring 3 is given a reference numeral from among the selected crossing points. Next, the circuit lead-out wiring 3, which is the upper layer, is formed.

Then, interlayer connections are formed only at the intersections where contact holes 5 are provided, and desired connections are achieved.

This interlayer connection can be formed in the same way even if the circuit lead-out wiring 2 is placed in the lower layer and the interblock wirings 1 (2a) to 1 (6a) are placed in the upper layer.

By the way, in FIG. 1, inter-block wiring 1 (2a) to
I see many things playing in (6a),
This is because the external connection ends of each circuit block A to F are explained as two, i and j, and in reality, the play is reduced.

Therefore, if the appropriate dividing points 2 can be connected,
It may become even more convenient.

This connection can be made as shown in the plan view of FIG. 2(C) and the side view of FIG. 2(d). This diagram shows inter-block wiring 1 (2a) to 1 (6
This example shows the case where the layer a) is placed on the bottom side.

That is, when forming the contact hole 5 mentioned above,
A contact hole 5 is also formed at the end of the wiring at the divided point 2 to be connected. The figure shows inter-block wiring 1
The connection at the dividing point 2 in (2a) is given by reference numeral as an example. Then, when forming the circuit lead-out wiring 3 that is the upper layer, the auxiliary wiring 6 that connects the divided portion 2 via the added contact hole 5 may be formed together.

As can be understood from the above explanation, in this wiring method, the selection of the formation location of the interlayer connection corresponds to the difference in the selected circuit blocks used, so the wiring pattern can be made constant. One inter-block wiring can be used for multiple connections without cutting the wiring.

Therefore, this wiring method simplifies the process and improves the reliability of the wiring compared to the conventional second method, which requires cutting the wiring differently for each different circuit block to be used after forming the wiring. becomes higher.

In addition, since there is no need to design wiring for each different circuit block to be used, the process is simpler than the first method, which is more complicated than the second method, which requires such design. Needless to say.

Note that the number of circuit blocks, the number of inter-block wirings, and the number of circuit blocks that span parts separated by adjacent dividing points of the inter-block wirings described in the above embodiment are examples. It is preferable to design it appropriately according to the desired circuit configuration.

Furthermore, although the above embodiment describes one side of a column of circuit blocks, the present wiring method also applies to both sides of the column, and when circuit blocks are arranged in a matrix, both vertical and horizontal columns. It is also applicable and valid.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, in the wiring method between circuit blocks in the manufacture of wafer integrated circuits, there is no need to design wiring for each different circuit block to be used, and There is no need to cut the wiring differently for each difference, which has the effect of simplifying the process and increasing the reliability of the wiring.

[Brief explanation of drawings]

FIG. 1 is a plan view for explaining an embodiment of the present invention, FIG. 2 is a plan view and side view showing interlayer connections, and FIG. 3 is a plan view for explaining a wafer integrated circuit. In the figure, 1 (2a) to 1 (6a) are wiring between blocks, 2 is a dividing point, 3 is a circuit lead-out wiring, 4 is an insulating film between eyebrows, 5 is a contact hole, 6 is an auxiliary wiring, 11 is a wafer, 12, A to F are circuit blocks, 13 is a wiring group, 14, i and j are external connection ends, and * are interlayer connections.畢 / bad wafer collection I co-route ogi Akira Ne m1 figure $ 3 figure

Claims (1)

[Claims] A plurality of circuit blocks corresponding to semiconductor integrated circuit chips are formed on a single wafer, and appropriate wiring is performed between the circuit blocks determined to be non-defective, to form a desired circuit configuration. A method for manufacturing a wafer integrated circuit comprising: a plurality of inter-block wirings along the circuit blocks arranged in a row and each divided into an appropriate number of circuit blocks; and a block lead-out from the external connection end of the circuit block. Interlayer wiring and intersecting circuit lead-out wiring in different layers are formed uniformly, and points that require connection to form the desired circuit configuration are selected from among the crossing points, and interlayer wiring is formed at that point. A method of manufacturing a wafer integrated circuit comprising forming connections and wiring between circuit blocks.