JPH05243379A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the area of a chip as a whole by a method wherein a wiring region on a hard macro inside a semiconductor chip is made small. CONSTITUTION:The following are arranged: third-layer interconnections 123 and fourth-layer interconnections 124 which are formed on a hard macro; and fifth-layer interconnections 125 and sixth-layer interconnections 126 which cross them obliquely. In addition, the following are formed: second through holes 132 which connect second-layer interconnections to the thirdlayer interconnections 123; fifth through holes 135 which connect the fifth-layer interconnections 125 to the sixth-layer interconnections 126; fourth through holes 134 which connect the fourth-layer interconnections 124 to the fifth-layer interconnections 125; and third through holes 133 which connect the third-layer interconnections 123 to the fourth-layer interconnections 124. Thereby, a wiring operation can be performed at a shortest distance on the hard macro.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to wiring between hard macros in a chip.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit device has a higher degree of integration year by year in accordance with miniaturization of the device and system requirements.

As shown in FIG. 4, a conventional semiconductor integrated circuit device has a first layer wiring 221 arranged in a horizontal direction on the drawing.
And a third layer wiring 223 having a wiring pitch twice that of the first layer wiring 221 is arranged in the horizontal direction like the second layer wiring 222 and the first layer wiring 221 arranged in the vertical direction on the drawing. The first layer wiring 221 and the second layer wiring 222 form a lattice having a minimum wiring interval, and the first through hole 231 connecting the first layer wiring 221 and the second layer wiring 222 at the lattice point.
And a second through hole 232 that connects the second layer wiring 222 and the third layer wiring 223 at a lattice point to the lattice formed by the second layer wiring 222 and the third layer wiring 223.

5 and 6 are layout diagrams showing the first and second examples of the conventional semiconductor integrated circuit device.

As shown in FIGS. 5 and 6, when the hard macro A and the hard macro B formed on the LSI chip 11 are formed by using the first layer wiring 221 and the second layer wiring 222, When wiring is connected from the hard macro A to the hard macro B according to the wiring pitch shown in 4,
The first layer wiring 221 and the second layer wiring 2 are formed on the hard macro B.
Since it is not possible to perform wiring using only 22, a method of passing over the hard macro B using the third layer wiring 223 as shown in FIG.
In the wiring region 13 around B, the first layer wiring 221 and the second layer wiring 221
There is a wiring method in which the layer wiring 222 is used. In the former case shown in FIG. 5, the output of the hard macro A is the second layer wiring 222.
Is connected to the third layer wiring 223 through the second through hole 232, and the third layer wiring 2 is formed on the hard macro B.
23 through the second through hole 23
2 is connected to the second layer wiring 222, then is connected to the first layer wiring 221 using the first through hole 231 and is again connected to the second layer wiring 222 using the first through hole 231. It is configured to be the input of. In the latter shown in FIG. 6, the upper output of the hard macro A is drawn out by using the second layer wiring 222, and the first through hole 2
31 is used to connect to the first layer wiring 221 and is wired to the upper left of the chip, is connected to the second layer wiring 222 using the first through hole 231 and is extended to the lower left, and the first through hole 231 is used again. Connected to the first layer wiring 221 and again using the first through hole 231 to form the second layer wiring 222.
It is configured to be connected to the hard macro B as an input.

[0006]

In the conventional semiconductor integrated circuit device, as shown in FIG. 4, the first layer wiring 2 in the lateral direction of the drawing is formed.
21, second layer wiring 222 and first layer wiring 2 in the vertical direction in the figure
As in the case of FIG. 21, it is formed by the third layer wiring 223 in the horizontal direction in the figure, the first through hole 231, which connects the first layer wiring 221 and the second layer wiring 222, the second layer wiring 222, and the third layer wiring 223. The second through-hole 232 connecting the second-layer wiring 222 and the third-layer wiring 223 is formed at the intersection of the minimum lattices, and the wiring in the hard macro is connected to the first-layer wiring 221.
Since it is configured by using the second layer wiring 222 and the second layer wiring 222, the wiring between the hard macros cannot pass through the hard macro by using the first layer wiring 221 and the second layer wiring 222, but passes through the hard macro. Without arranging the wiring in the empty area,
Alternatively, the third-layer wiring 223 is used only in the lateral direction of the drawing to pass through the hard macro, and then the first-layer wiring 221 is formed in the empty region.
Also, wiring is performed by connecting to the second layer wiring 222. Therefore, the shortest wiring cannot be provided, and the wiring has to be laid out, the wiring region is expanded, and the area of the entire chip is increased.

It is an object of the present invention to provide a semiconductor integrated circuit device which can reduce the wiring area and the area of the entire chip by using the multilayer wiring.

[0008]

A semiconductor integrated circuit device according to the present invention is a hard macro formed by connecting basic transistor elements using a first layer wiring and a second layer wiring provided on a semiconductor integrated circuit. A third layer wiring arranged in the horizontal direction for connecting the hard macros to each other, and a fourth layer wiring arranged in the vertical direction for intersecting the third layer wiring perpendicularly to form a lattice; A fifth-layer wiring and a sixth-layer wiring which obliquely intersect the third-layer wiring and the fourth-layer wiring other than the intersections of the layer-wiring and the fourth-layer wiring and intersect each other are provided.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram for explaining one embodiment of the present invention.

As shown in FIG. 1, for signal lines for connecting hard macros formed by connecting the basic transistor elements using the first layer wiring and the second layer wiring provided on the semiconductor chip to each other. Regarding the wiring, a third layer wiring 123 arranged in the horizontal direction on the drawing, a fourth layer wiring 124 arranged in the vertical direction on the drawing with respect to the third layer wiring 123, a third layer wiring 123 and a fourth layer The fifth-layer wiring 125, which intersects the third-layer wiring 123 and the fourth-layer wiring 124 obliquely and does not pass through the intersection of the wirings 124, and the sixth-layer wiring 125 and the sixth-layer wiring 125,
It has a layer wiring 126. Also, the third layer wiring 1
23 and the fourth layer wiring 124, the second layer wiring 222 used in the hard macro at a point shifted by a half pitch of the fourth layer wiring 124 and the inter-hard macro wiring. The third layer wiring 123 is connected by the second through hole 132, and the third layer wiring 123 and the fourth layer wiring 12 are connected.
At the intersection of the minimum lattices created in 4, the third layer wiring 123 and
The fourth layer wiring 124 is connected by the third through hole 133,
In the minimum lattice made up of the third-layer wiring 123 and the fourth-layer wiring 124, the fourth-layer wiring 124 and the fifth-layer wiring 125 are connected to the fourth through-hole 134 at a point shifted by a half pitch of the third-layer wiring 123. And the fifth layer wiring and the sixth layer wiring 124 are separated by a half pitch in the minimum lattice formed by the third layer wiring 123 and the fourth layer wiring 124 similarly to the second through hole 132. The layer wiring 126 is connected by the fifth through hole 135.

FIG. 2 is a layout diagram showing a first application example of the present invention.

As shown in FIG. 2, when wiring is connected from the lower output to the upper and lower inputs of the hard macro B on the drawing of the hard macro A according to the wiring pitch shown in FIG. Second layer wiring 222 which is wiring
The second through hole in the wiring area 13 for connecting the output to the hard macro wiring is used to connect to the third layer wiring 123, and the third through hole 133 is used to connect to the fourth layer wiring 124. Fourth through hole 13 on A
4 is used to connect to the fifth layer wiring 125, and the hard macro B
Wiring to the lower right in the drawing, and connecting wiring to the fourth layer wiring 124 using the fourth through hole 134 on the wiring region 13,
The third through hole 133 is used for connection wiring to the third layer wiring 123, and the second through hole 132 is used for connection to the input of the second layer wiring 222 which is the signal line wiring in the hard macro B.

FIG. 3 is a layout diagram showing a second application example of the present invention.

As shown in FIG. 3, when wiring is connected from the upper output in the drawing of the hard macro A to the lower input in the drawing of the hard macro B, the second layer wiring 222 output which is the wiring for the signal line in the hard macro A is output. Is connected to the third layer wiring 123 by using the second through hole 132 for connecting to the hard macro wiring, and is connected to the fourth layer wiring 124 by using the third through hole 133, and the fourth through hole 134 is formed. Connection wiring to the fifth layer wiring 125 using the fifth through hole 1
35 to connect to the sixth layer wiring 126, to the lower left of the hard macro B, to connect to the fifth layer wiring 125 to connect to the fifth layer wiring 125 to use the fifth through hole 135, and to connect to the fourth through hole 134.
Is used to connect to the fourth layer wiring 124, the third through hole 133 is used to connect to the third layer wiring 123, and the second through hole 132 is used to connect the signal line in the hard macro B. The second layer wiring 222 is connected to the input.

[0016]

As described above, according to the present invention, when hard macros formed by connecting the basic transistors using the first layer wiring and the second layer wiring on the semiconductor chip are connected to each other, the hard macros are connected to each other. Since the wiring can be arranged in the horizontal, vertical, and diagonal directions on the top, there is no need to lay out the wiring, and the second layer wiring and the third layer wiring are formed in the minimum lattice made up of the third layer wiring and the fourth layer wiring. A second through hole for connecting the third layer wiring and the fourth layer wiring, a fourth through hole for connecting the fourth layer wiring and the fifth layer wiring, and a fifth layer wiring Since the fifth through hole connecting the sixth layer wiring is arranged, wiring can be performed in a relatively short distance. According to the present embodiment, the wiring length, which was conventionally required to be 2 unit lengths in order to connect two terminals having different x-coordinates and y-coordinates, can be 2 ^1/2 unit lengths. As a result, the wiring area is reduced by about 50%, and the conventional wiring area occupies about 60% of the chip area.
The chip area can be reduced by about 30% (= 60% × 0.5).

As described above, according to the present invention, there is an effect that the wiring area can be reduced and further the entire chip can be reduced.

[Brief description of drawings]

FIG. 1 is a layout diagram for explaining an embodiment of the present invention.

FIG. 2 is a layout diagram showing a first application example of the present invention.

FIG. 3 is a layout diagram showing a second application example of the present invention.

FIG. 4 is a layout diagram for explaining a conventional wiring arrangement.

FIG. 5 is a layout diagram showing a first example of a conventional semiconductor integrated circuit device.

FIG. 6 is a layout diagram showing a second example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 11 LSI chip 13 Wiring region 123, 223 Third layer wiring 124 Fourth layer wiring 125 Fifth layer wiring 126 Sixth layer wiring 132, 232 Second through hole 133 Third through hole 134 Fourth through hole 135 Fifth through hole 221 First layer wiring 222 Second layer wiring 231 First through hole A, B Hard macro

Claims (2)

[Claims] 1. A hard macro formed by connecting between basic transistor elements by using a first layer wiring and a second layer wiring provided on a semiconductor chip, and a lateral direction connecting between the hard macros. Other than the intersection of the arranged third layer wiring, the fourth layer wiring arranged in the vertical direction that intersects the third layer wiring vertically and forms a lattice, and the intersection of the third layer wiring and the fourth layer wiring. A semiconductor integrated circuit device comprising: a fifth-layer wiring and a sixth-layer wiring which obliquely intersect the third-layer wiring and the fourth-layer wiring, respectively, and intersect each other. 2. The semiconductor integrated circuit device according to claim 1, wherein the fifth layer wiring and the sixth layer wiring are arranged on a hard macro.