JPS63172442A - Wiring method for integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to implement wires in required wiring regions between blocks by one trial, by diving the entire surface of a chip into the wiring regions on the blocks and the wiring regions between the blocks, determining wiring paths by a weighted wiring method corresponding to the degree of congestion, and thereafter determining the paths by a channel wiring method again. CONSTITUTION:Block arranging positions are fixed, and the surface of a chip is divided into wiring regions 1-4 on the blocks and wiring regions 5-11 between the blocks. A wiring path 12 of one net is determined by the wiring for the entire surface of the chip. Wirings 13-15 passing a channel regions are removed, and a set of the passing channels is determined. Only the wiring paths passing the wiring regions 1-4 are made to remain. Wiring paths 16, 17, 18 and 19 passing the wiring regions 1-4 become obstacles for the next net. Therefore, a wiring path 20 is determined by the wiring on the entire surface of the chip. All the wiring paths are determined by the same way. The wiring paths are determined by the wiring on the entire surface of the chip and the wiring between the blocks again. Therefore, unnecessary bending of the wiring in the channel region is decreased, and 100% wirings can be obtained in the smaller chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring configuration method for an integrated circuit, and more particularly to a wiring configuration method for a building block type integrated circuit.

[Conventional technology]

Conventionally, in the design of integrated circuits, the method of determining mutual wiring between blocks by passing over the blocks by computer processing is to fix all block placement positions and wiring areas between blocks, and then design using a line segment search method. There is a method of determining all wiring routes (for example, see [Large-scale high-density layout program: Alpha Ill, Information Processing Society of Japan Design Automation Study Group Materials, 1983, pp. 19-4-1 to 19-4-8].

The details of the line segment search method can be found in D. Hightower, “A Solution to Line Routing Proprem on Decontinuous Plane” (A.
ng problem on the continuo
us plane) J gross seeding of
Design Automation Workshop (Pro
Seeding of Designing Automat
ion Workshop) e1969, 1-24
It is written on the page.

When determining mutual wiring between blocks by computer processing by passing over the blocks, if the passing position on the block is selected appropriately, unnecessary bending of the wiring will occur within the wiring area between blocks, resulting in a large wiring area between blocks. However, the chip size becomes larger.

If the wiring route is determined on the entire surface of the chip after the block arrangement position is fixed by the line segment search method, the wiring route can be determined without causing unnecessary wiring bends in the inter-block wiring area.

[Problem that the invention seeks to solve]

In the conventional wiring design method described above, after fixing the 10 block placement positions through computer processing, wiring on blocks and wiring between blocks is performed. After sufficiently widening the wiring area (channel) between the blocks, the wiring is slightly rewired from the beginning.

Therefore, 100% for all connection requests (net)
The expansion and rewiring of the interblock wiring area must be repeated multiple times until the wiring is obtained.

In addition, since interconnection between blocks is performed net by net using the line segment search method, already wired nets become obstacles to the net to be wired in the on-block wiring area and the inter-block wiring area.

Even if a sufficient wiring area is secured, there is a drawback that 100% wiring cannot be achieved unless the wiring order of the nets is changed and multiple trials are performed.

Therefore, the technical problem of the present invention is to make it possible to realize 100 J wiring within the necessary inter-block wiring area by effectively utilizing the 10-block wiring area in one trial.

[Means for solving problems]

According to the present invention, in an integrated circuit in which basic logic circuits are created as blocks and the blocks are interconnected to realize a desired logic function.

After fixing the block arrangement position, the entire surface of the chip is divided into interblock wiring areas consisting of 10 upper wiring areas and a channel area which is a unit of wiring processing, and a set of channels through which a wiring path passes through the interblock wiring area is formed. After determining the wiring route passing through the upper passage wiring area by a weighted wiring method according to the degree of congestion of the wiring passing through each channel area.

A wiring configuration method for an integrated circuit is obtained, which is characterized in that a channel wiring method is used to re-determine a wiring path in a channel region passing through the wiring route in the inter-block wiring region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an Arco 9 rhythm flow diagram showing the overall structure of the present invention.

After the block arrangement position is fixed, the entire surface of the chip is divided into an inter-block wiring area consisting of an on-block wiring area and a channel area which is a wiring unit. In order to reduce the congestion of wires passing through the channel region, the entire chip is wired using a weighted wiring method (maze method) according to the number of wires passing through the channel region, and the wiring route is determined for each net on the entire chip surface. do. Furthermore, a set of channels passing through the channel region is determined for each net based on the wiring route passing through the channel region. At this time, each time the wiring route for one net is determined, only the wiring route on the block is left and the wiring route passing through the channel region is torn off and returned to an unused state. Therefore, in the channel area, the already routed nets do not become obstacles to the nets to be routed.

A net that has already been routed only in the on-block wiring area becomes an obstacle to the net to be routed. Even for terminals set inside a block, if the on-block wiring area of the uppermost wiring layer can be used freely, the terminals can be drawn out from inside the block without any problem, and a wiring route passing through the on-block wiring area can be determined.

Next, in full-chip wiring, the wiring that passes through the channel region that has been peeled off for each net is placed in the initial fixed block arrangement using the channel wiring method again for each channel, according to the set of passing channels determined for each net. Determine wiring routes within the required channel region regardless of location. In this way, the drawbacks of conventional wiring design methods are overcome.

100-chi wiring can be achieved in one trial without being affected by the net wiring order. For details on the channel wiring method, please refer to
F. Toyche [A1 Dog Reg Channel Router (A1
OpenLy”channel router ) J Flowseeding Op Design Automation Conference (proceeding of Design
nAutomation Conference)
v 1976, pp. 425-433.

FIG. 2 is a process diagram of a first embodiment of the present invention in which interconnections between blocks are determined in accordance with the order corresponding to the algorithm flow of FIG. 1.

In (,), the block arrangement position is fixed, and the inter-block wiring areas 5, 6° 7.8, 9, 10 are made up of on-block wiring areas 1.2, 3.4 and channel areas which are wiring processing units.
．． It is divided into 11 parts. In (b), the wiring route 12 of the l-net is determined by wiring the entire surface of the chip, and in (C), the set of channels passing through the channel area is determined by tearing off the wiring 13° 14.15 that passes through the wiring area on the block. 1
．． Only the wiring route passing through 2, 3 and 4 remains. (d
), the wiring areas 1, 2, 3 on the block left in (c)
, 4 become obstacles to the next net, so the wiring route 20 is formed by wiring the entire surface of the chip as in (b). In (,), in the same way as in (c), out of the wiring route 20 determined in (d), the wirings 21, 22, and 23 that pass through the channel area are peeled off to determine a set of channels that pass through the wiring area on the block. Only the wiring route passing through is left.

In (f), a wiring route passing through the channel 24 is determined by the channel wiring method. In (g), the wiring route passing through the channel 25 is determined in the same way as in (f). In (h), (
Determine the wiring route passing through the channel 26 in the same manner as f). In (i), channels 27 and 28 as in (f)
.

29. Determine the wiring route passing through 30. The placement position of the block is determined after all channel regions are wired using the channel wiring method.

FIG. 3 is a process diagram of a second embodiment of the present invention in which interconnections between blocks are determined in accordance with the order corresponding to the algorithm flow of FIG. 1.

In (,), as in FIG. 2 (,) of the first embodiment, 100
Fix the placement positions of all blocks to the block placement positions resulting from the wiring. In (b), the entire surface of the chip is interconnected again for each net. In (c), as in the embodiment shown in FIG. 2, the wiring route passing through the channel region is determined again for each channel by the channel wiring method.

In this second embodiment, after fixing the placement positions of all blocks to the block placement positions resulting from the 100-chire wiring according to the first embodiment, the wiring routes are determined again using the entire chip wiring and the inter-block wiring. Therefore, compared to the first embodiment, there are fewer unnecessary wire bends occurring in the channel region, and there is an advantage that 100% wiring can be obtained with a smaller chip area.

In this way, in the wiring design of an integrated circuit, the two embodiments of the present invention use the weighted wiring method (maze method), which has a higher search ability than the line segment search method, with the block placement position fixed. It is possible to avoid large-scale and complicated wiring prohibition areas in the wiring area and determine wiring routes that pass over high-density blocks, and also to create a weighted maze according to the degree of wiring congestion in the inter-block wiring area. By law.

Based on the set of channels to be passed determined for each net,
Since the wiring route is determined for each channel by the channel wiring method, 100-chi wiring with a small chip area can be realized in one trial by effectively utilizing the wiring area on the block.

〔Effect of the invention〕

As explained above, the present invention has the advantage that wiring with a small chip area can be realized in one trial by effectively utilizing the wiring area on the block.

[Brief explanation of the drawing]

FIG. 1 is an algorithm flow diagram showing the overall configuration of the present invention, FIG. 2 is a diagram for determining mutual wiring between blocks according to the order corresponding to the algorithm flow according to the first embodiment of the present invention, and FIG. 3 is a diagram of the present invention. FIG. 7 is a diagram for determining inter-block interconnection according to an order corresponding to an algorithm flow according to a second embodiment of the invention; 1.2, 3.4... Block and wiring area on the block, 5, 6, 7, 8, 9, 10, 11... Channel area, 12... Net wiring route, 13, 14. 15... Peeled wiring passing through the channel region, 16.17118.19... Wiring route passing on the block, 20... Net wiring route t21 = 22t23
...Teared wiring of the wiring route passing on the block, 2
4, 25, 26, 27, 28, 29. 30...Channel region, 31...Through hole or contact. Figure 1

Claims (1)

[Claims] 1) In an integrated circuit in which the basic logic circuit is created as a block and the blocks are mutually wired to realize the desired logic function, after the block placement position is fixed, the entire surface of the chip is connected to the wiring area on the block and the wiring. Divided into inter-block wiring areas consisting of channel areas, which are processing units,
After determining a set of channels through which the wiring route passes through the inter-block wiring area and a wiring route through the on-block wiring area by a weighted wiring method according to the congestion degree of the wiring through the channel area, A wiring configuration method for an integrated circuit, characterized in that a wiring route in the inter-block wiring area is determined again by a channel wiring method in the channel area through which the wiring route passes.