JPH06120342A - Wiring layout for semiconductor device - Google Patents

Abstract

PURPOSE:To minimize signal delays by determining the layout of signal lines for connecting adjacent regions and then those of signal lines in wiring regions for lines other than signal lines, and thus using only low-resistance wiring layers. CONSTITUTION:A signal line 6 is first formed for connection between wiring regions 4 and 5 adjacent to a wiring region 3 for connecting cell blocks 1 and 2. At that time the signal line 6 can be wired using a low-resistance wiring layer only without transfer from one wiring layer to another. Then signal lines 7-10, closed within the wiring region 3, are formed using an unused region therein. The method mentioned above minimizes signal delays, and is suitable for arraying high speed devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device wiring layout method for automatically laying out a wiring portion of a chip of a semiconductor device.

[0002]

2. Description of the Related Art In recent years, the chip layout of a semiconductor device has been automated, and the wiring between cells can be left to a computer to automatically perform the layout. The conventional automatic layout apparatus focuses on minimizing the signal wiring area in determining the wiring route. Therefore, the wiring layers of the signal lines often extend over multiple layers, and wiring is performed by switching the wiring layers and selecting a region having a low wiring density. Hereinafter, the method will be described with reference to FIG. FIG. 2 is a layout diagram according to a conventional wiring layout method for a semiconductor device.

As shown in FIG. 2, generally, an area for performing signal wiring layout in an automatic layout apparatus is composed of cell blocks 21 and 22 and a signal wiring area 23. Here, the wiring region 2 adjacent to the signal wiring region 23
The signal line 26 connecting the wirings 4 and 25 and the signal lines 27 to 30 closed in the wiring area 23 are automatically laid out. When performing the wiring layout of the signal line 26 with the automatic layout device,
In order to minimize the wiring area, a wiring layout is performed by finding a path for wiring a low wiring density area in the signal wiring area 23 in consideration of the area where the wiring path is already determined.

Therefore, as shown in the figure, the final wiring layout of the signal line 26 is bent in the vertical direction. That is, one type of wiring layer cannot connect adjacent wiring regions, and a plurality of wiring layers are used.

[0005]

Here, it is assumed that the wiring layer is a two-layer wiring of low resistance aluminum wiring (horizontal wiring) and high resistance polysilicon wiring (vertical wiring). In this case, if the wiring layout is performed by the above-mentioned conventional method, the polysilicon wiring is always used when the wiring layers are switched. Here, for a wiring having a long signal wiring length, the signal wiring delay is increased due to the product of the resistance of the polysilicon wiring having a high resistance and the additional capacitance of the aluminum wiring. Therefore, it is unsuitable as a wiring layout of a semiconductor device that requires high-speed operation.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a wiring layout method for a semiconductor device suitable for the layout of a high speed device.

[0007]

According to a wiring layout method of a semiconductor device of the present invention, second and third wiring regions adjacent to each other are connected via a first wiring region formed between cell blocks. After determining the wiring route of the signal line for connection between adjacent regions to be performed only by the low resistance wiring layer, the wiring route of the signal line in the first wiring region other than the signal line for connection between adjacent regions is determined. I'm trying to decide.

[0008]

According to the present invention, after determining the wiring route of the signal line for connection between adjacent areas, which connects between the second and third wiring areas, the first wiring other than the signal line for connection between adjacent areas is determined. The signal path in the wiring area is determined, and the wiring path for the signal line for connection between adjacent areas where the wiring length inevitably becomes long is designed to be wired only by the low resistance wiring layer, so that the signal delay is reduced. It can be minimized and is suitable for high speed device layout.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a layout diagram by a wiring layout method of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 1 and 2 are cell blocks, 3 is a wiring region between the cell blocks 1 and 2 (first wiring region),
4 and 5 are wiring regions (second and third wiring regions) adjacent to the wiring region 3, 6 is a signal line connecting the wiring regions 4 and 5 (signal line for connection between adjacent regions), and 7 to 10 are The signal line is closed in the wiring area 3.

The wiring layout method of this semiconductor device is as follows:
First, the layout is performed so that only the low resistance line is used for the signal line having a long wiring length. That is, the signal line 6 that connects the wiring regions 4 and 5 adjacent to the wiring region 3 that connects the cell blocks 1 and 2 is laid out. At this time, the signal line 6 can be wired using only the low resistance wiring layer without switching the wiring layer. Next, the signal line 7 to be closed in the wiring area 3 by using the vacant area in the wiring area 3 to
Lay out 10.

As described above, according to this embodiment, the cell
After laying out the signal line 6 that connects between the wiring regions 4 and 5 adjacent to the wiring region 3 that connects the blocks 1 and 2,
Lay out the signal lines 7 to 10 to be closed in the wiring area 3,
Since the signal line 6 whose wiring length is inevitably long is wired only by the low resistance wiring layer without switching the wiring layer, the signal delay can be minimized and the layout of the high speed device can be reduced. Suitable for

Further, as compared with the conventional example, the layout of the same size can be realized without increasing the height or the width of the wiring region.

[0013]

According to the present invention, after determining the wiring route of the signal line for connection between adjacent areas which connects between the second and third wiring areas, the wiring lines other than the signal line for connection between adjacent areas are determined. Since the wiring route of the signal line in the first wiring region is determined and the wiring route of the signal line for connecting the adjacent regions in which the wiring length is inevitably lengthened is performed only by the low resistance wiring layer, The delay can be minimized, which is suitable for high-speed device layout.

[Brief description of drawings]

FIG. 1 is a layout diagram of a wiring layout method for a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a layout diagram according to a conventional wiring layout method for a semiconductor device.

[Explanation of symbols]

 1, 2 cells / blocks 3 wiring area (first wiring area) 4, 5 wiring area (second and third wiring areas) 6 signal lines (signal lines for connection between adjacent areas) 7 to 10 signal lines

Claims (1)

[Claims] 1. A low-resistance wiring is used as a wiring path of a signal line for connection between adjacent regions, which connects between adjacent second and third wiring regions via a first wiring region formed between cell blocks. A wiring layout method for a semiconductor device, wherein after determining that wiring is performed only in a layer, wiring routes of signal lines in the first wiring region other than the signal lines for connecting between adjacent regions are determined.