JPH03227039A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive a reduction in the manhour of a layout and avoidance of a reduction in speed due to a detour of wirings by a method wherein a region, where first wiring layers intersect with a second wiring layer, is included between the first wiring layers, through which analog signals pass, and the second wiring layer, through which a digital pass, and a block having a third wiring layer, which is connected to the GND, is previously signal-arranged. CONSTITUTION:In order to connector wirings in an automatic layout between terminals, by which the wirings are connected to one another, at the shortest distance, analog signals inputted through analog input terminals A1, A2, A3 and A4 of a custom microcomputer 17 pass through analog signal wirings 1, 2, 3 and 4 and are inputted in a cell S2 by analog signal wirings 5, 6, 7 and 8 via a first wiring layers 11, 12, 13 and 14 of a block B1. A digital signal outputted from a port S1 passes through a digital signal wiring 9 and is inputted in a CPU by a digital signal wiring 10 via a second wiring layer 15 isolated from the layers 11, 12, 13 and 14 by a third wiring layer 16 which is connected to the GND. Thereby, it becomes possible to lay out the digital signal wirings and the analog signal wirings at the shortest distance on a mask pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a mixture of analog signal wiring and digital signal wiring designed by an automatic layout method.

[Conventional technology]

Among standard cell type custom LSIs, C
A custom LSI called the PU core method uses CPU, R
Users can freely configure a microcomputer that suits them by combining large-scale cells prepared by LSI manufacturers such as OM, RAM, I/O ports, serial processors, timers, etc. (hereinafter referred to as a custom microcontroller).

3 and 4 are mask layout diagrams showing an example of a conventional custom microcomputer in which analog signals and digital signals coexist.

As shown in FIGS. 3 and 4, 32 is the custom microcomputer described above, and A5. A6. A7. A8 is an input terminal for analog signals of the custom microcomputer, and S5 is a large-scale cell into which analog signals are input.The large-scale cell S5 and input terminals Al, A2, A3, . 27, 28, 29 which connects A4.
30 is an analog signal wiring. In addition, S4 is a large-scale cell of the I/O port, and S6 is a large-scale cell of the CPU.
Reference numeral 31 connecting the O port and the CPU is a digital signal wiring for an address bus, a data bus, a read signal, a write signal, a system clock, etc., and is simply shown as one wire.

In circuits where analog and digital signals coexist,
When analog signal wiring and digital signal wiring intersect, the analog signal is influenced by the digital signal and noise is generated in the analog signal. Therefore, in the conventional automatic layout of a custom microcontroller, when analog signals and digital signals are mixed and large cells are arranged as shown in Figure 3, the large cells of the custom microcontroller are pre-prepared cells. Since the positions of the terminals are fixed, and automatic layout generally routes the wiring between the connected terminals in the shortest possible time, it is possible to avoid crossing the analog signal wiring and digital signal wiring so that they do not intersect with the analog signal wiring. In some cases, the digital signal wiring that has the same characteristics as the analog signal wiring is manually routed in advance, or after automatic wiring, the digital signal wiring that intersects with the analog signal wiring is manually corrected. For example, in FIG. 3, the digital signal wiring 31 connecting S4 and 86 was previously manually routed around the digital signal wiring 33 shown in FIG.

[Problem to be solved by the invention]

When designing the conventional semiconductor integrated circuit described above using automatic layout, there is a possibility that the digital signal wiring and the analog signal wiring may be laid out in such a manner that they intersect. In other words, automatic layout is generally an algorithm that wires the connected terminals in the shortest possible time, and since the large-scale cell of a custom microcontroller is a pre-prepared cell, automatic layout can be performed directly after placing the large-scale cell. If this is done, the probability that analog signal wiring and digital signal wiring will intersect is quite high.

Therefore, digital signal wiring that may intersect with analog signal wiring was manually routed in advance, or after automatic wiring, digital signal wiring that intersected with analog signal wiring was manually corrected. Mistakes are likely to occur due to corrections, and detouring the signal wiring increases the chip size, and the detoured wiring becomes longer, resulting in a reduction in speed.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a first wiring layer through which an analog signal passes, a second wiring layer through which a digital signal passes, and a first wiring layer and a second wiring layer between the first wiring layer and the second wiring layer. A block including a region where the two wiring layers intersect and has a third wiring layer connected to GND is placed in advance at the intersection of the analog signal wiring and the digital signal wiring.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a mask layout diagram showing one embodiment of the present invention.

As shown in FIG. 1, Sl, S2. S3 has a large cell. Sl is a boat, which has an address bus, a data bus,
It is connected to the CPU and S3 via block B1 using digital signals such as read signals, write signals, and system clocks. Note that in actual layout, there are multiple digital signals that connect the board, Sl, and CPU, S3, but in FIG. The signal wiring is simplified to one, and is shown as 9 and 10. S2 is a block to which an analog signal is input, A
I, A2. A3. A4 is an input terminal for inputting an analog signal of the semiconductor integrated circuit, and the input analog signal is connected to S2 via block B1.

FIG. 2 shows a mask layout diagram of block B1 in FIG.

As shown in Figure 2, 11, 12 and 13, 14 are the first wiring layer through which analog signals pass, and 15 is the second wiring layer through which digital signals pass, and in reality, the digital signals connect Sl and 83. The same number exists. Further, 16 is a third wiring layer connected to GND existing between the first wiring layers 11, 12, 13, 14 and the second wiring layer 15, Includes areas where wiring layers intersect.

When large-scale cells are arranged as shown in Fig. 1, the wiring in the automatic layout connects the connected terminals in the shortest possible time, so the analog input terminal Al of the custom microcontroller 17,
A2. A3. The analog signal input from A4 passes through analog signal wiring 1, 23.4 and is sent to block B1 in Figure 2.
The signals are input to the cell S2 via the first wiring layers 11, 12, 13, and 14 of the analog signal wirings 5, 6, 7.8.

Further, the digital signal output from the boat S1 passes through the digital signal wiring 9 shown in FIG.
, 12, 13, and 14, and are inputted to the CPU via the digital signal wiring 10 via the second wiring layer 15.

〔Effect of the invention〕

As explained above, the present invention provides the first
wiring layer, a second wiring layer through which digital signals pass, and a first wiring layer.
A block having a third wiring layer connected to GND and including an area where the first wiring layer and the second wiring layer intersect between the wiring layer and the second wiring layer is preliminarily connected to analog and digital signals. By placing them where they intersect and performing automatic layout, it is possible to lay out the mask pattern of digital signal wiring and analog signal wiring in the shortest possible time, and it is also possible to manually correct the mask pattern layout data after automatic layout. Since this is no longer necessary, it is possible to reduce the number of layout steps, reduce the chip size of the semiconductor integrated circuit, and avoid a reduction in speed due to wiring detours.

[Brief explanation of drawings]

FIG. 1 is a mask layout diagram showing an embodiment of the present invention;
FIG. 2 is a mask layout diagram of block B1 in FIG.
3 and 4 are mask layout diagrams showing an example of a conventional semiconductor integrated circuit. 1.2, 3, 4, 5, 6, 7.8...Analog signal wiring, 9,10...Digital signal wiring, 11°12.1
3.14... First wiring layer, 15... Second wiring layer, 16... Third wiring layer, 17... Custom microcomputer, 27, 28, 29. 30... Analog signal wiring,
31.33...Digital signal wiring, 32...Custom microcomputer, Al, A2. A3. A4゜A5. A6. A
7. A8...Analog input terminal, Sl, S2. S3・
...Large scale cell.

Claims (1)

[Claims] Pre-prepared CPU, I/O port, ROM, RAM
In a semiconductor integrated circuit having a mixture of analog signal wiring and digital signal wiring designed using an automatic layout method based on mutual connection information of large-scale cells such as timers, the first wiring through which analog signals pass. a second wiring layer through which digital signals pass, the first wiring layer and the second wiring layer;
A semiconductor integrated circuit comprising: a third wiring layer provided between the wiring layers, including a region where the first wiring layer and the second wiring layer intersect, and connected to GND.