JPS5961057A - Formation of integrated circuit device - Google Patents

Abstract

PURPOSE:To enable high density wiring and enhance the integration degree by a method wherein signal wirings of a basic cell pattern are composed of a plurality of layers and then led outside the cell. CONSTITUTION:An integrated circuit device has the basic cell CL such as a NAND gate arranged according to necessity, and a power source line VDD, a ground line GND, and signal lines A, B, C are formed by connection to the outside of the cell. At this time, the signal wiring A of the basic cell pattern is composed of the plurality of the layers AP and AA and led outside the cell. Then, it becomes unnecessary to connect an external wiring and a signal line by means of a through hole outside the cell. As a result, a mask alignment margin is unnecessitated, and then the high density wiring is enabled. Therefore, the integration degree is enhanced.

Description

[Detailed description of the invention] The present invention relates to a method for forming a layout pattern for a circuit device.

Prior Art and Problems Conventionally, a layout pattern design method called the standard cell method is known as one of the methods for designing integrated circuit devices. This is, for example, a NAND gate or a flip gate.
Patterns are designed for basic circuits such as flops and prepared as basic cell patterns, and these basic cell patterns are arranged or interconnected as necessary to form an integrated circuit device with the desired function. This is the way to do it.

In this case, as connections to the outside of these basic cells, there are power supply wiring for supplying operating power to each basic cell and signal wiring for transmitting and receiving signals.

In general cell design, a metal wiring layer, typically aluminum, is used for the power supply wiring, and a metal wiring layer, typically aluminum, is used for the signal wiring.
Multiple wiring layers used as wiring for integrated circuit devices,
For example, any one of an aluminum layer, a polycrystalline silicon layer, a diffusion layer, etc. is selected and used. Typically, a polycrystalline silicon layer is used that can be crossed with aluminum power lines. Further, these power supply and signal wirings are led to the peripheral outer edge of the cell area and connected to the outside of the cell.

Normally, a wiring layer consisting of only one layer of polycrystalline silicon or aluminum is often used as the signal wiring in the cell, but if a large number of such cells are arranged,
When configuring an integrated circuit device by designing mutual wiring, signal wiring coming out of (or entering) a cell needs to cross other signal wiring or be installed at right angles, so it is necessary to Connections to wiring layers often occur, and this often occurs near the outer edges of the cell periphery.

In such a case, a through hole formed in an insulating film that insulates between the first layer wiring and the second layer wiring is used to connect the first layer wiring and the second layer wiring. In order to form through-holes, the pattern must be designed with allowances for mask alignment, so a considerable amount of area is required for the connections between wires, which is a major obstacle to improving the degree of integration. There is.

Let us now consider the case of designing a pattern using the two-man-powered NAND gate shown in FIG. 1 as one of the basic cells.

In this case, assuming that the gate is composed of MO3I transistors, the input signal lines are A and B, and the output signal line is C.
Therefore, a total of three signal lines are required, and in addition, a power line VOO and a ground line GND are required for supplying power to the cells.

These signal lines A, B, C1 power line VDD, ground line G N
D It is arranged as a terminal around the Hassell pattern.

In FIG. 2, a polycrystalline silicon signal line A from cell CL,
B, C, aluminum power supply line VDD and ground line GN
D has been derived.

In the figure, the signal line A is coupled to the aluminum external wiring A1 via the polycrystalline silicon external wiring P1. The polycrystalline silicon external wiring P1 and the aluminum external wiring AI are connected to each other through a through hole T formed in an insulating film (not shown).
They are connected via I.

As is clear from the diagram, polycrystalline 1-no-contact external wiring 1)
1 and the aluminum external wiring A1 is considerably enlarged to allow for mask alignment. Therefore, 2 to the aluminum external wiring installed in parallel with the aluminum external f+3 wiring △1 is J'+? If it is +, then the distance from the aluminum external wiring AI is 61, which is good; however, since there is a connection part 1iij, the distance must be set to G2.

Purpose of the Invention The present invention aims to enable high-density wiring, improve the wiring area efficiency, and increase the degree of integration by adopting a configuration that does not require a large area in the connection portion of the wiring. It is something.

Structure of the Invention In order to achieve the above-mentioned object, the present invention is used as an input signal wiring to a cell, an output signal wiring from a cell, and as an X/Y direction wiring of an integrated circuit device in a standard cell layout pattern. It is composed of two wiring layers, for example, a polycrystalline silicon layer and an aluminum layer, or a first aluminum layer and a second aluminum layer.

Embodiment of the Invention FIG. 3 is an explanatory diagram of the main parts of a basic cell which is an embodiment of the present invention, and this is intended for a NAND gate as explained in connection with FIGS. 1 and 2. The same parts as the glB part explained in connection with the figure are indicated by the same symbols.

The difference between this embodiment and the conventional example shown in FIG. 2 is that the signal wiring is composed of multiple layers.

That is, in the embodiment shown in FIG. 3, the signal line A is composed of a polycrystalline silicon line AP and an aluminum line AA. In addition, the signal wiring B is led out at the same position when viewed from above, and the polycrystalline silicon wiring BP has two layers, upper and lower.
and aluminum wiring (not shown).

Furthermore, like the signal wiring B, the signal wiring C has two layers, upper and lower, with the upper layer being a polycrystalline silicon wiring CP and the lower layer being an aluminum wiring (not shown).

In this way, since signal wiring A, B, and C are each composed of two layers of wiring, it is only necessary to select and connect some wiring corresponding to the external wiring, and in that case, through ball It is not necessary to form a connecting part such as.

The 21i wiring may be derived either by changing its position as in the signal wiring, or by making it the same as in the signal wiring B and C, and can be selected depending on the pattern design within the cell. Since the wiring layers are separated by an insulating film between the eyebrows, there is no problem with circuit function even if the wiring crosses or overlaps, other than when connecting through through holes.

By the way, since each of the signal wirings A, B, and C is derived from a plurality of wirings, the plurality of wirings, for example, the polycrystalline silicon wiring AP and the aluminum wiring A
He must be combined with A using a through ball somewhere in the cell. Although this may seem contradictory to the purpose of the present invention, it is by no means so. That is, even if the wiring density becomes slightly coarser due to the provision of the connecting portion within the cell, the area will not increase significantly because the cell itself is small. In contrast, connecting by providing through holes after going outside involves a long wiring layer, which has a far greater effect on wiring density.

Effects of the Invention According to the present invention, input/output signal wiring in a basic cell pattern having a basic function is connected to a plurality of wirings, such as a polycrystalline silicon layer and an aluminum layer, which are connected to each other within the cell. The integrated circuit device is constructed by arranging a large number of such basic cells, and selectively connecting one of the plurality of wiring layers in accordance with external wiring to form an integrated circuit device. Therefore, there is no need to use through holes to connect external wiring and signal wiring outside the cell, and therefore, the spacing between wiring can be narrower, making integrated circuit devices even more highly integrated. It is effective for

[Brief explanation of the drawing]

FIG. 1 is a symbolic diagram of a NAND gate, FIG. 2 is an explanatory diagram of a conventional example, and FIG. 3 is an explanatory diagram of a main part of an embodiment of the present invention. In the figure, CL is a cell, A, B, C are signal wiring, Δ1
) is polycrystalline silicon wiring, ΔA is aluminum wiring, B
1) is a polycrystalline silicon interconnect, and CI) is a polycrystalline silicon interconnect. Patent applicant: Fujitsu Ltd. Representative patent attorney: Kugobe (3 others)

Claims (1)

[Claims] Input/output signal wiring in a basic cell pattern with basic functions is constructed from multiple wiring layers, such as a polycrystalline silicon layer and an aluminum layer, which are connected within the cell, and are led outside the cell. 1. A method of forming an integrated circuit device, comprising arranging a large number of basic cell patterns and selectively connecting one of the plurality of wiring layers in correspondence with external wiring to configure the integrated circuit device.