JP2003324150A - Semiconductor integrated circuit device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To renew a value of a memory circuit by only changing an exposure mask which is necessary for specification modification, characteristic improvement, the addition of optional function or the like. <P>SOLUTION: Exclusive logical circuits 3a to 3d are disposed in a product information register 1. First input terminals I1 of the exclusive logical circuits 3a to 3d are connected to a power supply 11 or a GND 13 by switching first metal switch circuits 5a to 5d each composed of a first metal wiring layer, a second input terminal 12 is connected to the power supply 11 or the GND 13 by switching second metal switch circuits 7a to 7d each composed of a second metal wiring layer, and a third input terminal 13 is connected to the power supply 11 or the GND 13 by switching third metal switch circuits 9a to 9d each composed of a third metal wiring layer. When a metal wiring pattern is changed associated with specification modification, an output logical level of the exclusive logical circuits 3a to 3d and furthermore the value of the product information register 1 are changed by switching the first metal switch circuits 5a to 5d, the second metal switch circuits 7a to 7d and the third metal switch circuits 9a to 9d. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with a memory circuit for storing product information such as information on a mask set used and information on a chip type. The present invention relates to a manufacturing method thereof.

[0002]

2. Description of the Related Art In a manufacturing process of a semiconductor integrated circuit device, a plurality of exposure masks (including a reticle; the same applies hereinafter) unique to the semiconductor integrated circuit device are used. That is, the photolithography process is repeated using an exposure mask corresponding to each manufacturing process such as a transistor manufacturing process and a wiring process to manufacture a semiconductor integrated circuit device having desired functions and characteristics.

In the manufacture of a semiconductor integrated circuit device, a product is developed using a mask set consisting of a plurality of exposure masks corresponding to each process. If the developed product does not satisfy the specifications and functions in the evaluation of the prototype, it is necessary to change the circuit and improve the characteristics. Further, even after the production is started, it may be necessary to change the circuit parameters in order to stabilize the yield.

Such changes are made by revising the exposure mask. Revision of the exposure mask may be achieved by revising one exposure mask of the mask set, or revising a plurality of exposure masks in some cases. Further, the exposure mask may be revised multiple times. Thus, even the same product is manufactured with different mask sets.

There is a case where an unused basic logic function cell is embedded in advance at the designing stage in consideration of changing the function of the semiconductor integrated circuit device. When the function needs to be changed, the exposure mask in the wiring process is changed, the wiring pattern is changed to use the unused logic function cell, and the logic function is added or changed. . The function added or changed in this way is called a mask option function.

Similarly, a spare unit resistance or unit capacitance may be embedded, for example, assuming improvement or matching of analog characteristics. When it is necessary to change the characteristics, the exposure mask in the wiring process is changed to change the wiring pattern. Further, when another manufacturing line is used, a part of the exposure mask of the mask set may be changed in order to match the characteristics of the product.

In the semiconductor integrated circuit device, product information such as used mask set information (hereinafter referred to as mask set information) and chip type information (hereinafter referred to as chip type information) is recorded on the chip by some method. Preferably.

The semiconductor integrated circuit device is sealed in a package as a final product. Therefore, a method of including product information in the stamp on the surface of the package can be considered. However, the marking on the package surface is generally made to correspond to one wafer lot and to an assembly lot when assembled into a package, and it is not realistic to include more information.

On the other hand, a register having a plurality of storage circuits for storing product information is prepared in advance in a semiconductor integrated circuit chip, and the product information is stored in the register.
There is a method of knowing product information by reading the value of a register from an external terminal with an electric signal.

There are various advantages if the product information can be read out as an electric signal. For example, in production, applications such as first reading product information and performing a test according to it, and software reading this product information and automatically changing the software operation according to it can be considered.

For example, EPROM (erasable programmabl
e read only memory) and EEPROM (electrically E
For products that have a programmable non-volatile ROM such as PROM), the registers may be EPROM or EEPR.
With the OM, product information such as mask set information can be stored. However, it cannot be applied to products that do not have a programmable ROM such as EPROM or EEPROM as the product specifications, and thus has no versatility.

As a conventional technique applicable to the electrical storage of product information, there is a method of electrically storing an arbitrary unique identification number (see Japanese Patent Laid-Open No. 2000-68458). As shown in FIG. 14, a unique identification number configuration circuit 41 is provided as a register for programming a unique identification number of the device. Unique identification number configuration circuit 41
Is a plurality of basic circuits 4 each of which outputs a 1-bit signal.
3a to 43d are included.

The basic circuits 43a to 43d include a pull-up resistor 45 and a laser blow type fuse 47. In the basic circuits 43a to 43d, the pull-up resistor 45 is connected between the output terminals 49a to 49d of the basic circuits 43a to 43d and the power supply 11. The laser fusing type fuse 47 has output terminals 49a to 49d and GND (ground potential).
It is connected between 13 and. Output terminals 49a to 49d
Is a wired A of the output of the pull-up resistor 45 connected to the power supply 11 and the fuse 47 connected to the GND 13.
Expressed in ND. The outputs of the output terminals 49a to 49d are read out via the tri-state buffer 51.

However, in this method, in order to record the product information in the unique identification number forming circuit 41, it is necessary to blow the laser fusing type fuse 47 by laser irradiation, which is complicated and the manufacturing process is increased. There was a problem.

In order to eliminate such a problem, among the exposure masks for the wiring process which form the mask set, for example, the exposure mask for the metal wiring process of the uppermost layer is used to store the mask set information ( Hereinafter, a method of changing the input to a product information register) and updating the stored contents is generally performed.

FIG. 15 is a circuit diagram showing an example of a conventional product information register. As the product information register 53, third metal switch circuits 55a to 55d which are formed of a third metal wiring layer and whose input is switched to the power supply 11 or the GND 13 by the wiring pattern and connected thereto are provided. The outputs of the third metal switch circuits 55a to 55d are connected to the internal data bus 17 via the tristate buffers 57a to 57d.

Each of the third metal switch circuits 55a to 55d means a mask programmable switch circuit which constitutes one bit. Third metal switch circuit 5
By the exposure mask for forming the third metal wiring layer including 5a to 55d, the third metal switch circuit 55 is formed.
By forming the metal wiring of the third layer so that the inputs a to 55d are connected to the power supply 11 or the GND 13, the output of each bit can be set to the power supply potential or the GND potential. For example, by setting the power supply potential to be logically at H level and the GND potential to be at L level, the third metal switch circuit 55a
.About.55d can be used as the product information register 53 for storing the mask set information.

As described above, the product information register is generally constructed on the premise that it is updated using an exposure mask for a specific metal wiring process. If the mask set is designed on the assumption that, for example, only the exposure mask for a specific metal wiring process is changed and a part of the functions is added to the product lineup, the metal to be changed The exposure mask for the wiring process allows the stored contents of the product information register to be updated.

In the conventional method, the value of the product information register is updated by using only one specific exposure mask for wiring process. Therefore, it is preferable to design the particular wiring process exposure mask as a wiring process exposure mask that is highly likely to be revised due to specification revision or characteristic improvement.

[0020]

As shown in FIG. 15, when the product information register is formed by the third metal wiring layer, the third metal wiring layer is used when the specifications are revised or the characteristics are improved. When it is necessary to revise the exposure mask for the layer forming process, the product register 53 can be updated at the same time.

On the other hand, for example, when only the size of the polysilicon film pattern forming the resistor is changed as a circuit parameter to improve the analog characteristics, the mask is changed by changing the exposure mask for the polysilicon film pattern forming step. Since the set is changed, it is necessary to update the product information register.

However, updating the value of the product information register formed by the third metal wiring layer cannot be performed only by changing the exposure mask for the polysilicon film pattern forming step. In order to update the value of the product information register, it is necessary to change the exposure mask for the third metal wiring layer forming step.

As described above, in order to update the value of the product information register, even if the third metal wiring layer is not required to be revised when the specifications are revised or the characteristics are improved,
It is necessary to change the exposure mask for the third-layer metal wiring layer forming process. In other words, in addition to the original purpose of the exposure mask, which needs to be changed in accordance with the specification revision and characteristic improvement, there is a problem that other exposure masks also need to be revised just to update the value of the product information register. It was

When the mask set is revised in order to improve the functions and characteristics, it is preferable to make the desired specification change by revising the exposure mask with the smallest possible number. Changing the exposure mask only to update the value of the product information register is an unavoidable problem in the present situation where the mask manufacturing cost is rapidly increasing with the progress of miniaturization.

Therefore, the present invention provides a semiconductor integrated circuit device capable of updating the value of the memory circuit only by changing the exposure mask necessary for changing the specifications, improving the characteristics, adding an optional function, and the like, and a manufacturing method thereof. The purpose is.

[0026]

A semiconductor integrated circuit device of the present invention is for setting an exclusive logic circuit and an input logic level of the exclusive logic circuit to an H level or an L level, which are different from each other. The memory circuit is composed of a plurality of types of switch circuits that can be switched by changing only one exposure mask.

Since a plurality of types of switch circuits constituting the memory circuit can be switched by changing only one exposure mask, for example, when changing the specifications of the semiconductor integrated circuit device, improving the characteristics, or adding optional functions. In addition, the value of the memory circuit can be updated only by changing the exposure mask necessary for changing the specifications, improving the characteristics, and adding the optional function. As a result, it is possible to solve the problem that the exposure mask, which is not related to the revision of the specifications and the characteristic improvement of the semiconductor integrated circuit device, must be revised only for updating the memory circuit.

The method of manufacturing a semiconductor integrated circuit device according to the present invention uses the above memory circuit which constitutes the semiconductor integrated circuit device of the present invention and uses the above-mentioned plurality of exposure masks for each semiconductor integrated circuit device to manufacture the semiconductor integrated circuit device. The connection of the switch circuit is set to record information in the storage circuit. According to the method for manufacturing a semiconductor integrated circuit device of the present invention, information such as product information including, for example, specification information and characteristic improvement information is recorded for each semiconductor integrated circuit device manufactured using the same set of plural exposure masks. can do.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION In the semiconductor integrated circuit device of the present invention, as an example of the configuration of the memory circuit, a configuration in which the switch circuits of different types are connected to different input terminals of the exclusive logic circuit are described. Can be mentioned.

As one type of the above switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal depending on the formation area of the well region. By changing only the exposure mask for forming the well region. There can be mentioned those that can be switched. As a result, the value of the memory circuit can be updated corresponding to the change of the well region forming exposure mask.

As one type of the above switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal by the formation region of the impurity diffusion region formed on the semiconductor substrate using the field oxide film as a mask. Examples thereof include those that can be switched by changing only the exposure mask for forming the field oxide film. As a result, the value of the memory circuit can be updated corresponding to the change of the field oxide film forming exposure mask.

As one type of the above switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal depending on the formation region of the polysilicon film pattern, and the exposure mask for forming the polysilicon film pattern is used. Only those that can be switched by changing only one can be mentioned. As a result, the value of the memory circuit can be updated corresponding to the change of the exposure mask for forming the polysilicon film pattern.

As one type of the above switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal depending on the formation region of the metal wiring layer, and only the exposure mask for forming the metal wiring is changed. There can be mentioned those that can be switched by. As a result, the value of the memory circuit can be updated corresponding to the change of the metal wiring forming exposure mask.

It is preferable that each of the plurality of metal wiring layers is provided with the above-mentioned switch circuit that can be switched by changing only the exposure mask for forming the metal wiring. As a result, in the semiconductor integrated circuit device having the multi-layer metal wiring structure, the value of the memory circuit can be updated in response to the change of any metal wiring layer.

As one type of the above switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal depending on the formation region of the impurity diffusion region formed on the semiconductor substrate using the impurity introduction mask pattern as a mask. Examples of such masks are those that can be switched by changing only the exposure mask for forming the impurity introduction mask pattern. As a result, the value of the memory circuit can be updated corresponding to the change of the exposure mask for forming the impurity introduction mask pattern.

As one type of the above switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal by the formation region of the connection hole formed on the impurity diffusion region or the insulating film on the conductive material. Is something
One that can be switched by changing only the exposure mask for forming connection holes can be mentioned. As a result, the value of the memory circuit can be updated corresponding to the change of the exposure mask for forming the connection hole.

One of the switch circuits is an enhancement type MOSFET (Metal Oxide Semiconductor).
UCtor Field Effect Transistor) and a depletion type MOSFET, and an output terminal becomes an H level input terminal or an L level input terminal through an enhancement type MOSFET or a depletion type MOSFET due to an impurity injection region forming region for forming the depletion type MOSFET. One that is switched and connected, and can be switched by changing only the depletion implantation exposure mask. As a result, the value of the memory circuit can be updated corresponding to the change of the depletion implantation exposure mask.

Here, the enhancement type MOSFET
Is a MOSFET that is always off (normally off) when the voltage between the source and the gate is 0 V by applying a voltage to the gate.
The SFET has a channel formed when the source-gate voltage is 0 V, and is a normally-on MOSF.
It is ET. For example, in the N-channel MOSFET, when the threshold voltage, that is, the gate voltage when a channel is formed between the source region and the drain region and the state is switched from the non-conducting state to the conducting state, is positive with the source potential as a reference of 0V. Is called an enhancement type NMOSFET, and when it is negative, it is called a depletion type NMOSFET.

It is preferable that a plurality of the memory circuits are provided. As a result, the amount of information that can be stored increases and versatility increases.

It is preferable to further include an external output circuit for outputting the output logical value of the exclusive logic circuit to the outside. As a result, the output logical value of the exclusive logic circuit can be read out to the outside via the external output circuit. When the external output circuit is provided with an encoder, it is possible to reduce the number of wirings of a wiring circuit such as an internal data bus forming the external output circuit.

Product information can be given as the information stored in the storage circuit. As a result, the product information can be updated only by changing the exposure mask necessary for changing the specifications, improving the characteristics, and adding optional functions. Examples of product information include mask set information and chip type information.

In the method of manufacturing a semiconductor integrated circuit device of the present invention, the output terminal of the exclusive logic circuit is switched by switching the output terminal of the switch circuit corresponding to the changed exposure mask to the H level input terminal or the L level input terminal. Is preferably switched. As a result, the value of the storage circuit can be updated only by changing the exposure mask necessary for changing the specifications of the semiconductor integrated circuit device, and the exposure mask that is not related to the changes in the specifications of the semiconductor integrated circuit device can be updated. It is possible to solve the problem of having to revise just because.

[0043]

FIG. 1 is a circuit diagram showing an embodiment. In FIG. 1, only the parts constituting the present invention are shown, and other circuit parts mounted in the semiconductor integrated circuit device are omitted. In the product information register 1, for example, four exclusive OR gates (exclusive logic circuits) 3a to 3d having three input terminals are arranged.

First of exclusive OR gate 3a
The input terminal I1 is connected to the first metal switch circuit 5a formed of the first metal wiring layer, and the second input terminal I2 is formed of the second metal wiring layer of the second metal wiring layer.
The third input terminal I3 is connected to the metal switch circuit 7a.
Is connected to a third metal switch circuit 9a constituted by the third metal wiring layer. Here, the first-layer metal wiring layer, the second-layer metal wiring layer, and the third-layer metal wiring layer are sequentially formed from the lower layer side through the interlayer insulating film.

Similarly, the exclusive OR gate 3
Regarding b, 3c, 3d, the first input terminal I1 is connected to the first metal switch circuits 5b, 5c, 5d, the second input terminal I2 is connected to the second metal switch circuits 7b, 7c, 7d, and the third input The terminal I3 is connected to the third metal switch circuits 9b, 9c, 9d.

First metal switch circuits 5a-5d, second
The metal switch circuits 7a to 7d and the third metal switch circuits 9a to 9d are exclusive OR gates 3a.
To 3d input terminals I1, I2, I3, and a power supply 11 for supplying a power supply potential of H level logically, and a logic L
It is for switching and connecting the GND 13 for supplying the GND potential of the level.

2A and 2B are diagrams showing a first metal switch circuit as an example of a switch circuit. FIG. 2A is a state in which it is connected to the power source side, and FIG. 2B is a state in which it is connected to the GND side.
In (A) and (B), (a) is a sectional view, (b) is a plan view, and (c) is a circuit diagram.

For example, a P-type silicon substrate (P-substrate) 1
A field oxide film 107 for element isolation is formed on the surface of 01, and an interlayer insulating film 111 is further formed thereon. The first metal wiring layer is formed on the interlayer insulating film 111, and the power supply 11 is formed via the H level input terminal 114a.
To the GND 13 via the L level input terminal 114b and the H level input wiring 115a connected to the output terminal, and the output wiring connected to the input terminal of the exclusive OR gate 3 via the output terminal 114c. 115c is formed. Aluminum can be given as an example of the material of the first metal wiring layer.

In the state of (A), the H level input wiring 11
5a and the output wiring 115c are electrically connected to each other, and the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3. In the state of (B),
The exclusive OR gate 3 is formed by electrically connecting the L level input wiring 115b and the output wiring 115c.
The GND potential (L level) is input to the input terminal of.

Switching of this first metal switch circuit
This can be performed by changing the exposure mask for forming the first-layer metal wiring layer and selecting the region where the first-layer metal wiring layer is to be formed.

The first metal switch circuits 5a to 5d are shown in FIG.
Each has the same structure as the first metal switch circuit shown in FIG. Although not shown, the second metal switch circuits 7a to 7d have the same structure as the first metal switch circuit shown in FIG. The third metal switch circuits 9a to 9d have the same structure as that of the first metal switch circuit shown in FIG. 2 instead of the first metal wiring layer and the third metal wiring layer. Are formed respectively. Switching of the second metal switch circuits 7a to 7d
This can be performed by changing the exposure mask for forming the second metal wiring layer and selecting the region where the second metal wiring layer is formed. Third metal switch circuit 9
Switching from a to 9d can be performed by changing the exposure mask for forming the third-layer metal wiring layer and selecting the region in which the third-layer metal wiring layer is formed.

Although a metal wiring layer formed by patterning a conductive material formed on the insulating layer by, for example, sputtering is shown here, the metal wiring layer is not limited to this. Alternatively, it may be formed by a damascene method in which a groove is formed in the insulating layer and a conductive material such as copper is embedded in the groove. In that case, the switch circuit can be formed by selecting the groove formation region with the exposure mask for forming the groove.

The set of the exclusive OR gate, the first metal switch circuit, the second metal switch circuit, and the third metal switch circuit form the memory circuits D0 to D3, respectively. In this embodiment, the product information register 1 is a 4-bit register in which the outputs of the four registers D0 to D3 are each 1 bit.

Exclusive OR gates 3a to 3d
The output terminal O1 of is connected to the corresponding wiring of the internal data bus 17 composed of four wirings via the tri-state buffers 15a to 15d provided for each output terminal O1. Tri-state buffers 15a-1
A common read signal line 19 for controlling the operation of the tristate buffers 15a to 15d is connected to 5d.

FIG. 3 shows an example of a circuit diagram around the product information register. In FIG. 3, the tri-state buffer 15a-
The illustration of 15d and the read signal line 19 is omitted.
The read signal input to the read signal input terminal 21 is sent to the address decoder 25 via the buffer 23. An address input signal is also input to the address decoder 25 from the address input terminal 27 via the buffer 29 and the internal address bus 31. The address decoder 25 uses the product information register 1 based on the read signal and the address input signal.
Send register read signal to.

The product information register 1 transmits the stored information to the tri-state buffer 33 via the internal data bus 17 based on the register read signal from the product information register 1. Tri-state buffer 33
Is a product information register 1 based on the read signal input via the read signal input terminal 21 and the buffer 23.
To the terminal 35 connected to the external data bus. Reference numeral 37 is a buffer for fetching information from the external data bus into the internal data bus 17.

Table 1 shows the truth value of the exclusive OR of three inputs. In Table 1, O1 is the output logical value of the output terminal O1, I
1 is the input logical value of the input terminal I1, I2 is the input logical value of the input terminal I2, and I3 is the input logical value of the input terminal I3.
In Table 1, 1 means H level and 0 means L level.

[0058]

[Table 1]

In FIG. 4, the inputs of the memory circuit D0 are I1, I2,
Both I3 indicate a state of logical value 0. The input terminal I of the memory circuit D0 is formed by the first metal switch circuit 5a, the second metal switch circuit 7a, and the third metal switch circuit 9a.
1, I2, and I3 are connected to the GND 13. The output logic level of the output O1 of the exclusive OR gate 3a is L level (logic value 0) (see remarks in Table 1). This state is the initial state.

It is assumed that any one of the inputs to the exclusive OR gate 3a is inverted from the state shown in FIG. For example, as shown in FIG. 5, the first metal switch circuit 5a is switched to connect the input terminal I1 to the power supply 11,
When the input logic level to the input terminal I1 is changed from the L level to the H level, that is, the logic value 0 to 1, the output O1 is inverted from 0 to 1 (see remarks in Table 1).

Further, assume that any one of the inputs to the exclusive OR gate 3a is inverted from the state shown in FIG. For example, as shown in FIG. 6, when the second metal switch circuit 7a is switched to connect the input terminal I2 to the power supply 11 and the input logic level to the input terminal I2 is changed from the L level to the H level, that is, the logic value 0 to 1. , Output O
1 is inverted from 1 to 0 (see remarks in Table 1).

Further, assume that any one of the inputs to the exclusive OR gate 3a is inverted from the state shown in FIG. For example, as shown in FIG. 7, when the third metal switch circuit 9a is switched to connect the input terminal I3 to the power supply 11 and the input logical level to the input terminal I3 is changed from the L level to the H level, that is, the logical value 0 to 1. , The output is inverted from 0 to 1 (see remarks in Table 1).

As described above, the exclusive logic circuit has a property that the logical value of the output can be inverted by inverting the logical value of any one of the input terminals. When the embodiment shown in FIG. 1 is applied to the storage of mask set information, for example, since the product information register 1 has 4 bits, 16 kinds of data of mask set information from 0 to F can be set if expressed in hexadecimal. be able to.

When the data of the mask set information stored in the product information register 1 is updated with the change of the exposure mask forming the mask set, the exposure mask to be changed is, for example, for the first metal wiring layer forming step. Exposure mask,
If the exposure mask for the second-layer metal wiring layer forming process or the exposure mask for the third-layer metal wiring layer forming process or a combination thereof, the data of the mask set information in the product information register 1 is updated at the same time. can do.

For example, when the exposure mask for the first metal wiring layer forming step is changed, the pattern of the portion of the exposure mask corresponding to one or more of the first metal switch circuits 5a to 5d. Is changed to switch one or more of the first metal switch circuits 5a to 5d.
As a result, the exclusive OR gates 3a to 3d
One or more output logical values of
The data of the mask set information stored in the product information register 1 can be updated. As a result, it is possible to solve the problem that the exposure mask, which is not related to the revision of the specifications and the characteristic improvement of the semiconductor integrated circuit device, has to be revised only for updating the register (memory circuit).

As described above, the present invention utilizes this property of the exclusive logic circuit, and a plurality of exposure masks used for manufacturing the semiconductor integrated circuit device are provided at the respective inputs of the exclusive logic circuit. Among them, various switch circuits are provided by providing a memory circuit configured by connecting a plurality of types of switch circuits capable of switching the output logic level to the H level or the L level by only one different exposure mask. Even if any one of the exposure masks corresponding to is revised, the stored contents of the storage circuit can be updated to desired contents.

Although four storage circuits D0 to D3 are provided as the product information register 1 in this embodiment, the present invention is not limited to this, and any number of storage circuits may be used.

Further, in this embodiment, exclusive
A first metal switch circuit and a second metal switch circuit are provided as switch circuits for switching logical inputs to the OR gates 3a to 3d.
Although a metal switch circuit and a third metal switch circuit are provided, the present invention is not limited to this, and a plurality of types of switch circuits for switching the input logic level of the exclusive or gate are used in the manufacturing process. It is only necessary to provide a switch circuit having a configuration that can be switched by changing only one of the plurality of exposure masks, and the exposure mask used for switching the connection is different for each type of switch circuit. .

Further, for example, when the number of exposure masks required for manufacturing a semiconductor integrated circuit device is n (n is an integer), a switchable one is exposed by changing only one different exposure mask. The switch circuits may be provided in the same number n as the number n of masks. If an exclusive logic circuit with the number of input terminals is m (m is an integer) is provided (2 ≦ m ≦ n), when the number of input terminals is m = n, different types of switch circuits are provided for the respective input terminals. When the number of input terminals is m <n, m kinds of switch circuits are selected from the n kinds of switch circuits and connected to the respective input terminals. The combination of m kinds of switch circuits is arbitrary. In addition, the structure of the n kinds of switch circuits is arbitrary, and the input logic level of the exclusive logic circuit is set to the H level by only one of the exposure masks used for manufacturing the semiconductor integrated circuit device. Or L
It does not impose any restrictions other than that the level can be set.

As a method for realizing the logically high level of the input terminal of the exclusive logic circuit by the switch circuit, for example, as shown in FIGS. 1 and 2, between the input terminal of the exclusive logic circuit and the power supply potential, There may be mentioned a method in which the potential of the input terminal is set to the power supply potential by providing a conductive path in the above and setting the input terminal of the exclusive logic circuit and the GND potential to a blocking insulation state.

As a method for realizing the logically L level of the input terminal of the exclusive logic circuit by the switch circuit,
For example, as shown in FIGS. 1 and 2, the input terminal of the exclusive logic circuit and the power supply potential are cut off and insulated, and a conduction path is provided between the input terminal of the exclusive logic circuit and the GND potential. Therefore, a method of setting the potential of the input terminal of the exclusive logic circuit to the GND potential can be given.

In the above embodiment, as the switch circuit,
Although it is possible to select and switch the formation region of the metal wiring layer by changing only the exposure mask for forming the metal wiring, the switch circuit constituting the semiconductor integrated circuit device of the present invention is not limited to this. Instead, a switch circuit that can be switched by changing the exposure mask of only one sheet may be used. For example, if the well region is regarded as a high resistance wiring, it is possible to switch between formation and interruption of the conduction path by selecting the formation region of the well region with one exposure mask. Further, the same can be done depending on the presence or absence of a connection hole such as a contact hole or a through hole. Therefore, in this specification, circuits that logically switch the input of the exclusive logic circuit to the H level or the L level are collectively referred to as a switch circuit. Therefore, the switch circuit may be a transistor switch circuit, or may be an analog circuit or a digital circuit including them.

Some examples of the structure of the switch circuit are shown below. The switch circuit shown below is, for example, a CMO.
It can be applied to a semiconductor integrated circuit device provided with S (Complementally MOS).

FIG. 8 is a diagram showing another example of the switch circuit. FIG. 8A shows a state of being connected to the power source side, FIG. 8B shows a state of being connected to the GND side, and in FIGS. ,
(A) is a sectional view, (b) is a plan view, and (c) is a circuit diagram. This switch circuit can be switched by changing only the well region forming exposure mask.

For example, a P-type silicon substrate (P-substrate) 1
Two N well regions (N well) 103 on the surface side of 01
a and 103b are formed to be electrically separated from each other with a gap. The N well regions 103a and 103b can be used as resistors having an electrically high resistance value.

In the two N well regions 103a and 103b, a total of three N type impurity diffusion regions (N +) 105a,
105b and 105c are formed at intervals.
In (A) and (B), the N-type impurity diffusion region 105
The formation regions of a, 105b, and 105c are common, but N
The formation regions of the well regions 103a and 103b are different. In (A), two N-type impurity diffusion regions 105a and 105c are formed in the N-well region 103a, and one N-type impurity diffusion region 105b is formed in the N-well region 103b. In (B), one N-type impurity diffusion region 105a is formed in the N-well region 103a, and two N-type impurity diffusion regions 105 are formed in the N-well region 103b.
b and 105c are formed.

A field oxide film 107 having openings on N-type impurity diffusion regions 105a, 105b, 105c is formed on the surface of silicon substrate 101, and an interlayer insulating film is formed on the entire surface of silicon substrate 101 including field oxide film 107. 111 (not shown in (B)) is formed.
Contact holes 113a, 113 are formed in the interlayer insulating film 111 on the N-type impurity diffusion regions 105a, 105b, 105c.
b, 113c are formed. Contact hole 11
A conductive material such as tungsten or the same conductive material as that of the first-layer metal wiring layer described later is embedded in 3a, 113b, and 113c.

H is formed on the interlayer insulating film 111 and the contact hole 113a corresponding to the N-type impurity diffusion region 105a.
An H level input wiring 115a connected to the power supply 11 via the level input terminal 114a is formed. The L-level input terminal 114 is formed on the interlayer insulating film 111 and the contact hole 113b corresponding to the N-type impurity diffusion region 105b.
L level input wiring 1 connected to GND 13 via b
15b is formed. Contact hole 1 corresponding to the interlayer insulating film 111 and the N-type impurity diffusion region 105c
The output wiring 115 connected to the input terminal of the exclusive OR gate 3 via the output terminal 114c on 13c.
c is formed. The H level input wiring 115a, the L level input wiring 115b, and the output wiring 115c are formed by the first metal wiring layer.

In the state of (A), the output wiring 115c has a contact hole 113c and an N-type impurity diffusion region 105.
c, N well region 103a, N type impurity diffusion region 105
a is electrically connected to the H level input wiring 115a through the contact hole 113a and the output wiring 11
Since 5c and the L level input wiring 115b are non-conductive,
The power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

In the state of (B), the output wiring 115c has a contact hole 113c and an N-type impurity diffusion region 105.
c, N well region 103b, N type impurity diffusion region 105
b is electrically connected to the L level input wiring 115b through the contact hole 113b and the output wiring 115c and the H level input wiring 115a are not electrically connected to each other.
The ND potential (L level) is input.

This switching of the switch circuit is performed by changing the well region forming exposure mask for defining the formation regions of the N well regions 103a and 103b, and changing the N well region 10 from the exposure mask.
This can be performed by selecting the formation regions of 3a and 103b.

For example, in the manufacturing process of a semiconductor integrated circuit device, the N well regions 103a and 103b are formed by ion implantation using the mask pattern formed on the silicon substrate 101 as a mask. As an exposure mask (referred to as a well region forming exposure mask) used in the photolithography process when forming the mask pattern, only the opening including the formation regions of the N-type impurity diffusion regions 105a and 105c and the N-type impurity diffusion region 105b are formed. By using an exposure mask for forming a mask pattern having an opening including a formation region of (A), it is possible to form a state (A) in which the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3. it can. Conversely, the N-type impurity diffusion regions 105b, 1
05c forming region and N-type impurity diffusion region 1
If an exposure mask for forming a mask pattern having an opening including a formation region of only 05a is used, the state of (B) in which the GND potential (L level) is input to the input terminal of the exclusive OR gate 3 is formed. be able to.

By including this switch circuit, for example, when the specifications of the semiconductor integrated circuit device are changed,
If the exposure mask for forming the well region is changed,
The switch circuit can be switched, and the value of the memory circuit can be updated without using an exposure mask dedicated to updating the value of the memory circuit.

This switch circuit has two N well regions 1
03a and 103b, the formation region of the N well region is not limited to this. For example, a region that covers the N type impurity diffusion regions 105a and 105c or a region that covers the N type impurity diffusion regions 105b and 105c. The switch circuit can be switched by one N well region formed in any of the above.

FIG. 9 is a diagram showing still another example of the switch circuit. FIG. 9A is a state in which the switch circuit is connected to the power source side, and FIG.
In the state of being connected to the ND side, in (A) and (B), (a) is a sectional view, (b) is a plan view, and (c) is a circuit diagram. This switch circuit can be switched by changing only the exposure mask for forming the field oxide film.

For example, a P-type silicon substrate (P-substrate) 1
Two N-type impurity diffusion regions (N +) 10 on the surface side of 01.
5a and 105b are formed at intervals. On the surface of the silicon substrate 101, the N-type impurity diffusion regions 105a,
A field oxide film 107 having an opening is formed on 105b, and an interlayer insulating film 111 (not shown in (B)) is formed on the entire surface of the silicon substrate 101 including the field oxide film 107.

The field oxide film 107 is, for example, LOCO.
It is formed by the S (Local Oxidation of Silicon) method. The N-type impurity diffusion regions 105a and 105b are formed using the field oxide film 107 as a mask by, for example, an ion implantation method or a method of depositing an impurity layer and thermal diffusion, and form the source and drain regions of the N-channel MOSFET. It can be formed at the same time. The N-type impurity diffusion regions 105a and 105b can be used as resistors having a resistance value relatively lower than that of the well regions 103a and 103b shown in FIG.

A total of three contact holes 1 are formed in the interlayer insulating film 111 on the N-type impurity diffusion regions 105a and 105b.
13a, 113b, 113c are formed. A conductive material is embedded in the contact holes 113a, 113b, 113c.

In (A) and (B), the formation regions of the contact holes 113a, 113b, 113c are common, but the formation regions of the field oxide film 107 are different. Further, the formation regions of the N-type impurity diffusion regions 105a and 105b defined by the field oxide film 107 are also different. In (A), two contact holes 113a, 11 are formed on the N-type impurity diffusion region 105a.
3c is formed, and one contact hole 113b is formed on the N-type impurity diffusion region 105b. (B)
Then, one contact hole 113a is formed on the N-type impurity diffusion region 105a.
Two contact holes 113b and 113c are formed on b.

An H level input wiring 115a connected to the H level input terminal 114a is formed on the interlayer insulating film 111 and the contact hole 113a, and an L level input terminal 1 is formed on the interlayer insulating film 111 and the contact hole 113b.
An L level input wiring 115b connected to 14b is formed on the interlayer insulating film 111 and the contact hole 113c.
An output wiring 115c connected to the output terminal 114c is formed on the top.

In the state of (A), the output wiring 115c has a contact hole 113c and an N-type impurity diffusion region 105a.
And the H level input wiring 115a is electrically connected through the contact hole 113a and the output wiring 115.
Since c and the L level input wiring 115b are non-conductive, the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

In the state of (B), the output wiring 115c has a contact hole 113c and an N-type impurity diffusion region 105b.
Since the output wiring 115c and the H level input wiring 115a are not electrically connected to each other via the contact hole 113b and the L level input wiring 115b, the GN is connected to the input terminal of the exclusive OR gate 3.
D potential (L level) is input.

The switching of this switch circuit is performed by changing the field oxide film forming exposure mask for defining the formation region of the field oxide film 107 to change the field oxide film 1
This can be done by selecting the formation area of 07.

For example, in the manufacturing process of a semiconductor integrated circuit device, the field oxide film 107 is formed on the silicon substrate 101 by the LOCOS method to form an oxidation resistant film (silicon nitride film or the like) pattern, and is not covered by the oxidation resistant film pattern. Is formed by selectively oxidizing the region of.

The contact hole 11 is used as an exposure mask (referred to as an exposure mask for forming a field oxide film) used in the photolithography process for forming the oxidation resistant film pattern.
If an exposure mask for separately forming an oxidation resistant film pattern covering the region including the formation regions of 3a and 113c and an oxidation resistant film pattern covering the region including the formation region of only the contact hole 113b is used, (A ), It is possible to form the field oxide film 107 having an opening in each of the region including the formation regions of the contact holes 113a and 113c and the region including the formation region of the contact holes 113b only. It is possible to form the state of (A) in which the power supply potential (H level) is input to the input terminal of.

On the contrary, the contact holes 113b, 113
an oxidation resistant film pattern covering a region including a formation region of c;
If an exposure mask for forming the oxidation resistant film pattern covering the region including the formation region of the contact hole 113a separately is used, as shown in (B), the region including the formation regions of the contact holes 113b and 113c is formed. And the field oxide film 107 having an opening in each of the regions including only the contact hole 113a can be formed, and the GND potential (L level) is input to the input terminal of the exclusive OR gate 3 (B).
Can be formed.

By including this switch circuit, for example, when the specifications of the semiconductor integrated circuit device are changed,
If the exposure mask for forming the field oxide film is changed, the switch circuit can be switched and the value of the storage circuit can be updated without using the exposure mask dedicated to updating the value of the storage circuit.

In this switch circuit, the field oxide film 107 has two N-type impurity diffusion regions 105a and 105b.
However, the opening of the field oxide film and the formation region of the N-type impurity diffusion region are not limited to this, and, for example, the contact hole 113.
a, 113c formation region or contact hole 113
The switching circuit can be switched also by the field oxide film having one opening formed corresponding to one of the formation regions of b and 113c and one N-type impurity diffusion region.

In this switch circuit, P is used as an impurity diffusion region formed using the field oxide film as a mask.
Although the N-type impurity diffusion region formed on the N-type silicon substrate is shown, the impurity diffusion region formed by using the field oxide film as a mask is not limited to this. For example, it is formed in the N-well region. It may be a P-type impurity diffusion region or an N-type impurity diffusion region formed in the P well region.

FIG. 10 is a diagram showing still another example of the switch circuit, in which (A) is a state of being connected to the power source side, (B) is a state of being connected to the GND side, and (A) and (B). 2A is a sectional view, FIG. 2B is a plan view, and FIG. This switch circuit can be switched by changing only the exposure mask for forming the polysilicon film pattern.

For example, a P-type silicon substrate (P-substrate) 1
A field oxide film 107 is formed on the surface of 01. Two polysilicon film patterns 109a and 109b are formed on field oxide film 107 via an insulating film. Polysilicon film patterns 109a and 109b
Is formed at the same time as a polysilicon film pattern as a resistor formed in another region of the semiconductor substrate (not shown).

Polysilicon film patterns 109a and 109
interlayer insulating film 11 on the field oxide film 107
1 is formed. In the figure, the insulating film between the field oxide film 107 and the polysilicon film patterns 109a and 109b and the interlayer insulating film 111 are integrally shown.

Polysilicon film patterns 109a and 109
A total of three contact holes 113a, 113b, 113c are formed in the interlayer insulating film 111 on b. A conductive material is embedded in the contact holes 113a, 113b, 113c.

In (A) and (B), the formation regions of the contact holes 113a, 113b, 113c are common, but the formation regions of the polysilicon film patterns 109a, 109b are different. In (A), two contact holes 113a are formed on the polysilicon film pattern 109a.
113c is formed, and the polysilicon film pattern 109b is formed.
One contact hole 113b is formed above. In (B), 1 is formed on the polysilicon film pattern 109a.
Two contact holes 113a are formed, and two contact holes 11 are formed on the polysilicon film pattern 109b.
3b and 113c are formed.

An H level input wiring 115a connected to the H level input terminal 114a is formed on the interlayer insulating film 111 and the contact hole 113a, and an L level input terminal 1 is formed on the interlayer insulating film 111 and the contact hole 113b.
An L level input wiring 115b connected to 14b is formed on the interlayer insulating film 111 and the contact hole 113c.
An output wiring 115c connected to the output terminal 114c is formed on the top.

In the state of (A), the output wiring 115c includes the contact hole 113c and the polysilicon film pattern 10.
9a and the contact hole 113a, it is electrically connected to the H level input wiring 115a, and further the output wiring 1
Since 15c and the L level input wiring 115b are non-conductive, the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

In the state of (B), the output wiring 115c includes the contact hole 113c and the polysilicon film pattern 10.
It is electrically connected to the L level input wiring 115b through 9b and the contact hole 113b, and the output wiring 115c and the H level input wiring 115a are non-conducting. Therefore, the input terminal of the exclusive OR gate 3 is connected to the GND potential ( L level) is input.

The switching of the switch circuit is performed by changing the exposure mask for forming the polysilicon film patterns 109a and 109b to select the formation regions of the polysilicon film patterns 109a and 109b. It can be done by doing.

For example, in a manufacturing process of a semiconductor integrated circuit device, for example, CVD is performed on the entire surface of the field oxide film 107.
After forming a polysilicon film by (Chemical Vapor Deposition) method, a resist pattern is formed on the polysilicon film by photolithography, and the polysilicon film is patterned by using the resist pattern as a mask by etching technology. Silicon film pattern 109
Polysilicon film patterns for a and 109b and resistors (not shown) are formed. Ion implantation for controlling the resistance value of the resistor is performed before or after patterning the polysilicon film.

Areas where contact holes 113a and 113c are formed as an exposure mask (referred to as an exposure mask for forming a polysilicon film pattern) used in a photolithography process for forming a resist pattern used as a mask when patterning a polysilicon film. If an exposure mask for forming a resist pattern is used in the region including the region and the region including only the contact hole 113b,
As shown in (A), the contact holes 113a, 11a
Polysilicon film pattern 1 in the region including the formation region of 3c
09a can be formed, and the polysilicon film pattern 109b can be formed in a region including the formation region of only the contact hole 113b, so that the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3. be able to.

On the contrary, the contact holes 113b, 113
A region including the formation region of c and the contact hole 113
By using an exposure mask for forming a resist pattern in a region including a formation region of only a, a polysilicon film pattern 109a is formed in a region including a formation region of only contact hole 113a, as shown in FIG. The polysilicon film pattern 109b can be formed in a region including the formation regions of the contact holes 113b and 113c, and the GN is formed in the input terminal of the exclusive OR gate 3.
A state in which the D potential (L level) is input can be formed.

By including this switch circuit, for example, when the specifications of the semiconductor integrated circuit device are changed,
If the exposure mask for forming the polysilicon film pattern is changed, the switch circuit can be switched and the value of the storage circuit can be updated without using the exposure mask dedicated to updating the value of the storage circuit.

In this switch circuit, the polysilicon film patterns 109a and 109b formed at the same time as the polysilicon film pattern as the resistor are used, but the polysilicon film pattern is not limited to this and, for example, MOSFETs are used. You may use the polysilicon film pattern formed simultaneously with this gate electrode.

FIG. 11 is a diagram showing still another example of the switch circuit. (A) shows a state of being connected to the power source side, (B) shows a state of being connected to the GND side, and (A) and (B). 2A is a sectional view, FIG. 2B is a plan view, and FIG. This switch circuit can be switched by changing only the exposure mask for forming the N-type impurity diffusion region.

For example, a P-type silicon substrate (P-substrate) 1
Two N-type impurity diffusion regions (N +) 10 on the surface side of 01.
5a and 105b are formed at intervals. On the surface of the silicon substrate 101, the N-type impurity diffusion regions 105a,
Field oxide film 1 having an opening in the formation region of 105b and the region between N-type impurity diffusion regions 105a and 105b.
07, an interlayer insulating film 111 (not shown in (B)) is formed on the entire surface of the silicon substrate 101 including the field oxide film 107.

The N-type impurity diffusion regions 105a and 105b are formed by using a resist pattern mask (not shown) formed on the field oxide film 107 and the silicon substrate 101 by, for example, an ion implantation method, and are sources of the N-channel MOSFET. And the drain region can be formed at the same time.

A total of three contact holes 1 are formed in the interlayer insulating film 111 on the N-type impurity diffusion regions 105a and 105b.
13a, 113b, 113c are formed. A conductive material is embedded in the contact holes 113a, 113b, 113c.

In (A) and (B), the formation regions of the contact holes 113a, 113b, 113c are common, but the formation regions of the N-type impurity diffusion regions 105a, 105b are different. In (A), N-type impurity diffusion region 1
Two contact holes 113a and 113c on 05a
And one contact hole 113b is formed on the N-type impurity diffusion region 105b. In (B), one contact hole 113a is formed on the N-type impurity diffusion region 105a, and two contact holes 113b and 113c are formed on the N-type impurity diffusion region 105b.

An H level input wiring 115a connected to the H level input terminal 114a is formed on the interlayer insulating film 111 and the contact hole 113a, and an L level input terminal 1 is formed on the interlayer insulating film 111 and the contact hole 113b.
An L level input wiring 115b connected to 14b is formed on the interlayer insulating film 111 and the contact hole 113c.
An output wiring 115c connected to the output terminal 114c is formed on the top.

In the state of (A), the output wiring 115c has a contact hole 113c and an N-type impurity diffusion region 105a.
And the H level input wiring 115a is electrically connected through the contact hole 113a and the output wiring 115.
Since c and the L level input wiring 115b are non-conductive, the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

In the state of (B), the output wiring 115c has a contact hole 113c and an N-type impurity diffusion region 105b.
Since the output wiring 115c and the H level input wiring 115a are not electrically connected to each other via the contact hole 113b and the L level input wiring 115b, the GN is connected to the input terminal of the exclusive OR gate 3.
D potential (L level) is input.

This switching of the switch circuit is performed by changing the N-type impurity diffusion region forming exposure mask for demarcating the formation regions of the N-type impurity diffusion regions 105a and 105b.
This can be performed by selecting the formation region of the type impurity diffusion region.

For example, in the manufacturing process of the semiconductor integrated circuit device, the N-type impurity diffusion regions 105a and 105b are formed on the field oxide film 107 and the region surrounded by the field oxide film 107 by the photoengraving technique on the silicon substrate 101. It is formed by the ion implantation method using the resist pattern as a mask. This resist pattern is formed, for example, in another region (not shown) of the silicon substrate 101 so as to have an opening in the formation region of the N-channel MOSFET and cover the formation region of the P-channel MOSFET. And used as a mask for forming the drain region.

The contact hole 11 is used as an exposure mask (referred to as an N-type impurity diffusion region forming exposure mask) used in the photolithography process for forming the resist pattern.
3a, 113c has an opening in a region including the formation region,
If an exposure mask for forming a resist pattern having an opening in a region including only the contact hole 113b is used, as shown in FIG. 9A, an N-type resist is formed in the region including the contact holes 113a and 113c. The impurity diffusion region 105a is formed, and the contact hole 113 is formed.
The N-type impurity diffusion region 10 is formed in the region including the formation region of only b.
5b can be formed, and a state in which the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3 can be formed.

On the contrary, the contact holes 113b, 113
If an exposure mask for forming a resist pattern having an opening in a region including the formation region of c and an opening in a region including only the formation region of the contact hole 113a is used, as shown in FIG. The N-type impurity diffusion region 105a is formed in a region including the formation region of only the hole 113a.
And an N-type impurity diffusion region 105b can be formed in a region including the formation regions of the contact holes 113b and 113c, and a state in which the GND potential (L level) is input to the input terminal of the exclusive OR gate 3 is formed. can do.

By including this switch circuit, for example, when the specifications of the semiconductor integrated circuit device are changed,
If the exposure mask for forming the N-type impurity diffusion region is changed, the switch circuit can be switched and the value of the storage circuit can be updated without using the exposure mask dedicated to updating the value of the storage circuit.

In this switch circuit, the N-type impurity diffusion region formed on the P-type silicon substrate is shown as the impurity diffusion region, but the field oxide film and the resist pattern are used as a mask, or only the resist pattern is masked. The impurity diffusion region formed as described above is not limited to this, and may be, for example, a P-type impurity diffusion region formed in the N well region, or an N-type impurity formed in the P well region. It may be a diffusion region.

FIG. 12 is a diagram showing still another example of the switch circuit. (A) shows a state of being connected to the power source side, (B) shows a state of being connected to the GND side, and (A) and (B). 2A is a sectional view, FIG. 2B is a plan view, and FIG. This switch circuit can be switched by changing only the contact hole forming exposure mask.

For example, a P-type silicon substrate (P-substrate) 1
A field oxide film 107 is formed on the surface of 01. A polysilicon film pattern 109 is formed on field oxide film 107 via an insulating film. The polysilicon film pattern 109 is formed simultaneously with, for example, a polysilicon film pattern as a resistor formed in another region of a semiconductor substrate (not shown).

An interlayer insulating film 111 (not shown in (B)) is formed on the field oxide film 107 including the polysilicon film pattern 109. In the figure, the insulating film between the field oxide film 107 and the polysilicon film pattern 109 and the interlayer insulating film 111 are integrally shown.

A total of two contact holes 113a are formed in the interlayer insulating film 111 on the polysilicon film pattern 109.
113c or 113b, 113c are formed. A conductive material is embedded in the contact holes 113a, 113b, 113c.

An H level input wiring 115a connected to the H level input terminal 114a is formed on the interlayer insulating film 111 and a contact hole 113a forming region, and an L level is formed on the interlayer insulating film 111 and a contact hole 113b forming region.
L level input wiring 1 connected to the level input terminal 114b
15b is formed, and the output wiring 115c connected to the output terminal 114b is formed on the interlayer insulating film 111 and in the formation region of the contact hole 113c.

In (A) and (B), the formation regions of the polysilicon film pattern 109, the H level input wiring 115a, the L level input wiring 115b, and the output wiring 115c are common, but the formation areas of the contact holes are different. There is. In (A), on the polysilicon film pattern 109,
Polysilicon film pattern 109 and H level input wiring 11
Contact hole 113 for electrically connecting 5a
a, the polysilicon film pattern 109, and the output wiring 115
contact hole 113c for electrically connecting c
Is formed. In (B), the polysilicon film pattern 10
A contact hole 113b for electrically connecting the polysilicon film pattern 109 and the L level input wiring 115b and a contact hole 113c for electrically connecting the polysilicon film pattern 109 and the output wiring 115c are formed on the substrate 9. To be done.

In the state of (A), the output wiring 115c includes the contact hole 113c and the polysilicon film pattern 10.
9 and the contact hole 113a, electrically connected to the H level input wiring 115a, and further connected to the output wiring 11
Since 5c and the L level input wiring 115b are non-conductive,
The power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

In the state of (B), the output wiring 115c includes the contact hole 113c and the polysilicon film pattern 10.
9 is electrically connected to the L-level input wiring 115b through the contact hole 113b and the output wiring 115c and the H-level input wiring 115a are not electrically connected to each other.
The ND potential (L level) is input.

The switching of the switch circuit is performed by changing the contact hole forming exposure mask for defining the forming regions of the contact holes 113a, 113b, 113c, and selecting the forming region of the contact hole opened in the insulating interlayer film 111. It can be done by doing.

For example, in the manufacturing process of a semiconductor integrated circuit device, the contact holes 113a, 113b, 113c.
Is formed by forming a resist pattern on the interlayer insulating film 111 by a photolithography technique and selectively removing the interlayer insulating film 111 by using the resist pattern as a mask by an etching technique.

Contact holes 113a, 113b, 1
As an exposure mask (referred to as a contact hole forming exposure mask) used in a photolithography process for forming a resist pattern used as an etching mask when forming 13c, an H level input is performed in the formation region of the polysilicon film pattern 109. Wiring 115a and output wiring 115
If an exposure mask for forming a resist pattern having an opening corresponding to the formation region of c is used, the polysilicon film 109 and the H level input wiring 11 can be formed as shown in FIG.
Contact hole 113 for electrically connecting 5a
a, a contact hole 113c for electrically connecting the polysilicon film 109 and the output wiring 115c can be formed, and a state in which the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3 is formed. can do.

On the contrary, if an exposure mask for forming a resist pattern having openings in the formation region of the polysilicon film pattern 109 and corresponding to the formation regions of the L level input wiring 115b and the output wiring 115c is used, (B)
As shown in FIG. 6, a contact hole 113b for electrically connecting the polysilicon film 109 and the L level input wiring 115b, and the polysilicon film 109 and the output wiring 115.
contact hole 113c for electrically connecting c
Can be formed, and a state in which the GND potential (L level) is input to the input terminal of the exclusive OR gate 3 can be formed.

By including this switch circuit, for example, when the specifications of the semiconductor integrated circuit device are changed,
If the exposure mask for forming the contact hole is changed, the switch circuit can be switched and the value of the storage circuit can be updated without using the exposure mask dedicated to updating the value of the storage circuit.

In this switch circuit, the output wiring 115c is connected to the H level input wiring 115a through the contact hole.
Alternatively, the polysilicon film pattern 109 formed at the same time as the polysilicon film pattern as the resistor is used as a conductor for electrically connecting to the L level input wiring 115b, but the conductor is not limited to this. not,
For example, a polysilicon film pattern formed at the same time as the gate electrode of the MOSFET may be used, or an N type or P type impurity diffusion region formed in the silicon substrate 101 may be used.

Further, in this switch circuit, the contact hole is used as the connection hole, but the connection hole is not limited to this, and the lower metal wiring layer and the upper metal wiring layer are electrically connected. Therefore, it may be a through hole or a via hole provided in the interlayer insulating film. In the present specification, the term “exposure mask for forming a connection hole” includes an exposure mask for forming a contact hole and an exposure mask used in a photolithography process for forming a resist pattern used as an etching mask when forming a via hole.

FIG. 13 is a diagram showing still another example of the switch circuit. (A) shows a state of being connected to the power source side, (B) shows a state of being connected to the GND side, and (A) and (B). 2A is a sectional view, FIG. 2B is a plan view, and FIG. This switch circuit can be switched by changing only the depletion implantation exposure mask.

For example, a P-type silicon substrate (P-substrate) 1
N-channel MOSFET formation region 1 on the surface side of 01
Each of 17a and 117b has a source region 105s and a drain region 1 formed of an N-type impurity diffusion region (N +).
05d are formed at intervals. Silicon substrate 1
On the surface of 01, the N-channel MOSFET formation region 11
A field oxide film 107 having an opening is formed in each of 7a and 117b.

N-channel MOSFET forming region 117
In a and 117b, the gate electrode 121 is formed on the silicon substrate 101 between the source region 105s and the drain region 105d via the gate oxide film 119. An interlayer insulating film 111 is formed on the silicon substrate 1 including the field oxide film 107 and the gate electrode 121.

The source region 105s is formed on the interlayer insulating film 111.
Corresponding to the contact hole 113s, and the contact hole 113d corresponding to the drain region 105d.
And a contact hole 113g is formed corresponding to the gate electrode 121. Contact hole 11
A conductive material is embedded in 3s, 113d, and 113g.

On the contact hole 113d of the MOSFET formation region 117a and on the interlayer insulating film 111, an H level input wiring 115a connected to the power supply 11 via the H level input terminal 114a is formed. MOSFET
An L level input wiring 115b connected to the GND 13 via an L level input terminal 114b is formed on the contact hole 113s in the formation region 117b and on the interlayer insulating film 111. Via the L level input wiring 115b,
N-channel type MOSF of MOSFET formation region 117b
The ET source 105s and the gate electrode 121 are electrically connected.

Contact holes 113s and 113g in the MOSFET formation region 117a, MOSFET formation region 1
An output wiring 115c connected to the input terminal of the exclusive OR gate 3 via the output terminal 114c is formed on the contact hole 113d of 17b and the interlayer insulating film. Through the output wiring 115c, the MOSFE
The source 105s of the N-channel MOSFET in the T formation region 117a and the gate electrode 121 are electrically connected.

MOSFET formation region 117a or 117
A depletion implantation region 123, in which an N-type impurity is implanted into the surface of the silicon substrate 101, is formed between the source region 105s and the drain region 105d in either one of b.

In (A) and (B), the formation region of the depletion implantation region 123 is different. In (A), the source region 105s of the MOSFET formation region 117a is
A depletion injection region 123 is formed between the drain region 105d and the drain region 105d, a depletion type N-channel type MOSFET is formed in the MOSFET forming region 117a, and an enhancement type N-channel type MOSFET is formed in the MOSFET forming region 117b. (B)
Then, the source region 105 of the MOSFET formation region 117b
s and the drain region 105d, the depletion injection region 123 is formed, and the MOSFET formation region 117a is formed.
An enhancement-type N-channel MOSFET is formed in, and a depletion-type N-channel MOSFET is formed in the MOSFET formation region 117b.

In the state (A), the depletion type N-channel MOSFET of the MOSFET formation region 117a is formed.
Is on, and the enhancement-type N-channel MOSFET in the MOSFET formation region 117b is off, so that the output wiring 115c is in the contact hole 11
3s, source region 105s, depletion implantation region 1
23, drain region 105d and contact hole 11
3d, electrically connected to the H level input wiring 115a, and further connected to the output wiring 115c and the L level input wiring 11
Since 5b is non-conductive, the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

In the state of (B), the depletion type N-channel MOSFET of the MOSFET formation region 117b is formed.
Is on, and the enhancement-type N-channel MOSFET in the MOSFET formation region 117a is off, so that the output wiring 115c is in the contact hole 11.
3d, drain region 105d, depletion implantation region 123, source region 105s and contact hole 11
Electrically connected to the L level input wiring 115b through 3s, and further connected to the output wiring 115c and the H level input wiring 11
Since 5a is non-conductive, the GND potential (L level) is input to the input terminal of the exclusive OR gate 3.

This switching of the switch circuit is performed by changing the depletion implantation exposure mask for defining the formation region of the depletion implantation region 123 and selecting whether the MOSFET is the enhancement type or the depletion type. be able to.

For example, in the manufacturing process of a semiconductor integrated circuit device, the depletion implantation region 123 is ion-implanted by using the resist pattern formed on the silicon substrate 101 in the region surrounded by the field oxide film 107 by photolithography as a mask. Is formed by.

As an exposure mask used in the photolithography process for forming the resist pattern (referred to as an exposure mask for depletion implantation), the MOSFET formation region 11 is formed.
7a has an opening in the region between the source region 105s and the drain region 105d, and the MOSFET formation region 117b
If an exposure mask for forming a resist pattern covering the region between the source region 105s and the drain region 105d is used, the depletion type N-channel type MOSFE is formed in the MOSFET formation region 117a as shown in FIG.
T can form an enhancement type N-channel MOSFET in the MOSFET formation region 117b,
It is possible to form a state in which the power supply potential (H level) is input to the input terminal of the exclusive OR gate 3.

On the contrary, the source region 10 of the MOSFET formation region 117b is covered by covering the region between the source region 105s and the drain region 105d of the MOSFET formation region 117a.
If an exposure mask for forming a resist pattern having an opening in the region between 5s and the drain region 105d is used, as shown in FIG.
enhancement type N-channel MOSFET in a
A depletion type N-channel MOSFET can be formed in the MOSFET formation region 117b, and a state in which the GND potential (L level) is input to the input terminal of the exclusive OR gate 3 can be formed.

By including this switch circuit, for example, when the specifications of the semiconductor integrated circuit device are changed,
If the depletion implantation exposure mask is changed, the switch circuit can be switched and the value of the memory circuit can be updated without using the exposure mask dedicated to updating the value of the memory circuit.

In the switch circuit described above, the case where the P-type silicon substrate is used has been described, but the present invention is not limited to this, and when the N-type silicon substrate is used, It can be applied by forming the switch circuit shown in (1) with impurities of the opposite conductivity type.

As described above with respect to some examples of the structure of the switch circuit, using only one of all the exposure masks used for manufacturing the semiconductor integrated circuit device, It is possible to configure a switch circuit that logically switches the input of the exclusive logic circuit to the H level or the L level.

However, the structure of the switch circuit is not limited to that shown above, and any one of all the exposure masks used in the manufacturing process may be used as a single exposure mask. As long as it can switch the input potential of the exclusive logic circuit only by itself, it can be used for the memory circuit constituting the semiconductor integrated circuit device of the present invention.

As described above, the exclusive logic circuit has the property that the logical value of the output can be inverted by inverting the logical value of any one of its input terminals. , The output logic level of each of the exclusive logic circuits is set to the H level or the L level by using only one different exposure mask among the exposure masks used for manufacturing the semiconductor integrated circuit device.
By providing a memory circuit configured by connecting different switch circuits that can be switched to different levels, the memory content of the memory circuit is desired regardless of which one exposure mask is revised. It becomes possible to update the contents of.

An embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention will be described. For each semiconductor integrated circuit device manufactured using the same set of a plurality of exposure masks using the switch circuit and the storage circuit described above. The connection of a plurality of switch circuits is set in and the product information is recorded in the storage circuit.

Then, for example, when the specifications of the semiconductor integrated circuit device are changed, the characteristics are improved, or the option function is added, a predetermined switch circuit is changed by changing the exposure mask necessary for changing the specifications, the characteristics, or the option function. The value of the memory circuit is updated by switching the connection.

Although the embodiments of the present invention have been described above, the arrangement of the switch circuits may correspond to, for example, all the exposure masks forming the mask set, or some of the exposure masks forming the mask set. It is also possible to correspond only to the exposure mask of.

Further, in the above embodiment, the number of input terminals of the exclusive OR gates 3a to 3d is three, but the present invention is not limited to this, and the exclusive OR gate has at least two input terminals. Should be provided.

The information that can be stored by the semiconductor integrated circuit device and the method of manufacturing the same according to the present invention is not limited to the mask set information, but can be applied to the storage of other product information such as the type of chip. it can.

In the above embodiment, the value of the product information register 1 is directly read out via the data bus 17, but the present invention is not limited to this. For example, the value of the product information register 1 is The value of the product information register may be read by another reading method such as reading via the encoder.

In the above embodiment, the exclusive OR gate is used as the exclusive logic circuit.
The present invention is not limited to this, and an exclusive NOR gate may be used. Exclusive
The output of the NOR gate is inverted compared to the exclusive OR gate.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications can be made within the scope of the present invention described in the claims.

[0170]

In the semiconductor integrated circuit device according to the first and second aspects, the exclusive logic circuit and the input logic level of the exclusive logic circuit are set to the H level or the L level. Since the memory circuit including the plurality of types of switch circuits that can be switched by changing only one different exposure mask is provided, any one of the plurality of types of switch circuits that configures the memory circuit can be used. Since the memory circuit can be updated by changing the exposure mask, that is, by changing any one of the exposure masks, the value of the memory circuit can be updated only by changing the exposure mask necessary for changing the specifications.

According to another aspect of the semiconductor integrated circuit device of the present invention, one of the switch circuits has an H level input terminal or an L level output terminal depending on the well region formation region.
Since the switch is connected to the level input terminal by switching, and the switch capable of switching is provided only by changing the well region forming exposure mask, the memory circuit can be adapted to the change of the well region forming exposure mask. The value of can be updated.

According to another aspect of the semiconductor integrated circuit device of the present invention, as one type of the switch circuit, the output terminal is at the H level by the formation region of the impurity diffusion region formed in the semiconductor substrate using the field oxide film as a mask. The exposure mask for field oxide film formation is changed by connecting to the input terminal or the L-level input terminal by switching, and the changeable exposure mask for field oxide film formation is provided. The value of the memory circuit can be updated corresponding to

According to another aspect of the semiconductor integrated circuit device of the present invention, as one type of the switch circuit, the output terminal is switched to the H level input terminal or the L level input terminal depending on the region where the polysilicon film pattern is formed. Since it has a switch that can be switched by changing only the exposure mask for forming the polysilicon film pattern, the value of the memory circuit is updated in response to the change in the exposure mask for forming the polysilicon film pattern. can do.

According to another aspect of the semiconductor integrated circuit device of the present invention, as one type of the switch circuit, the output terminal is switched and connected to the H level input terminal or the L level input terminal depending on the formation region of the metal wiring layer. Is something
Since a switchable switch is provided by changing only the metal wiring forming exposure mask, the value of the memory circuit can be updated in response to the change of the metal wiring forming exposure mask.

In the semiconductor integrated circuit device according to the seventh aspect, it is preferable that each of the plurality of metal wiring layers is provided with the switch circuit which can be switched by changing only the exposure mask for forming the metal wiring. As a result, in the semiconductor integrated circuit device having the multi-layer metal wiring structure, the value of the memory circuit can be updated in response to the change of any metal wiring layer.

According to another aspect of the semiconductor integrated circuit device of the present invention, as one type of the switch circuit, the output terminal is formed by the formation region of the impurity diffusion region formed in the semiconductor substrate using the impurity introduction mask pattern as a mask. The mask pattern for impurity introduction is designed to be connected to the H level input terminal or the L level input terminal by switching and to be switched by changing only the exposure mask for forming the impurity introduction mask pattern. The value of the memory circuit can be updated corresponding to the change of the formation exposure mask.

According to a ninth aspect of the semiconductor integrated circuit device of the present invention, as one type of the switch circuit, the output terminal is H level by the formation region of the connection hole formed on the impurity diffusion region or the insulating film on the conductive material. The exposure mask for connection hole formation is changed by connecting to the level input terminal or the L level input terminal by switching, and the changeable exposure mask for connection hole formation is provided. The value of the memory circuit can be updated correspondingly.

In the semiconductor integrated circuit device according to the tenth aspect, one of the switch circuits is an enhancement type MOSFET or a depletion type MOSF.
The output terminal is an enhancement type MOSFET or a depletion type MO depending on the formation region of the impurity implantation region for forming the depletion type MOSFET.
An exposure mask for depletion injection is provided which is switched and connected to the H level input terminal or the L level input terminal via the SFET, and is provided with a switchable one by changing only the depletion injection exposure mask. The value of the memory circuit can be updated in response to the change of.

In the semiconductor integrated circuit device according to the eleventh aspect, since the plurality of storage circuits are provided, the amount of information that can be stored is increased and versatility is increased.

Since the semiconductor integrated circuit device according to the twelfth aspect is further provided with an external output circuit for outputting the output logical value of the exclusive logic circuit to the outside, the external output circuit is provided. The output logic value of the exclusive logic circuit can be read out via the. When the external output circuit is provided with an encoder, it is possible to reduce the number of wirings of a wiring circuit such as an internal data bus forming the external output circuit.

In the semiconductor integrated circuit device according to the thirteenth aspect, since the product information is stored as the information stored in the storage circuit, the exposure necessary for changing the specifications, improving the characteristics, adding the optional function, etc. Product information can be updated simply by changing the mask. Examples of product information include mask set information and chip type information.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, wherein the memory circuit constituting the semiconductor integrated circuit device of the present invention is used and a plurality of exposure masks of the same set are used to manufacture the semiconductor integrated circuit device. Since the connection of the switch circuit is set for each device and the information is recorded in the memory circuit, for example, for each semiconductor integrated circuit device manufactured by using a plurality of exposure masks of the same set, for example, specification information and characteristic improvement Information such as product information including information can be recorded.

In the method of manufacturing a semiconductor integrated circuit device according to the fifteenth aspect, the output terminal of the switch circuit corresponding to the changed exposure mask is switched to the H level input terminal or the L level input terminal, and the exclusive logic circuit is operated. Since the output logic level of is changed, the value of the memory circuit can be updated only by changing the exposure mask necessary for changing the specifications of the semiconductor integrated circuit device. It is possible to solve the problem that a missing exposure mask has to be revised only for updating the memory circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment.

FIG. 2 is a diagram showing a first metal switch circuit as an example of a switch circuit, in which (A) is a state of being connected to a power supply side, (B) is a state of being connected to a GND side, and (A) and ( In (B), (a) is a sectional view, (b) is a plan view,
(C) shows a circuit diagram.

FIG. 3 is a circuit diagram showing an example of a peripheral portion of the same embodiment.

FIG. 4 is a circuit diagram showing a state in which inputs to a memory circuit D0 are logical values 0 for I1, I2, and I3.

5 is a circuit diagram showing a state in which an input of an input terminal I1 is changed from a logical value of 0 to 1 from the state of FIG.

6 is a circuit diagram showing a state in which an input of an input terminal I2 is changed from a logical value 0 to 1 from the state of FIG.

7 is a circuit diagram showing a state in which an input of an input terminal I3 is changed from a logical value 0 to 1 from the state of FIG.

FIG. 8 is a diagram showing another example of the switch circuit, which can be switched only by the well region forming exposure mask.

FIG. 9 is a diagram showing another example of the switch circuit, which can be switched only by the exposure mask for forming a field oxide film.

FIG. 10 is a diagram showing another example of the switch circuit, which can be switched only by the exposure mask for forming the polysilicon film pattern.

FIG. 11 is a diagram showing another example of the switch circuit, which can be switched only by the N-type impurity diffusion region forming exposure mask.

FIG. 12 is a diagram showing another example of the switch circuit, which can be switched only by the exposure mask for forming the connection hole.

FIG. 13 is a diagram showing another example of the switch circuit, which can be switched only by the exposure mask for depletion implantation.

FIG. 14 is a circuit diagram showing a conventional example.

FIG. 15 is a circuit diagram showing another conventional example.

[Explanation of symbols]

1 register 3a, 3b, 3c, 3d exclusive logic circuit 5a, 5b, 5c, 5d first metal switch circuit 7a, 7b, 7c, 7d second metal switch circuit 9a, 9b, 9c, 9d third metal switch circuit 11 Power supply 13 GND 15a, 15b, 15c, 15d Tri-state buffer 17 Internal data bus 19 Read signal line

Claims (15)

[Claims] 1. An exclusive logic circuit and a plurality of switches for setting an input logic level of the exclusive logic circuit to an H level or an L level, which can be switched by changing only one different exposure mask. A semiconductor integrated circuit device having a memory circuit composed of various types of switch circuits. 2. The semiconductor integrated circuit device according to claim 1, wherein the switch circuits of different types are connected to different input terminals of the exclusive logic circuit. 3. One of the switch circuits is one in which an output terminal is switched and connected to an H level input terminal or an L level input terminal depending on a well region forming region, and only a well region forming exposure mask is provided. The semiconductor integrated circuit device according to claim 1 or 2, which can be switched by changing. 4. One of the switch circuits is connected by switching an output terminal to an H level input terminal or an L level input terminal depending on a region where an impurity diffusion region is formed in a semiconductor substrate using a field oxide film as a mask. 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device can be switched by changing only an exposure mask for forming a field oxide film. 5. One of the switch circuits is one for switching an output terminal to an H level input terminal or an L level input terminal depending on a region where a polysilicon film pattern is formed. 2. The changeover can be made by changing only the exposure mask.
5. The semiconductor integrated circuit device according to any one of 1 to 4. 6. One of the switch circuits is one in which an output terminal is switched and connected to an H level input terminal or an L level input terminal depending on a formation region of a metal wiring layer, and only an exposure mask for forming a metal wiring is provided. 6. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device can be switched by changing. 7. The semiconductor integrated circuit device according to claim 6, wherein each of the plurality of metal wiring layers is provided with the switch circuit that can be switched by changing only a metal wiring forming exposure mask. 8. One of the switch circuits has an H level output terminal due to a formation region of an impurity diffusion region formed in a semiconductor substrate using an impurity introduction mask pattern as a mask.
8. The semiconductor integrated device according to claim 1, wherein the semiconductor integrated circuit is connected to a level input terminal or an L level input terminal by switching, and can be switched by changing only an exposure mask for forming a mask pattern for impurity introduction. Circuit device. 9. One of the switch circuits has an H level input terminal or an L level output terminal depending on a region where a connection hole is formed in an insulating film on an impurity diffusion region or a conductive material.
9. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is switched and connected to a level input terminal, and can be switched by changing only a connection hole forming exposure mask. 10. One of the switch circuits is an enhancement type MOSFET or a depletion type MO.
The SFET is provided, and the output terminal is switched and connected to the H level input terminal or the L level input terminal through the enhancement type MOSFET or the depletion type MOSFET by the formation region of the impurity implantation region for forming the depletion type MOSFET. 10. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device can be switched by changing only an exposure mask for depletion implantation. 11. The semiconductor integrated circuit device according to claim 1, comprising a plurality of the memory circuits. 12. The semiconductor integrated circuit device according to claim 1, further comprising an external output circuit for outputting the output logical value of the exclusive logic circuit to the outside. 13. The semiconductor integrated circuit device according to claim 1, wherein the storage circuit stores product information. 14. The connection of the switch circuit is set for each semiconductor integrated circuit device manufactured by using the memory circuit according to claim 1 and using a plurality of exposure masks of the same set. And a method for manufacturing a semiconductor integrated circuit device for recording information in the memory circuit. 15. The semiconductor integrated device according to claim 14, wherein the output terminal of the switch circuit corresponding to the changed exposure mask is switched to an H level input terminal or an L level input terminal to switch the output logic level of the exclusive logic circuit. Method of manufacturing circuit device.