JP2658829B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of laying out a semiconductor integrated circuit, and more particularly to a method of laying out a functional block for optimizing the driving capability of function blocks and arranging and wiring.

[0002]

2. Description of the Related Art In a gate array, a block size and connection positions of a power supply terminal, a ground terminal, and a signal input / output terminal are unified according to a predetermined standard, and these various functional blocks are regularly arranged in a matrix in advance. In addition, a wafer that is fixedly arranged and completed up to the substrate process is prepared. By combining these various functional blocks arranged on this wafer, only the connection wiring connecting these functional blocks is completed using a wiring mask in order to realize a one-chip integrated circuit device having a predetermined function. It is made to let.

In designing the gate array, a desired function block is selected and designed from a library of function blocks prepared in advance in consideration of the load capacity of the function block, the timing of signal change, and the like. After design, D
An RC (Design Rule Check) is executed by the host computer to verify a load capacity limitation error and the like, and verify a timing error by a logic simulation. If an error is detected here, the circuit is reviewed and the same check is repeated to complete the design of the complete gate array.

Recently, this gate array has been highly integrated,
The scale is rapidly increasing, and the circuit configuration for supplying the output signal of one functional block to many functional blocks is also increasing. However, the drive capability has been reduced due to the reduction in transistor size accompanying the high integration, and the switching speed is reduced when the load capacity is increased.

[0005] Therefore, in order to be able to cope with any circuit configuration, even with the same function, a small number of transistors are used and a functional block with a low driving capability, or a large number of transistors and a large driving capability are used. Like functional blocks, many blocks must be prepared for each specification as a library.

[0006] Therefore, if each function is prepared for each specification even if the function is not so complicated, a library of function blocks becomes enormous, and a circuit designer manually selects an optimum function block from among them. It is difficult to choose.

An example of a method for facilitating these operations is described in Japanese Patent Application Laid-Open No. 61-6850. FIG. 8 shows a block for enhancing the driving capability of this conventional functional block.
, The functional block A includes a functional unit A1 and a buffer unit A2. When designing the gate array, the load capacity connected to the output terminal AOUT of this block is calculated, and the buffer section A2 is replaced with a buffer section having an optimum driving capability. In this case, the output terminal AOUT is a terminal that has already been determined independently of the buffer unit A2. For example, if the functional block A must supply signals to a large number of blocks, the buffer unit A2 has a high driving capability. It is replaced by a buffer unit, and signals are supplied to all functional blocks from one terminal of the output terminal AOUT.

At this time, since a large amount of current flows into one point of the output terminal AOUT, there is a problem that the life of a wiring connected to the output terminal AOUT is shortened by electromigration.

An example of a method for solving the problem of the wiring life is described in Japanese Patent Application Laid-Open No. Sho 62-112420. Referring to FIG. 9, which shows a block in which measures against electromigration have been applied to this conventional functional block, a high drive buffer B includes an output-side inverter B2 which is cascaded to an input-side inverter B1 and another parallel-connected inverter B2. It comprises output-side inverters B3 to B5.

The output terminals of the inverters B2 to B5 of the respective output stages connected in parallel to enhance the driving capability are connected to output terminals BOUT1 to BOUT4, respectively. With this configuration, the output points of the signal are dispersed to the respective output terminals BOUT1 to BOUT4, and the current is prevented from being concentrated at one point.

However, in the case of this example, the number of output terminals changes according to the driving capability.
As in the method described in Japanese Patent Application Laid-Open No. 850, it is not possible to perform a process of automatically replacing only the buffer section of the output stage at the time of layout design.

Therefore, it is necessary to create a large number of libraries for each specification.

As described above, in the layout design of the conventional functional buffer, when a method of automatically replacing the buffer with an optimal buffer according to the load capacity is applied, the output current is concentrated at one point. There is a problem of electromigration, but when applying a method of dispersing current, automatic optimization of buffers cannot be performed, and the optimal function block must be manually selected from a huge library of function blocks The problem arises.

SUMMARY OF THE INVENTION An object of the present invention is to provide a functional block in which an optimum driving capability is enhanced corresponding to an output load capacitance value, and an enhancement of the driving capability. In accordance with the increased number of output terminals, other cascade-connected functional blocks are evenly allocated to these terminals, so that the current does not concentrate at one point, thereby suppressing the occurrence of electromigration. An object of the present invention is to provide a circuit layout method.

[0014]

According to the integrated circuit layout method of the present invention, a function block used for a mask pattern layout prepared in advance is stored in a block library as layout pattern information, and the function extracted from the block library is extracted. Arrange blocks
The above functions are intended for layout patterns designed with
Block drives other function blocks connected to the next stage
Drive capability connected in parallel with the functional block
Add the number of blocks for reinforcement to the wiring between the functional blocks
Includes processing to find drive capacity enhancement coefficient corresponding to capacity value
The design rule check step and the drive capacity coefficient
Therefore, the function enhancement block prepared in advance
That includes the process of adding additional layout patterns
Add the wiring step and the result of this processing step to the chip
Steps to generate the entire artwork pattern
Designed to run on a computer
The layout method of a semiconductor integrated circuit,
Out connection information, and rewrite this connection information.
The layout pattern previously arranged using the information
Function block in the
The output end of the block for function enhancement connected and connected,
Increased number of output terminals with increased drive capability
A net distribution step for equally allocating and wiring each
It is characterized by having . Further, it is possible that the driving capability enhancement block is preliminarily laid out in a layout pattern so that it can be arranged in any of the upper, lower, left and right directions of the layout pattern of the functional block, and the driving capability enhancement block is arranged and wired. I can do it. Further, the driving capability enhancement block is preliminarily laid out in a layout pattern so that it can be arranged in at least one position in the up, down, left, and right directions of the layout pattern of the functional block, and the driving capability enhancement block is arranged and wired. Can also.

The driving capacity enhancing block is preliminarily laid out in a layout pattern so that it can be arranged at any position in the vertical and horizontal directions of the layout pattern of the functional block. It is characterized by doing.

[0016] Further, the driving capability enhancing block may include:
A layout pattern is formed in advance so that the layout pattern of the functional block can be arranged in at least one position in the up, down, left, and right directions, and the driving capability enhancement block is arranged and wired.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the present invention. Referring to FIG. 1, the block library 1
Stores layout information of functional blocks to be referred to in circuit design.
One is performed.

When the circuit design ST1 is completed, a design rule check ST2 is executed with reference to the design rule file 3. At this time, the load capacities attached to the outputs of all the functional blocks are calculated. This load capacitance is the sum of the capacitances of the input terminals of other functional blocks connected to the next stage.
The capacity of each input terminal is defined in the design rule file 3.

At this time, by referring to the enhancement counting file 2, if there is a functional block whose driving capability is to be enhanced, information on which functional block should be enhanced and how much should be enhanced is written in the size file 6. Coefficient values corresponding to the output capacitance values of the respective functional blocks are written in the enhanced counting file 2. For example, the function block BUF1 is written such that the coefficient becomes 1 until the load capacitance reaches 1.0 pF, and this coefficient increases by 1 each time the load capacity increases by 1.0 pF.

When the design rule check ST2 is completed,
The processing shifts to the next delay simulation ST3. In executing the delay simulation ST3, the simulation model 4 and the delay calculation library 5 are referred to. That is, generally, the switching speed t of the block is obtained by t = (output impedance Z) × (load capacitance Cl) + (basic delay td) (1).

However, if the driving capacity enhancement coefficient is defined in the size file 6, the output impedance defined by the delay calculation library 5 often differs from the actual output impedance. After reading the size 6 data and correcting the output impedance, it is necessary to execute the delay calculation.

Specifically, increasing the driving capability means connecting the buffers at the output stage in parallel, and the driving capability enhancement coefficient indicates the number of buffers connected in parallel. . Therefore, the delay time Td of the block when the driving ability is changed can be obtained by Td = ( Z / (driving ability enhancement coefficient) ) × C1 + td (2)

Next, the processing of the placement ST4 is executed with reference to the placement and routing library 7. Here, referring to FIG. 2 showing an artwork pattern diagram of a functional buffer whose drive capability is to be enhanced, and FIG. 3 showing an equivalent circuit diagram thereof, the same reference numerals are given to the common components in both drawings. Each one is attached.

This functional block includes a PMOS transistor P1 connected in series between a power supply wiring 12 and a ground wiring 14 by a contact hole 16 having a source / drain electrode formed by a P ⁺ diffusion layer 11 and a source transistor formed by an N ⁺ diffusion layer 17. The gate electrode 10 of the NMOS transistor N1 on which the drain electrode is formed is connected to the input terminal 9 and connected to the gate electrode of the buffer composed of the PMOS transistor P2 and the NMOS transistor N2 connected to the next stage from the series connection point by aluminum wiring. Connected. This buffer has the same configuration as the buffer on the input side, and the series connection point of this buffer is connected to the output terminal 13 by aluminum wiring.

In order to increase the driving capability of the functional buffer, a buffer for enhancing the driving capability may be connected in parallel to the output-side buffer (inverter) connected to the output terminal 13. Referring to FIG. 4 showing a layout pattern diagram of the buffer for enhancing the driving capability and FIG. 5 showing an equivalent circuit diagram thereof, the buffer for enhancing the driving capability is shown in FIGS. 2 and 3. It has the same configuration as the buffer on the input side or output side of the functional block, and the input terminals 9 and 18 correspond to the output terminals 13 and 19, respectively. Other components are the same.

In the case of the buffer of the layout pattern shown in FIG. 2, when the size file specifies the driving capability enhancement coefficient as 1, this figure is placed immediately below the position where this layout pattern is arranged on the chip layout. 4 are arranged so as to be connected to the layout pattern of the driving capacity enhancement buffer. FIG. 6 shows a layout pattern resulting from the additional arrangement. FIG. 7 is a block diagram showing the equivalent circuit.

Referring to FIG. 6, the P ⁺ diffusion layer of the buffer for enhancing the driving ability and the N ⁺ diffusion layer 17 of the buffer connected to terminal 13 are connected by an aluminum wiring 21 at the shortest distance, and an aluminum wiring 22 Thus, the gate electrodes of the buffer for enhancing the driving capability and the gate electrode of the output side buffer are connected to each other via the shortest path. Since two buffers at the output stage are arranged vertically, the driving capability is increased. At this time, in addition to the output terminal 13, the output terminal of the added buffer can be used as the output terminal 19.

When the placement of the buffer for enhancing the driving capability is completed, the process of net distribution ST5 is executed. By arranging the buffer for enhancing the driving capability, signals can be supplied to a large number of function blocks. However, since these many function blocks are initially connected to the output terminal 13, In this state, it is not connected to the output terminal 19 of the buffer for enhancing the driving ability.

Therefore, in the process ST5, the connection information for layout is rewritten, the functional blocks are equally allocated to the output terminals 13 and 19, and the process proceeds to the next arrangement ST6 process.

In the placement ST6 process, the routing between the functional blocks assigned in the process ST5 is executed with reference to the placement and routing library.

When the wiring process is completed, the result of the process ST6 is added while referring to the artwork pattern library 8 to generate an artwork pattern for the entire chip.

When the layout pattern of the function enhancing buffer shown in FIG. 4 is further arranged on the lower side in the layout pattern of FIG. 6, it is apparent that the buffers are further connected in parallel. That is, the layout patterns of the function enhancement buffer may be arranged by the number of enhancement coefficients.

In the above-described embodiment, as an example, the buffer for enhancing the function is arranged one by one on the lower side. By preparing the layout pattern of the function enhancement buffer described above, it is possible to arrange the layout pattern in an arbitrary shape by observing the layout state of the entire chip, and to improve the degree of freedom in layout.

[0035]

As described above, the layout method of the semiconductor integrated circuit according to the present invention can be used to check
A desired driving capability enhancement coefficient is obtained, and the host computer arranges the layout pattern of the driving capability enhancement buffer in the buffer section where the driving capability needs to be enhanced in consideration of the layout of the entire chip in accordance with the obtained coefficient. By distributing and arranging the connection wiring (net) to the output terminal of the layout pattern of the buffer for enhancing capacity, it is possible to easily design a circuit having the optimum driving capability in the chip layout design, and to perform wiring by electromigration. A semiconductor chip with reduced degradation can be designed.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout method of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a layout pattern diagram of a buffer in a layout method of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of FIG. 2;

FIG. 4 is a diagram showing an example of a layout pattern of a driving capability enhancement buffer in a layout method of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of FIG.

FIG. 6 is a diagram illustrating a layout pattern of a buffer with enhanced driving capability in a layout method of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of FIG. 6;

FIG. 8 is a diagram showing an example of a conventional driving capability enhancement method.

FIG. 9 is a diagram showing an example of a conventional countermeasure against electromigration.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 block library 2 reinforcement coefficient file 3 design rule file 4 simulation model 5 delay calculation library 6 size file 7 placement and wiring library 8 artwork pattern library 9 input terminal 10, 20 gate 11 P ⁺ diffusion layer 12 power supply wiring 13 output terminal 14 ground Wiring 15 Aluminum wiring 16 Contact hole 17 N ⁺ diffusion layer 18 Input terminal 19 Output terminal 21, 22 Aluminum wiring P1, P2 PMOS transistor N1, N2 NMOS transistor

Claims (3)

(57) [Claims] 1. A function block used for a mask pattern layout prepared in advance is stored in a block library as layout pattern information, and the function block group extracted from the block library is arranged.
The above functions are intended for layout patterns designed with
Block drives other function blocks connected to the next stage
Drive capability connected in parallel with the functional block
Add the number of blocks for reinforcement to the wiring between the functional blocks
Includes processing to find drive capacity enhancement coefficient corresponding to capacity value
The design rule check step and the drive capacity coefficient
Therefore, the function enhancement block prepared in advance
That includes the process of adding additional layout patterns
Add the wiring step and the result of this processing step to the chip
In the layout method of a semiconductor integrated circuit which is designed by and a step of generating a whole artwork pattern on the host computer, the ray
Out connection information, and rewrite this connection information.
The layout pattern previously arranged using the information
Function block in the
Output terminals of additional and connected function-enhancing blocks
With a predetermined number of output terminals
Net distribution steps to allocate and wire the
Layout method of a semiconductor integrated circuit, characterized in that it comprises a flop. 2. The driving capability enhancement block is preliminarily laid out in a layout pattern so that it can be arranged at any position in the up, down, left, and right directions of the layout pattern of the functional block, and the driving capability enhancement block is arranged and wired. 2. The layout method for a semiconductor integrated circuit according to claim 1, wherein: 3. The driving capability enhancement block is preliminarily laid out in a layout pattern so that it can be arranged at least in one of the upper, lower, left and right directions of the layout pattern of the functional block, and the driving capability enhancement block is arranged. 2. The layout method for a semiconductor integrated circuit according to claim 1, wherein wiring is performed.