JPH07130857A - Method of laying out semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent current from concentrating at one point by generating functional blocks where an optimum drive capacity is reinforced correspondingly to the output load capacity value and uniformly assigning other functional blocks which are connected independently to these terminals corresponding to the number of output terminals which is increased along with the reinforcement of the drive capacity. CONSTITUTION:A desired drive capacity coefficient is calculated from coefficients which are stored in a reinforcement coefficient file 2 in advance and is written to a size file 6 at the time of a design rule check ST2 of chip layout, the information of the size file 6 is read and delay calculation is compensated in a delay simulation ST3, reinforcement patterns whose number is equal to the number of patterns which are written into the size file 6 are laid out around the functional block to be reinforced in a layout ST4 for reinforcing the drive capacity. A net allocation ST 5 assigns the net of the functional blocks to be connected to the output terminal which increase due to the layout of the reinforcement patterns and then wiring is made in a wiring ST6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for laying out a semiconductor integrated circuit, and more particularly to a method for laying out functional blocks in which the driving capability of functional blocks and the layout and wiring are optimized.

[0002]

2. Description of the Related Art In a gate array, the block size, the connection positions of power supply terminals, ground terminals, and signal input / output terminals are unified according to a predetermined standard, and these various functional blocks are regularly arranged in a matrix. Further, a wafer which is fixedly arranged and has undergone the substrate process is prepared. By combining these various functional blocks arranged on this wafer, only the connection wiring that connects these functional blocks is completed by using a wiring mask in order to realize a one-chip integrated circuit device having a predetermined function. I am allowed to do it.

In the design of this gate array, a desired functional block is selected from a library of functional blocks prepared in advance and selected in consideration of the load capacity of the functional block and the timing of signal change. After design, D
RC (Design Rule Check) is executed by the host computer, the load capacity limit error and the like are verified, and the timing error is verified by the logic simulation. When an error is detected here, the circuit is reviewed and the same check is repeated to complete the design of the gate array.

This gate array has recently been highly integrated,
As the scale is increased rapidly, the circuit configuration for supplying the output signal of one functional block to many functional blocks is also increasing. However, due to the reduction in transistor size that accompanies higher integration, the driving capability is decreasing, and if the load capacity increases, the switching speed will decrease.

Therefore, in order to be applicable to any circuit configuration, the number of transistors used for the same function is small and the functional block has low driving capability, or the number of transistors used is large and the driving capability is large. Like functional blocks, many blocks must be prepared as a library for each specification.

Therefore, even if the function is not so complicated, if each function is prepared for each specification, the library of function blocks becomes huge, and the circuit designer manually selects the optimum function block. It is difficult to choose.

An example of a method for facilitating these operations is described in Japanese Patent Application Laid-Open No. 61-6850. FIG. 8 showing a block for enhancing the driving capability of this conventional functional block.
Referring to, the functional block A includes a functional unit A1 and a buffer unit A2. When designing the gate array, the load capacity connected to the output terminal AOUT of this block is calculated, and the buffer section A2 is replaced with a buffer section having an optimum driving capability. In that case, the output terminal AOUT is a terminal that has already been determined irrespective of the buffer unit A2. For example, if the functional block A must supply signals to a large number of blocks, the buffer unit A2 has a high driving capability. It is replaced with a buffer section, and a signal is supplied from one terminal of the output terminal AOUT to all the functional blocks.

At this time, since a large amount of current flows into one point of the output terminal AOUT, there is a problem that the life of the wiring connected to the output terminal AOUT is shortened due to electromigration.

An example of a method for solving this wiring life problem is described in JP-A-62-112420. Referring to FIG. 9 which shows a block in which an electromigration countermeasure is applied to this conventional functional block, a high drive buffer B includes an output side inverter B2 connected in cascade with an input side inverter B1 and another output side inverter B2 connected in parallel with this inverter B2. It is composed of output side inverters B3 to B5.

The output terminals of the inverters B2 to B5 of the respective output stages connected in parallel to increase the driving capability are connected to the output terminals BOUT1 to BOUT4, respectively. With this configuration, the output points of the signals are distributed to the output terminals BOUT1 to BOUT4, and the current is prevented from being concentrated at one point.

However, in the case of this example, since the number of output terminals changes according to the driving ability, the above-mentioned Japanese Patent Laid-Open No. 61-6 is used.
Unlike the method described in Japanese Patent Publication No. 850, it is impossible to automatically replace only the buffer section at the output stage during layout design.

Therefore, it is necessary to create a large number of libraries for each specification.

As described above, in the conventional layout design of the functional buffer, if an attempt is made to automatically replace the buffer with an optimum buffer according to the load capacity, one point of the output current is concentrated. Therefore, there is a problem of electromigration. On the other hand, if the method of distributing the current is applied, the buffer cannot be automatically optimized, and the optimum functional block must be manually selected from the huge library of functional blocks. The problem arises.

An object of the present invention is to solve the above-mentioned conventional problems, and to generate a functional block having an optimal drive capacity enhanced corresponding to an output load capacitance value and to enhance the drive capacity. In accordance with the increased number of output terminals, other functional blocks connected in cascade are evenly allocated to these terminals to prevent the current from concentrating at one point, thereby suppressing the occurrence of electromigration. It is to provide a circuit layout method.

[0014]

According to an integrated circuit layout method of the present invention, functional blocks used for a mask pattern layout prepared in advance are stored in a block library as layout pattern information, and the functions extracted from the block library are stored. In a layout method of a semiconductor integrated circuit designed by executing design rule check of block group, delay simulation, placement and routing, and artwork pattern generation on a host computer, at the time of design rule check,
The driving capacity corresponding to the wiring load capacitance value between the functional blocks is defined by the number of driving capacity enhancing blocks connected in parallel to the functional block in order to drive the other functional block connected to the next stage. A function of obtaining a strengthening coefficient, a function of arranging a layout pattern prepared in advance according to the driving capacity coefficient, and a function of allocating connection information to a layout pattern of output terminals in the arranged layout pattern and performing layout wiring. And is provided.

Further, the drive capacity enhancement block is preliminarily patterned into a layout pattern so that it can be arranged at any position in the vertical and horizontal directions of the layout pattern of the functional block, and the drive capacity enhancement block is arranged and wired. It is characterized by doing.

Further, the drive capacity enhancing block comprises:
It is characterized in that a layout pattern is formed in advance so that it can be arranged at at least one position in the vertical and horizontal directions of the layout pattern of the functional block, and the drive capability enhancing block is arranged and wired.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a flow chart showing an embodiment of the present invention. Referring to FIG. 1, a block library 1
Stores the layout information of the functional blocks referred to in the circuit design, and the circuit design ST
1 is performed.

When the circuit design ST1 is completed, the design rule check ST2 is executed with reference to the design rule file 3. At this time, the load capacities attached to the outputs of all the functional blocks are calculated. This load capacity is the sum of the capacities of the input terminals of the other functional blocks connected to the next stage.
The capacity of each input terminal is defined in the design rule file 3.

At this time, by referring to the enhancement count file 2, if there is a functional block whose drive capability is desired to be enhanced, information on which functional block should be enhanced and how much should be written is written to the size file 6. Coefficient values corresponding to the output capacity values of the respective functional blocks are written in the enhanced count file 2. For example, the functional block BUF1 is written such that the coefficient becomes 1 up to the load capacitance of 1.0 pF and the coefficient also increases by 1 every time the load capacitance increases by 1.0 pF.

When the design rule check ST2 is completed,
The processing shifts to the next delay simulation ST3. In executing the delay simulation ST3, the simulation model 4 and the delay calculation library 5 are referred to. That is, generally, the switching speed t of the block is obtained by t = (output impedance Z) × (load capacitance Cl) + (basic delay td) (1).

However, here, when the driving capability enhancement coefficient is defined in the size file 6, the output impedance defined in the delay calculation library 5 and the actual output impedance often differ. It is necessary to execute the delay calculation after reading the size 6 data and correcting the output impedance.

Specifically, increasing the driving capacity means connecting the output stage buffers in parallel, and the driving capacity enhancement coefficient indicates the number of buffers connected in parallel. . Therefore, the delay time Td of the block when the driving capacity is changed can be calculated by the following formula: Td = Z / (driving capacity enhancement coefficient) × Cl + td ………………………… (2) .

Next, referring to the placement and routing library 7, the process of placement ST4 is executed. Here, referring also to FIG. 2 showing an artwork pattern diagram of the function buffer for which the driving capability is to be enhanced and FIG. 3 showing an equivalent circuit diagram thereof, the same reference numerals are given to common constituent elements in both figures. It corresponds to each.

In this functional block, a source / drain electrode is formed in the P ⁺ diffusion layer 11 and a source is formed in the N ⁺ diffusion layer 17 connected in series by a contact hole 16 between the power supply wiring 12 and the ground wiring 14. The gate electrode 10 of the NMOS transistor N1 in which the drain electrode is formed is connected to the input terminal 9 respectively, and the gate electrode of the buffer including the PMOS transistor P2 and the NMOS transistor N2 connected to the next stage from the serial connection point by the aluminum wiring. Connected. This buffer has the same structure as the buffer on the input side, and the series connection point of this buffer is connected to the output terminal 13 by aluminum wiring.

In order to increase the driving capacity of the functional buffer, a buffer for driving capacity enhancement may be connected in parallel to the output side buffer (inverter) connected to the output terminal 13. Referring to FIG. 4 showing the layout pattern diagram of the buffer for enhancing the driving ability and FIG. 5 showing the equivalent circuit diagram thereof, the buffer for enhancing the driving ability is shown in FIGS. 2 and 3. It has the same configuration as the buffer on the input side or the output side of the functional block, and corresponds to the input terminals 9 and 18 and the output terminals 13 and 19, respectively. The other components are the same.

For the buffer of the layout pattern shown in FIG. 2, when the size file specifies the driving capacity enhancement coefficient as 1, this figure is located immediately below the position where this layout pattern is arranged on the chip layout. The layout of the buffer for driving capacity enhancement shown in FIG. 4 is arranged so as to be connected. The layout pattern resulting from the additional placement is shown in FIG. FIG. 7 is a block diagram showing the equivalent circuit.

Referring to FIG. 6, the P ⁺ diffusion layer of the buffer for enhancing the driving capability and the N ⁺ diffusion layer 17 of the buffer connected to the terminal 13 are connected by the aluminum wiring 21 at the shortest distance, and the aluminum wiring 22 is connected. Thus, the gate electrodes of the drive capacity enhancing buffer and the output side buffer are shortest connected to each other. Since two buffers at the output stage are arranged in the upper and lower parts, the driving capability is large. At this time, in addition to the output terminal 13, the output terminal of the added buffer can be used as the output terminal 19.

When the arrangement of the buffer for enhancing the driving ability is completed, the processing of net distribution ST5 is executed. By arranging the buffer for enhancing the driving capability, it becomes possible to supply signals to a large number of functional blocks, but since these large number of functional blocks are initially connected to the output terminal 13. As it is, it is not connected to the output terminal 19 of the buffer for driving capacity enhancement.

Therefore, in this process ST5, the connection information for layout is rewritten, the functional blocks are evenly allocated to the output terminals 13 and 19, and the process proceeds to the next layout ST6 process.

In the placement ST6 processing, the wiring between the functional blocks obtained as a result of the processing ST5 is executed with reference to the placement / wiring library.

When the wiring process is completed, the result of the process ST6 is added while referring to the artwork pattern library 8 to generate the artwork pattern of the entire chip.

In the layout pattern of FIG. 6 described above, if the layout pattern of the buffer for function enhancement shown in FIG. 4 is arranged on the lower side, it is apparent that the buffers are further connected in parallel. That is, the layout patterns of the function enhancement buffers may be arranged by the number of enhancement coefficients.

In the above-described embodiment, as an example, the function-enhancing buffers are arranged downward one after another. However, a layout pattern dedicated to the upper, lower, left, and right directions, or a layout so that they can be arranged in either the upper, lower, left, or right directions. By preparing the layout pattern of the function-enhancing buffer described above, it is possible to arrange the layout pattern in an arbitrary shape in view of the layout arrangement state of the entire chip, and it is possible to improve the degree of freedom of layout.

[0035]

As described above, according to the layout method of the semiconductor integrated circuit of the present invention, when the design rule is checked,
The desired drive capacity enhancement coefficient is calculated, and the host computer places the layout pattern of the drive capacity enhancement buffer in the buffer section where the drive capacity needs to be enhanced while considering the layout of the entire chip according to the coefficient. By allocating and laying out the connection wiring (net) to the output terminals of the layout pattern of the capacity enhancement buffer, it is possible to easily design a circuit with the optimum drive capacity for the chip layout design, and wiring by electromigration. A semiconductor chip with reduced deterioration can be designed.

[Brief description of drawings]

FIG. 1 is a flowchart of a semiconductor integrated circuit layout method according to an embodiment of the present invention.

FIG. 2 is a layout pattern diagram of a buffer in a semiconductor integrated circuit layout method according to an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of FIG.

FIG. 4 is a diagram showing an example of a layout pattern of a drive capability enhancement buffer in a semiconductor integrated circuit layout method according to an embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of FIG.

FIG. 6 is a diagram showing a layout pattern of a buffer with enhanced drive capability in a semiconductor integrated circuit layout method according to an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of FIG.

FIG. 8 is a diagram showing an example of a conventional drive capacity enhancement method.

FIG. 9 is a diagram showing an example of a conventional electromigration countermeasure.

[Explanation of symbols]

1 Block Library 2 Strengthening Coefficient File 3 Design Rule File 4 Simulation Model 5 Delay Calculation Library 6 Size File 7 Placement / Wiring Library 8 Artwork Pattern Library 9 Input Terminals 10, 20 Gate 11 P ⁺ Diffusion Layer 12 Power Supply Wiring 13 Output Terminal 14 Grounding Wiring 15 Aluminum wiring 16 Contact hole 17 N ⁺ Diffusion layer 18 Input terminal 19 Output terminal 21,22 Aluminum wiring P1, P2 PMOS transistor N1, N2 NMOS transistor

Claims (3)

[Claims] 1. A functional block used for a mask pattern layout prepared in advance is stored in a block library as layout pattern information, and a design rule check of the functional block group extracted from this block library, delay simulation, placement and routing, and In a layout method of a semiconductor integrated circuit designed by executing artwork pattern generation on a host computer, at the time of checking the design rule,
The driving capacity corresponding to the wiring load capacitance value between the functional blocks is defined by the number of driving capacity enhancing blocks connected in parallel to the functional block in order to drive the other functional block connected to the next stage. A function of obtaining a strengthening coefficient, a function of arranging a layout pattern prepared in advance according to the driving capacity coefficient, and a function of allocating connection information to a layout pattern of output terminals in the arranged layout pattern and performing layout wiring. A layout method of a semiconductor integrated circuit, comprising: 2. The drive capacity enhancement block is preliminarily layout-patterned so that it can be arranged at any position in the vertical and horizontal directions of the layout pattern of the functional block, and the drive capacity enhancement block is arranged and wired. The method for laying out a semiconductor integrated circuit according to claim 1, wherein: 3. The drive capability enhancing block is preliminarily layout-patterned so that it can be disposed at at least one position in the vertical and horizontal directions of the layout pattern of the functional block, and the drive capability enhancing block is disposed. The method for laying out a semiconductor integrated circuit according to claim 1, wherein wiring is performed.