JP2013097705A - Layout device and layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve both securing precision and holding a duty, in adjustment of clock skew in a clock tree.SOLUTION: A layout device (10) is provided with a table where first cells each of which is formed of one stage of MOS transistors and second cell each of which is formed of a plurality of stages of MOS transistors are stored as libraries. The layout device includes an arithmetic unit (12) which can adjust clock skew between different clock systems in a clock tree by inserting combination chains comprising first cells and second cells, to the clock tree. By inserting the combination chains to adjust the clock skew, propagation of delay errors in individual first cells is suppressed to reduce delay errors in delay calculation. Further, since each first cell is formed of one stage of MOS transistors and the logic is inverted in the first cell, the layout device is advantageous with respect to holding a duty.

Description

  The present invention relates to a standard cell layout technique, and further to a technique for adjusting clock skew in a clock tree.

  In order to efficiently design a logic scale integration (Large Scale Integration), a standard cell (simply referred to as a “cell”) showing a pattern for realizing a predetermined function is designed for each function in advance, and the circuit to be designed A plurality of standard cells are laid out on the chip according to the functions included in. In addition, a clock tree for distributing clock signals is constructed in the logic LSI. The clock tree is one of logical structures for clock distribution.

  Patent Document 1 describes a technique of repeatedly dividing a region where flip-flops are arranged on a semiconductor integrated circuit based on the number of data connection paths, and connecting the flip-flops of the divided regions in a tree shape. Yes.

  Patent Document 2 describes a technique in which a flip-flop included in a clock tree is divided into a plurality of groups and a delay buffer is inserted at the front stage of the group so that the circuit scale converges below a threshold value. .

JP 2007-123336 A JP 2006-107206 A

  In a semiconductor device such as a logic LSI, a clock tree for distributing clock signals is constructed. The clock tree is one of the logical structures for clock distribution, and multiple delay elements are used to minimize the variation in clock arrival time (clock skew) from the clock logic start point to the flip-flop circuit in the semiconductor device. Is built in a tree shape. In the clock tree, it may be necessary to adjust the clock skew (latency adjustment) between different clock systems. In this clock skew adjustment, a delay calculation of a circuit designed at the component level is performed.

  In the delay calculation of the circuit designed at the component level, the delay characteristics (libraries) that have been measured in advance for each component are used, and the delay variation factors (slew rate, load capacity, etc.) for each cell. After delay calculation for each cell, it is added according to the net list. The inventors of the present application examined such delay calculation, and found the following problems.

  In the method of extracting the component characteristics in cell units, the nonlinear delay variation characteristics by circuit simulation are expressed in a library in a linear or piecewise linear (table) form, so that a certain accuracy error occurs. This error varies depending on each cell type and the degree of variation, but in most cases it does not become a large error. However, in a one-stage cell of a MOS transistor such as an inverter or a two-input NAND gate, the delay error in the delay calculation tends to increase because the delay error on the input side directly affects the output side. In particular, in an inverter chain in which a plurality of inverters are connected in series with each other, the error increases due to propagation of delay errors in the individual inverters.

  In contrast, a two-stage MOS transistor cell such as a buffer has less delay error than a one-stage MOS transistor cell such as an inverter or a two-input NAND gate. However, a two-stage cell of a MOS transistor such as a buffer is inferior to a one-stage MOS transistor cell in terms of maintaining the ratio (duty) between the high level period and the low level period of the clock signal. That is, in a cell having one stage of a MOS transistor such as an inverter, the output logic is inverted with respect to the input logic. Therefore, in the inverter chain in which a plurality of inverters are connected in series, the duty of the clock signal is difficult to change. On the other hand, since the output logic of the two-stage MOS transistor cell such as a buffer is not inverted with respect to the input logic, in the buffer chain in which a plurality of buffers are connected in series with each other, the waveform rise and fall delays The clock signal duty is likely to change due to the time difference.

  An object of the present invention is to provide a technique for achieving both ensuring of accuracy and maintaining a duty in adjusting a clock skew in a clock tree.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, the layout device can construct a clock tree for distributing the clock signal to each part in the semiconductor device, and can adjust the clock skew between different clock systems in the clock tree. In such a layout apparatus, a table is provided in which a first cell formed by one stage of a MOS transistor and a second cell formed by a plurality of stages of MOS transistors are formed into a library. In the layout apparatus, an arithmetic processing capable of adjusting a clock skew between different clock systems in the clock tree by inserting a combination chain of a combination of the first cell and the second cell into the clock tree. Parts are provided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the adjustment of the clock skew in the clock tree, it is possible to ensure both accuracy and duty retention.

1 is a block diagram illustrating a configuration example of a layout device according to the present invention. It is explanatory drawing of clock tree generation. It is explanatory drawing of the principal part in a clock tree. It is explanatory drawing of the clock skew adjustment in a clock tree. It is explanatory drawing of the clock skew adjustment by an inverter chain. It is explanatory drawing of the clock skew adjustment by the combination chain of a buffer and an inverter. It is explanatory drawing of the clock skew adjustment by the combination chain of an inverter and wiring delay. It is explanatory drawing of the clock skew adjustment by the combination chain of a buffer, an inverter, and wiring delay. It is explanatory drawing of the general layout process of the some inverter for delay adjustment between clocks. It is explanatory drawing of arrangement | positioning space | interval determination of the inverter cell for delay adjustment between clocks. It is a structural example explanatory drawing of a delay table. It is a flowchart of a clock tree construction process. It is another flowchart of a clock tree construction process. It is a flowchart of the latency adjustment process between start points in clock tree construction. It is another flowchart of the latency adjustment processing between start points in clock tree construction. It is another flowchart of the latency adjustment processing between start points in clock tree construction. It is explanatory drawing of the circuit structure and input / output waveform of an inverter. It is explanatory drawing of the circuit structure and input / output waveform of a buffer.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A layout device (10) according to a typical embodiment of the present invention constructs a clock tree for distributing a clock signal to each part in a semiconductor device, and clock skew between different clock systems in the clock tree. Can be adjusted. In such a layout device, there is provided a table (111) in which a first cell formed of one stage of a MOS transistor and a second cell formed of a plurality of stages of MOS transistors are formed into a library. The layout device includes an arithmetic processing unit capable of adjusting a clock skew between different clock systems in the clock tree by inserting a combination chain formed by a combination of the first cell and the second cell into the clock tree. (12) is provided.

  According to the above configuration, since the clock skew is adjusted by the combination chain formed by the combination of the first cell and the second cell, the delay error in each first cell is propagated. It is possible to suppress the delay error in the delay calculation. Thereby, the accuracy in adjusting the clock skew in the clock tree can be improved.

  Further, by using a combination chain that is a combination of the first cell and the second cell, the first cell is interposed in the combination chain, and the logic is inverted there, which is advantageous from the viewpoint of maintaining the duty. The

  [2] In the above [1], the arithmetic processing unit sets the number of stages of the first cell to “1”, sets the number of stages of the second cell to “n”, and calculates a delay error of one stage of the first cell. When “X” is set, the delay error of the second stage of the second cell is “Yn”, and the delay error per combination chain is “Z”, (X + Yn) / (n + 1) ≦ Z is satisfied. It is possible to configure so as to determine the configuration per one combination chain. And, it is possible to adjust the clock skew between different clock systems in the clock tree by connecting the combination chains in series as many as necessary for adjusting the clock skew between the clock trees. . From the standpoint of accuracy, it is better that the number of stages of the second cell is larger, but considering the latency and ease of use, it is better that the number of stages of the second cell is smaller. Considering the trade-off, it is desirable to determine the configuration per one combination chain so that the above formula is satisfied.

  [3] In the above [2], the arithmetic processing unit determines the wiring length of the input side net of the first cell to be laid out based on the lower limit value of the wiring capacity of the first cell in the library. Can be configured to determine.

  [4] In the above [3], the arithmetic processing unit determines that the capacity calculated from the shortest distance wiring length of the first cell to be laid out is a lower limit of the wiring capacity of the first cell in the library. The layout position of the first cell can be determined so as to be larger than the value. By specifying the wiring capacity for the input-side net of the first cell in the combination chain, the corresponding wiring capacity is formed, so that it is possible to reduce the delay error in the delay calculation. At this time, since all the cells forming the chain do not add wiring delay, the risk of using a large amount of wiring resources can be avoided.

  [5] In the above [4], the first cell can be an inverter and the second cell can be a buffer.

  [6] Another layout apparatus (10) according to a typical embodiment of the present invention is a layout target with a table (111) in which adjustment cells formed by one stage of a MOS transistor are made into a library, and the layout target. Arithmetic processing for determining the layout position of the adjustment cell so that the capacity calculated from the shortest distance wiring length of the adjustment cell is larger than the lower limit value of the wiring capacity of the adjustment cell in the library Part (12).

  According to the above configuration, the capacity calculated from the shortest distance wiring length of the adjustment cell to be laid out is larger than the lower limit value of the wiring capacity of the adjustment cell in the library. By determining the layout position of the adjustment cell, a wiring capacity corresponding to the wiring capacity of the adjustment cell in the library is formed, so that a delay error in delay calculation can be reduced.

  [7] In the above [6], the adjustment cell may be an inverter.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 shows a configuration example of a layout apparatus according to the present invention.

  The layout device 10 shown in FIG. 1 is configured using a computer system including a display device 11, an arithmetic processing device 12, a storage device 13, and an input device 14. The storage device 13 is a hard disk device using, for example, a magnetic disk as a recording medium. The storage device 13 stores various programs and various information used for the layout of the semiconductor device. Various information used for the layout of the semiconductor device includes a net list and a library. This library includes delay tables of various cells such as inverters and buffers. The arithmetic processing unit 12 includes a microcomputer that can execute various arithmetic processes according to a program and its peripheral circuits, and performs layout processing of the semiconductor device. This layout processing includes construction of a clock tree for distributing a clock signal to each part in the semiconductor device and adjustment of clock skew between the clock trees. In the layout device 12, a netlist or library in the storage device 13 is referred to as necessary. The input device 14 includes a keyboard and a mouse, and is used for inputting various information related to the layout processing of the semiconductor device. The display device 11 is a liquid crystal display or the like, and can display various information related to the layout processing of the semiconductor device.

  In a semiconductor device such as a logic LSI, a clock tree for distributing clock signals is constructed. The clock tree is one of logic structures for clock distribution. For example, as shown in FIG. 2A, the clock arrival time variation from the clock logic start point 203 to the flip-flop circuit 201 in the semiconductor device 200 (clock skew). ) Is made as small as possible, and a plurality of delay elements 202 are interposed as shown in FIG.

  FIG. 12 shows the flow of the clock tree construction process.

  The clock tree construction process shown in FIG. 12 is realized by executing a predetermined program for the clock tree construction process in the arithmetic processing unit 12.

  In order to efficiently form a large-scale circuit, in the cell placement process in step 1201 described above, cell placement processing of a semiconductor device to be laid out is performed using cells such as an inverter, a NAND gate, a NOR gate, and a flip-flop circuit ( 1201). A timing optimization process is performed (1202), and then a clock tree synthesis process (CTS) is performed (1203). When this clock tree synthesis processing is completed, timing optimization processing is performed again (1208), and then wiring processing is performed (1209).

  In the clock configuration process of step 1203, when the start point and end point of the clock tree are instructed via the input device 14 (1204), a clock tree is constructed for each start point (1205). Then, a latency matching process is performed for each constructed clock tree (1206), and when this is completed, a latency matching process between the start points is performed (1207).

  As shown in FIG. 13, it is determined whether or not the latency matching process is necessary between the latency matching process for each clock tree in step 1206 and the latency matching process between start points in step 1207 (1301). ) May be performed. Only when it is determined in this determination process that the latency matching process is necessary, the latency matching process between the start points in step 1207 is performed. In this way, when the latency matching process is actually unnecessary, the latency matching process can be omitted, so that the processing efficiency can be improved.

  Next, the start point latency matching processing in step 1207 will be described in detail.

  In the clock tree, it may be necessary to adjust the clock skew (latency adjustment) between different clock systems. For example, as shown in FIG. 3, different clock systems 302 and 304 are provided in the clock tree, the clock system 302 is supplied with the clock signal divided by the frequency dividing circuit 301, and the clock system 304 is supplied to the clock system 304. Consider a case where a clock signal is supplied via the buffer 303. When the number of flip-flop circuits in the clock system 302 is smaller than the number of flip-flop circuits in the clock system 304, the difference in clock latency between the clock system 302 and the clock system 304 becomes large. For this reason, when data transfer is performed between the flip-flop circuit belonging to the clock system 302 and the flip-flop circuit belonging to the clock system 304, it is necessary to adjust the clock skew. To adjust the clock skew, a buffer chain 401 is provided between the frequency divider 301 and the clock system 302 as shown in FIG. 4, or the frequency divider 301 and the clock system are shown in FIG. It is conceivable to provide an inverter chain 501 with the terminal 302. The buffer chain 401 includes a plurality of buffers connected in series. The inverter chain is formed by connecting a plurality of inverters in series with each other.

  For example, as shown in FIG. 17A, the inverter includes a p-channel MOS transistor 1701 and an n-channel MOS transistor 1702 connected in series. The gate electrode of the p-channel MOS transistor 1701 and the gate electrode of the n-channel MOS transistor 1702 are commonly connected to the input terminal (IN). An output terminal (OUT) is drawn from a series connection node of the p-channel MOS transistor 1701 and the n-channel MOS transistor 1702. A wiring capacitor 1703 exists on the output side of the inverter.

  For example, as shown in FIG. 18A, the buffer includes a first inverter in which a p-channel MOS transistor 1801 and an n-channel MOS transistor 1802 are connected in series, a p-channel MOS transistor 1803 and an n-channel. A second inverter formed by connecting a type MOS transistor 1804 in series is connected in series. A wiring capacitor 1805 exists on the output side of the second inverter (1803, 1804). Although there is a wiring capacity on the output side of the first inverter (1801, 1802), the value is extremely smaller than the wiring capacity 1805. This is because in the buffer as a cell, the wiring between the first inverter (1801, 1802) and the second inverter (1803, 1804) is extremely short.

  Since a wiring capacitor 1703 is formed on the output side of the inverter, the clock signal input through the input terminal is delayed and output as shown in FIG. That is, the output waveform becomes dull due to the presence of the wiring capacitance 170. On the other hand, in the case of the buffer, since the wiring capacity on the output side of the first inverter (1801, 1802) is minimal, the second inverter (1803, 1803) after the input waveform of the first inverter (1801, 1802) is shaped. 1804), the output waveform of the second inverter (1803, 1804) is less dull than the output waveform of the inverters (1701, 1702) shown in FIG.

  As described above, the delay calculation of the circuit designed at the component level uses the delay characteristics measured for each component in advance (the library in the storage device 13), and the delay variation for each cell. The delay is calculated for each cell stage according to factors (slew rate, load capacity, etc.), and then added according to the net list. The method of extracting component characteristics in cell units is to calculate delays for large-scale LSIs at high speed for nonlinear delay variation characteristics, and is expressed in a library in linear or piecewise linear (table) form. An error is generated. Compared to a two-stage MOS transistor cell such as a buffer, a one-stage MOS transistor cell such as an inverter tends to have a larger error because a delay error affects the next stage. In particular, in an inverter chain 701 in which a plurality of inverters are connected in series, delay errors in individual inverters are sequentially propagated, so that the error becomes large.

  Therefore, in the latency adjustment processing between the start points in step 1207, the clock skew is adjusted by the combination chain 601 of the buffer and the inverter as shown in FIG. In this combination chain 601, buffers are provided before and after the inverter.

  FIG. 14 shows a flow of latency matching processing between start points using a combination chain 601 of a buffer and an inverter.

  In the start point latency matching processing 1207 shown in FIG. 14, when a target delay value and skew are set via the input device 14 (1401), a buffer and an inverter are added according to a predetermined combination rule. (1402). Then, the buffer and inverter added in the process of step 1402 are arranged on the actual layout pattern (1403), and the delay value of the added buffer and inverter is calculated (1404). Then, it is determined whether or not the delay value calculated in step 1404 is equal to the target delay value set in step 1401 (1405). If it is determined in this determination that the delay value calculated in step 1404 is not equal to the target delay value set in step 1401 (NO), the process returns to step 1402 again. After the addition of the buffer and the inverter, the determination processing in step 1405 is performed again through the processing in steps 1403 and 1404. When it is determined that the delay value calculated in step 1404 is equal to the target delay value set in step 1401 (YES) in the determination process in step 1405, the start point latency matching process 1207 is performed. Is terminated.

  Here, the addition of the buffer and the inverter in step 1402 will be described in detail.

  Depending on the process, for example, in the case of a process of 65 nm or more, if the error of one stage of the inverter is about 8%, the error of one stage of the buffer is about 2%, and the delay value of the buffer is about twice that of the inverter In order to keep the accuracy within 3% required by the tree, a serial connection configuration of three buffers and one inverter is employed. From the standpoint of accuracy, it is better to have a larger number of buffer stages. However, considering the trade-off between latency and ease of use (the smaller number of stages is easier to use), the buffer has three stages and the inverter has one stage. The combination of the buffer and the inverter is input to the arithmetic processing unit 12 as a parameter for latency matching between start points. This parameter may be set in advance or may be input via the input device 14.

  In general, it is assumed that the inverter stage number is “1”, the buffer stage number is “n”, the inverter one stage error is “X”, and the buffer n stage error is “Yn” (where X> Y). If the target error (one stage) is “Z”, the configuration per combination chain is determined so that the relationship of the following equation is established.

  In this manner, the buffer and the inverter are added in step 1402. The combination chain is added until it is determined that the target delay value set in step 1401 is equal (YES). In other words, when the target delay is Sns, when the delay obtained by the above combination (1 inverter stage, n buffer stage) is Pns, the value of “m” when the relationship of Pns · m = Sns is established. The above combination chains are additionally formed by an equal number.

  If the combination chain is further added when the delay is slightly insufficient, the delay amount may be too large. In that case, it is preferable to add a buffer or an inverter alone.

  In addition, since the drive capacities of the buffers and the inverters are generally different, actually, the drive capacities of the buffers and the inverters are different. Since the errors by drive capacity are X1, X2..., Xn, Y1, Y2..., Yn for the buffers and inverters, respectively (the relationship between error and drive capacity is 1 <2,. The number of stages is determined as follows. In this case, the selection of the driving capability may be determined based on the following ideas (1) to (3).

  (1) In order to achieve a combination that minimizes the delay error, a buffer having the maximum driving capability is used.

  (2) In order to achieve a combination that minimizes power, a buffer having the minimum driving capability is used.

  (3) Combine (1) and (2) above. That is, the combination of the minimum power within a certain error or the combination of the minimum error within a certain power value is used.

  Thus, according to this example, as shown in FIG. 6, the clock skew is adjusted by the combination chain 601 of the buffer and the inverter, and the buffer is interposed so as to sandwich the inverter. Propagation of delay errors in individual inverters can be suppressed, and delay errors in delay calculation can be reduced as compared with the case of using an inverter chain. Thereby, the accuracy in adjusting the clock skew in the clock tree can be improved.

  Further, in a buffer chain in which a plurality of buffers are connected in series with each other, the duty of the clock signal is likely to change due to the difference between the rising and falling delay times. However, in this example, a combination chain 601 of a buffer and an inverter is used. As a result, an inverter is interposed in the chain, and the logic is inverted there, which is superior in terms of duty retention compared to the case of using a buffer chain that does not cause logic inversion.

<< Embodiment 2 >>
In the processing for adjusting the latency between the start points in step 1207, the clock skew can be adjusted by the combination chain 701 of the inverter and the wiring delay as shown in FIG. When the clock skew is adjusted by the combination chain 701 of the inverter and the wiring delay, the minimum capacity value (the lower limit value of the capacity) is input as a parameter to the arithmetic processing unit 12. This parameter may be set in advance or may be input via the input device 14.

  FIG. 15 shows a flow of latency matching processing between start points using the combination chain 701 of the inverter and the wiring delay.

  In the start point latency matching processing 1207 shown in FIG. 15, when the target delay value and skew are set via the input device 14 (1501), an inverter is added (1502). Then, the inverter added in the process of step 1502 is placed on the actual layout pattern (1503), and the placement position of the inverter is determined so that the added inverter becomes equal to or greater than the designated wiring capacitance value ( 1504). Then, it is determined whether or not the delay value of the combination chain 701 after the arrangement position is determined in step 1504 is equal to the target delay value set in step 1501 (1505). In this determination, if it is determined that the delay value of the combination chain 701 after the arrangement position is determined in step 1504 and the target delay value set in step 1501 are not equal (NO), the above is performed again. After returning to the process of step 1502 and adding the inverter, the determination process of step 1505 is performed again through the processes of steps 1503 and 1504. In the determination processing in step 1505, if it is determined that the delay value of the combination chain 701 after the arrangement position determination in step 1504 is equal to the target delay value set in step 1501 (YES), The inter-start point latency matching process 1207 is terminated.

  Here, the arrangement position determination in step 1504 will be described in detail.

  FIG. 11 shows a configuration example of a delay table of cells in the library in the storage device 13. In the delay table 111 shown in FIG. 11, variable_1 and index_1 are associated with each other, and variable_2 and index_2 are associated with each other. The table size is 6 for both index_1 and index_2. The more the number of actual definitions of index_2 is, the larger the table size will be, and it will take time to refer to the table. In the delay table 111 of FIG. 11, the actual value of index_2 is a capacity value and is defined as “0.001, 0.00123399, 0.00189322, 0.003755043, 0.00898268, 0.0137473”. .

  For example, an inverter chain as shown in FIG. 9A is formed by connecting a plurality of inter-clock delay adjusting inverters in series with each other after the buffer 901. In a general layout process of a plurality of inter-clock delay adjustment inverters, for example, as shown in FIG. 9B, a plurality of inter-clock delay adjustment inverters are arranged in the immediate vicinity of the output side of the buffer 901. For this reason, the wiring between the clock delay adjusting inverters is also shortened, and the wiring capacitance value on the output side of each clock delay adjusting inverter is reduced. With this layout, if the wiring capacitance value on the output side of each inverter for adjusting delay between clocks is outside the range of the capacitance value (actual value of index_2) defined in the delay table 111 of FIG. Will become bigger.

  Therefore, in the determination of the arrangement position in step 1504, the arrangement interval between the inverter cells for delay adjustment between clocks is set using the lower limit value of the capacitance value (actual value of index_2) defined in the delay table 111 of FIG. 11 as a parameter. It is determined. For example, since the lower limit value of the capacity value (the actual value of index_2) defined in the delay table 111 of FIG. 11 is “0.001”, the arithmetic processing unit 12 uses this capacity value (the actual value of index_2). ) Is used as a parameter to determine the arrangement interval between cells. That is, as shown in FIG. 10A, the value of the capacitance (wiring capacitance) calculated from the length of the shortest wiring (shortest distance wiring) 902 among the wirings in the inter-clock delay adjusting inverter cell row. However, the arrangement interval of the inter-clock delay adjusting inverter cells is determined so as to be equal to or greater than the lower limit “0.001” of the capacitance value (actual value of index_2) as the parameter.

  When the lower limit value of the capacitance value (actual value of index_2) as the above parameter is “0.002,” as shown in FIG. 10B, an inverter cell row for delay adjustment between clocks. Among the wirings in FIG. 5B so that the capacitance value calculated from the length of the shortest wiring 903 is not less than the lower limit “0.002” of the capacitance value (actual value of index_2) as the above parameter. The arrangement interval of the delay adjustment inverter cells is determined. For this reason, when the lower limit value of the capacity value (actual value of index_2) used as the parameter is “0.002,” the arrangement interval of the clock delay adjusting inverter cells is the capacity value (index_2) used as the parameter. The lower limit value of (actual value of) is larger than the arrangement interval of the inter-clock delay adjusting inverter cells when the lower limit value is “0.001”.

  As described above, the capacitance value calculated from the length of the shortest wiring 902 among the wirings in the inverter cell row for adjusting the delay between clocks is not less than the lower limit value of the capacitance value (actual value of index_2) as the above parameter. By determining the arrangement interval of the inter-clock delay adjustment inverter cells, the input side and output side of each inter-clock delay adjustment inverter correspond to the definition information in the delay table 111 of FIG. Therefore, the delay error can be reduced.

<< Embodiment 3 >>
In the case of the combination chain of the inverter and the wiring delay or the combination chain of the buffer and the wiring delay as in the second embodiment, it is necessary to add the wiring delay to all the inverters or buffers forming the chain. There is a risk of using a lot of wiring resources. Therefore, as shown in FIG. 8, the combination chain 801 of the buffer and the inverter as in the first embodiment is constructed, and the input side net 802 of the inverter in this combination chain is connected to the wiring capacity as in the second embodiment. It is good to specify.

  FIG. 16 shows a flow of latency adjustment processing between start points using a combination chain 701 of a buffer, an inverter, and a wiring delay. In this case, the combination of the buffer and inverter to be inserted and the minimum capacity value are input to the arithmetic processing unit 12 as parameters.

  In the inter-start point latency matching processing 1207 shown in FIG. 16, when the target delay value and skew are set via the input device 14 (1601), a buffer and an inverter are added according to a predetermined combination rule. (1602). Then, the buffer and inverter added in the process of step 1602 are arranged on the actual layout pattern (1603), and the wiring capacity of the input side net of the added inverter exceeds the specified wiring capacity value. Thus, the arrangement position of the cell is determined (1604). This arrangement position can be determined in the same manner as in the second embodiment. That is, the cell arrangement interval is determined so that the wiring capacity of the input inverter net of the added inverter is equal to or greater than the lower limit value of the capacitance value (actual value of index_2) as a parameter. Then, the delay values of the buffer and the inverter added in step 1603 are calculated (1605), and it is determined whether or not the calculated delay value is equal to the target delay value set in step 1401. (1606). If it is determined in this determination that the delay value calculated in step 1605 is not equal to the target delay value set in step 1601 (NO), the process returns to step 1602 again. After the addition of the buffer and the inverter, the determination processing in step 1606 is performed again through the processing in steps 1603, 1604, and 1605. If it is determined that the delay value calculated in step 1605 is equal to the target delay value set in step 1601 (YES) in the determination process in step 1606, the latency matching process between start points 1207 is performed. Is terminated.

  Thus, according to this example, since the combination chain of the buffer and the inverter is constructed as in the first embodiment, it is possible to suppress the propagation of delay error in each inverter, and the inverter chain The delay error in the delay calculation can be reduced as compared with the case of using. In addition, by specifying the wiring capacity for the input side net 802 of the inverter in the combination chain as in the second embodiment, the wiring capacity corresponding to the definition information is formed in the delay table 111 of FIG. The delay error can be reduced. Further, for the input side net 802 of the inverter in the combination chain, the wiring capacity is designated as in the second embodiment, and wiring delay is not added to all the inverters or buffers forming the chain. The risk of using a lot of wiring resources can be avoided.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, an inverter is an example of a cell formed of one stage of a MOS transistor, and a buffer is an example of a cell formed of a plurality of stages of MOS transistors. As a cell formed of one MOS transistor, a two-input NAND gate can be cited in addition to the inverter. As a cell formed of a plurality of stages of MOS transistors, a multiplexer can be used in addition to the buffer.

DESCRIPTION OF SYMBOLS 10 Layout apparatus 11 Display apparatus 12 Arithmetic processing apparatus 13 Storage apparatus 14 Input apparatus 111 Delay table 601,701,801 Combination chain

Claims (11)

A layout device capable of constructing a clock tree for distributing a clock signal to each part in a semiconductor device and adjusting a clock skew between different clock systems in the clock tree,
A table in which a first cell formed by one stage of a MOS transistor and a second cell formed by a plurality of stages of MOS transistors are formed into a library;
An arithmetic processing unit capable of adjusting a clock skew between different clock systems in the clock tree by inserting a combination chain formed by a combination of the first cell and the second cell into the clock tree. A layout device.   The arithmetic processing unit sets the number of stages of the first cell to “1”, the number of stages of the second cell to “n”, the delay error of one stage of the first cell to “X”, and the second cell When the delay error of n stages is “Yn” and the delay error per combination chain is “Z”, the configuration per combination chain so that (X + Yn) / (n + 1) ≦ Z is satisfied. 2. The clock skew between different clock systems in the clock tree is adjusted by connecting the combination chains in series to each other as many times as necessary for adjusting the clock skew between the clock trees. Layout device.   The layout according to claim 2, wherein the arithmetic processing unit determines the wiring length of the input side net of the first cell to be laid out based on the lower limit value of the wiring capacity of the first cell in the library. apparatus.   The arithmetic processing unit is configured so that the capacity calculated from the shortest distance wiring length of the first cell to be laid out is larger than the lower limit value of the wiring capacity of the first cell in the library. The layout apparatus according to claim 3, wherein the layout position of the first cell is determined.   The layout apparatus according to claim 4, wherein the first cell is an inverter and the second cell is a buffer. A layout device capable of constructing a clock tree for distributing a clock signal to each part in a semiconductor device and adjusting a clock skew between different clock systems in the clock tree,
A table in which adjustment cells formed by one stage of MOS transistors are made into a library;
The layout position of the adjustment cell so that the capacity calculated from the shortest distance wiring length of the adjustment cell to be laid out is larger than the lower limit value of the wiring capacity of the adjustment cell in the library. And a calculation processing unit for determining the layout.   The layout apparatus according to claim 6, wherein the adjustment cell is an inverter. A table in which a first cell formed by one stage of a MOS transistor and a second cell formed by a plurality of stages of MOS transistors are made into a library and an arithmetic processing unit that performs arithmetic processing are used for each part in the semiconductor device. A layout method capable of adjusting a clock skew between different clock systems in the clock tree while constructing a clock tree for distributing clock signals,
Inserting a combination chain formed by a combination of the first cell and the second cell into the clock tree to cause the arithmetic processing unit to execute processing for adjusting clock skew between different clock systems in the clock tree. Characteristic layout method.   The arithmetic processing unit sets the number of stages of the first cell to “1”, the number of stages of the second cell to “n”, the delay error of one stage of the first cell to “X”, and the second cell When the delay error of n stages is “Yn” and the delay error per combination chain is “Z”, the configuration per combination chain so that (X + Yn) / (n + 1) ≦ Z is satisfied. 9. The clock skew between different clock systems in the clock tree is adjusted by connecting the combination chains in series to each other as many times as necessary for adjusting the clock skew between the clock trees. Layout method.   The arithmetic processing unit is configured so that the capacity calculated from the shortest distance wiring length of the first cell to be laid out is larger than the lower limit value of the wiring capacity of the first cell in the library. The layout method according to claim 9, wherein the layout position of the first cell is determined. Using a table in which adjustment cells formed by one stage of MOS transistors are made into a library and an arithmetic processing unit that performs arithmetic processing, a clock tree for distributing a clock signal to each unit in the semiconductor device is constructed, A layout method capable of adjusting a clock skew between different clock systems in the clock tree,
The layout position of the adjustment cell so that the capacity calculated from the shortest distance wiring length of the adjustment cell to be laid out is larger than the lower limit value of the wiring capacity of the adjustment cell in the library. A layout method characterized by causing the arithmetic processing unit to execute a process for determining the value.

Images