CN109960866B - Signal processing method, verification method and electronic equipment - Google Patents

Signal processing method, verification method and electronic equipment Download PDF

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CN109960866B
CN109960866B CN201910213600.9A CN201910213600A CN109960866B CN 109960866 B CN109960866 B CN 109960866B CN 201910213600 A CN201910213600 A CN 201910213600A CN 109960866 B CN109960866 B CN 109960866B
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signal
bit width
list
signals
data type
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CN109960866A (en
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彭琅
冯春阳
黄晶
王俊杰
张兴革
刘刚
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Hexin Technology Suzhou Co ltd
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Abstract

The invention relates to the technical field of signal processing, in particular to a signal processing method, a verification method and electronic equipment, wherein the signal processing method comprises the steps of acquiring a list of signals to be processed; the list of signals to be processed corresponds to a first language; inquiring a preset bit width and a data storage mode; the data storage mode comprises a big end mode and a small end mode; processing signals of each data type in the signal list to be processed according to the preset bit width and the data storage mode to obtain a first signal list and a second signal list; wherein the first signal list corresponds to the first language and the second signal list corresponds to the second language; and establishing a mapping relation between the signals in the first signal list and the second signal list. And processing the signals of each data type in the signal to be processed list by using a preset bit width and a data storage mode so as to obtain a data structure with both compatible sides and ensure one-to-one correct mapping between the signals.

Description

Signal processing method, verification method and electronic equipment
Technical Field
The invention relates to the technical field of signal processing, in particular to a signal processing method, a verification method and electronic equipment.
Background
In the design of a processor, a C model is often used for verifying the function of an instruction set, DPI is introduced into Systemverilog, and C, C + + and other non-verilog programming languages can be simply connected; the c code can read the stimulus, contain the reference model, or expand the sv function to achieve data access to the shared memory area. Therefore, DPI is widely used in digital hardware design and verification in recent years.
Under the conditions that the quantity of data of interaction interfaces of a plurality of systems mverilog and C is small and the types of data are few (such as supported basic data types, simple arrays and structure bodies), the DPI can conveniently realize the communication between the two systems mverilog and C; when the data volume of the interactive interface is large, a file reading mode is usually adopted at present, and the real-time performance of the mode is poor.
Therefore, the DPI interface is often used to transmit directly in the prior art, but some problems caused by DPI communication are encountered during debugging. Since each variable passed through DPI has two matching definitions, one in the systemveirlog language and one in the c language, it is necessary to ensure that compatible data types are used, otherwise communication errors may result, and there is a basic data type mapping relationship between sv and c, but some mappings are not accurate.
Disclosure of Invention
In view of this, embodiments of the present invention provide a signal processing method, a signal verification method and an electronic device, so as to solve the problem that a mapping relationship is inaccurate due to data types of two languages.
According to a first aspect, an embodiment of the present invention provides a signal processing method, including:
acquiring a list of signals to be processed; wherein the list of signals to be processed corresponds to a first language;
inquiring a preset bit width and a data storage mode; the data storage mode comprises a big end mode and a small end mode;
processing signals of each data type in the signal list to be processed according to the preset bit width and a data storage mode to obtain a first signal list and a second signal list; wherein the first signal list corresponds to the first language and the second signal list corresponds to the second language;
and establishing a mapping relation between the signals in the first signal list and the second signal list.
In the signal processing method provided by the embodiment of the invention, the inventor discovers that the reason for incompatibility of the data structures on the two sides is the bit width and the data storage mode of the signals through analyzing the data structures on the two sides, so that the method uses the preset bit width and the data storage mode to process the signals of each data type in the signal list to be processed, thereby obtaining the data structures with both sides compatible, and ensuring one-to-one correct mapping between the signals.
With reference to the first aspect, in a first implementation manner of the first aspect, the processing, according to the preset bit width and the data storage mode, signals of each data type in the to-be-processed signal list to obtain a first signal list and a second signal list includes:
expanding the bit width of the signal of each data type in the signal list to be processed based on the preset bit width;
solidifying the position of each signal in a compressed data structure corresponding to the first language by using the expanded bit width to obtain a first signal list;
solidifying the position of each signal in the structure corresponding to the second language based on the data storage pattern and the position of each signal in the compressed data structure corresponding to the first language to obtain the second signal list.
The signal processing method provided by the embodiment of the invention can ensure the corresponding relation between the signals on the two sides in different compression modes by expanding the bit width of the signal of each data type and the bit width related to the preset bit width.
With reference to the first implementation manner of the first aspect, in a second implementation manner of the first aspect, the expanding, based on the preset bit width, a bit width of a signal of each data type in the to-be-processed signal list includes:
judging whether the data type of the signal is a basic data type;
when the data type of the signal is the basic data type, expanding the bit width of the signal by using the size relation between the bit width of the basic data type and the preset bit width;
and when the data type of the signal is a composite data type, expanding the bit width of the composite data type by utilizing the size relation between the total bit width of all signals in the composite data type and the preset bit width.
With reference to the second implementation manner of the first aspect, in a third implementation manner of the first aspect, the expanding the bit width of the signal by using a size relationship between the bit width of the basic data type and the preset bit width includes:
when the bit width of the basic data type is smaller than the preset bit width, expanding the bit width of the signal to the preset bit width;
and when the bit width of the basic data type is larger than the preset bit width, expanding the bit width of the signal to be integral multiple of the preset bit width.
According to the signal processing method provided by the embodiment of the invention, the bit width is expanded to the preset bit width or the integral multiple of the preset bit width, so that each complete element data can be independently used on both sides, and a better determined position in the compression structure bodies on both sides can be ensured when data needs to be newly supplemented.
With reference to the second implementation manner of the first aspect, in a fourth implementation manner of the first aspect, expanding a bit width of the composite data type by using a size relationship between a total bit width of all signals in the composite data type and the preset bit width includes:
and when the total bit width of all signals in the composite type is non-integral multiple of the preset bit width, expanding the bit width of the composite data type to integral multiple of the preset bit width.
According to the signal processing method provided by the embodiment of the invention, the bit width is expanded to the preset bit width or the integral multiple of the preset bit width, so that each complete element data can be independently used on both sides, and a better determined position in the compression structure bodies on both sides can be ensured when new data needs to be supplemented.
With reference to the first embodiment of the first aspect, in a fifth embodiment of the first aspect, the solidifying, by using the expanded bit width, a position of each signal in a compressed data structure body corresponding to the first language to obtain the first signal list includes:
comparing the bit width corresponding to each signal;
and sequentially solidifying the signals with the bit widths from large to small from the low bit to the high bit of the compressed data structure body to obtain the first signal list.
According to the signal processing method provided by the embodiment of the invention, the signals are arranged according to the bit width, so that the orderliness and regularity of the arrangement of the signals can be realized, and conditions are provided for the subsequent establishment of the corresponding relation between the two sides.
With reference to the fifth implementation manner of the first aspect, in the sixth implementation manner of the first aspect, based on the data storage mode and the position of each of the signals in the compressed data structure corresponding to the first language, solidifying the position of each of the signals in the structure corresponding to the second language includes:
when the data storage mode is a big-end mode, solidifying the position of each signal in the structure body corresponding to the second language according to the sequence of the position of each signal in the first signal list;
and when the data storage mode is a small-end mode, solidifying the position of each signal in the structural body corresponding to the second language according to the reverse order of the position of each signal in the signal list.
In the signal processing method according to the embodiment of the present invention, since the data storage corresponding to the second language depends on the data storage mode, the positions of the signals in the structure corresponding to the second language can be determined by combining the order of the positions of the signals in the first signal list on the basis of the data storage mode.
With reference to the first aspect, or any implementation manner of the first aspect, in a seventh implementation manner of the first aspect, the method further includes:
outputting the first signal list and the second signal list in a text form.
According to the signal processing method provided by the embodiment of the invention, the first signal list and the second signal list are output in a text form, and corresponding files are directly called when needed, so that the compatibility of data structures on two sides in subsequent verification can be ensured.
According to a second aspect, an embodiment of the present invention further provides a verification method, including:
sending a list of signals to be verified;
calling a first signal list and a second signal list, and verifying the signal to be verified by using the mapping relation between the first signal list and the second signal list; wherein the first signal list and the second signal list are obtained according to the first aspect of the present invention or the signal processing method described in any embodiment of the first aspect.
According to the verification method provided by the embodiment of the invention, the signal processing method is utilized to process the signals of each data type in the signal list to be verified to obtain the data structures compatible at two sides, the corresponding relation of the data at two sides is constructed, and the constructed corresponding relation is directly utilized to process the data of the corresponding language during verification.
According to a third aspect, an embodiment of the present invention further provides an electronic device, including:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, and the processor executing the computer instructions to perform the signal processing method according to the first aspect of the present invention or any of the embodiments of the first aspect, or the verification method according to the second aspect of the present invention.
According to a fourth aspect, the present invention further provides a computer-readable storage medium, which stores computer instructions for causing a computer to execute the first aspect of the present invention, the signal processing method described in any embodiment of the first aspect, or the verification method described in the second aspect of the present invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of the data flow of a verification platform according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a signal interface between a C-side and an SV-side in the prior art;
FIG. 3 is a schematic diagram of the compression structure of C and SV in the prior art;
FIG. 4 is a flow chart of a signal processing method according to an embodiment of the present invention;
FIG. 5 is a flow chart of a signal processing method according to an embodiment of the present invention;
FIG. 6 is a flow chart of a signal processing method according to an embodiment of the present invention;
FIG. 7 is a process flow diagram of a data structure according to an embodiment of the invention;
FIG. 8 is a flow chart of a signal processing method according to an embodiment of the present invention;
FIG. 9 is a flow diagram of a verification method according to an embodiment of the invention;
fig. 10 is a block diagram of a configuration of a signal processing apparatus according to an embodiment of the present invention;
fig. 11 is a block diagram of a configuration of a signal processing apparatus according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The signal processing method of the present invention can be applied to the design of a processor, for example, in the verification of an instruction set. For example, referring to FIG. 1, the flow of data during instruction set validation is shown in FIG. 1. In particular, in the Power processor, the VSU execution unit is implemented as a body of numerous fixed-point, floating-point, scalar, vector computation instructions, which inputs (small data volumes such as the opcode iop, operand operands, etc.), outputs (state returned to upstream, small data volumes), and internal register files VRF (large data volumes), software architecture registers SAR (large data volumes). The Reference model (Reference) is implemented as software for the corresponding instructions described above, with the same inputs, outputs, VRF, and SAR.
As shown in fig. 1, two ends of the DPI communication respectively correspond to a hardware function module and a software algorithm module, wherein the hardware function module (ISU and LSU), and the software algorithm module (Reference) adopt different programming languages to implement corresponding functions, the hardware function module adopts a hardware description language verilog or a systemverilog, and the software algorithm module can adopt C, C + +, matlab, etc. Data communication between the two devices in the verification environment inevitably faces the problems of difference between hardware language and software language, diversity, complexity, data size and the like of communication data. The data flow as the thick line in fig. 1 needs to use DPI communication.
The interface signals comprise hundreds of signals of various data types and large data volumes VRF and SAR, and are subjected to interval compression and non-interval compression on two sides, after DPI, the signals on the two sides are matched one by one, which is difficult to achieve, and debugging is more difficult if signal deletion exists subsequently.
Since one end of the DPI is connected to a hardware function module, that is, corresponding to SV language, and the other end is connected to a software program module, corresponding to C, C + +, etc., in the following description, the software program module is described in detail by taking C language as an example, but the scope of the present invention is not limited thereto, and may also be other programming languages.
Referring to fig. 2, when the C model and the SV communicate with each other using simple interface data, that is, interface expansion using DPI is performed according to the basic mapping relationship of data types of the C side and the SV side, an expansion error is likely to occur. The inventor finds that both SV and C can use a structure struct to model complex data types in the research process of C and SV; when the data types are more, the struct data types are suitable. For C, the processor typically stores the data in a compressed manner aligned with the ideal boundary, i.e., the byte-aligned systeverilog-side data structure adopts a compressed structure. That is, the compressed data structure data compression method of C is different from the compressed data structure storage compression method of SV. If the data is not considered and planned to be directly transmitted through the DPI, the data taken by the two-side codes from the memory is different. Since side c is typically compressed with 32-bits aligned, there are gaps (padding, leaving some bytes free to align data with boundaries); whereas the compression of sv is gapless. Referring to fig. 3, when the vector is transmitted from sv side to c side, a in c side does not obtain the value of a [ 24; similarly, when c-side transfers to sv-side, data is lost upon receipt of sv { a [8 ]:24, _ 8' b0 }. Based on this, the invention provides a signal processing method, and the signal processing method and the verification method provided by the invention adopt script (python or perl) to automatically process.
In accordance with an embodiment of the present invention, there is provided an embodiment of a signal processing method, it should be noted that the steps illustrated in the flowchart of the accompanying drawings may be executed in a computer system such as a set of computer executable instructions, and that while a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be executed in an order different than that herein.
In the present embodiment, a signal processing method is provided, which can be used in the electronic device, and fig. 4 is a flowchart of the signal processing method according to the embodiment of the present invention, as shown in fig. 4, the flowchart includes the following steps:
and S11, acquiring a signal list to be processed.
Wherein the list of signals to be processed corresponds to a first language. Hereinafter, the first language is SV language and the second language is C language.
Specifically, the to-be-processed signal list is a set of signals of each data type, and includes that in the data processing process, the signals need to be transmitted from the hardware function module side to the reference model side, and then the signals in the to-be-processed signal list are signals formed by the hardware function module side. For example:
Bit[9:0]vs_p0_iop；
Bit[5:0]vs_p0_route；
Bit[2:0]vs_p0_thread_id；
Bit[7:0]vs_p0_itag；
Bit[63:0]fx_vx_lu0_data；
Typedef struct packed{
bit[7:0]flag；
bit[15:0]ecc；
bit[127:0]data；
}VRF_SAR_entry；
VRF_SAR_entry[7:0][127:0]SAR；
VRF_SAR_entry[143:0]VRF；
the data types related in the signal list include Bit, struct packet and two-dimensional data, and the signals include: vs _ p0_ iop, vs _ p0_ route, vs _ p0_ thread _ id, vs _ p0_ itag, fx _ vx _ lu0_ data, flag, and so on.
And S12, inquiring the preset bit width and the data storage mode.
The data storage mode comprises a big end mode and a small end mode. And querying the preset bit width and the data storage mode by adopting a script language. Specifically, the preset bit width may be 32 bits, 64 bits, 128 bits, and so on.
And S13, processing the signals of each data type in the signal list to be processed according to the preset bit width and the data storage mode to obtain a first signal list and a second signal list.
Wherein the first signal list corresponds to a first language and the second signal list corresponds to a second language.
Processing the signals of each data type in the signal list to be processed into a data structure compatible with both the SV side and the C side, and processing the signals of each data type according to the bit width and the data storage mode of the processor, for example, expanding the bit width of the signals of each data type into integral multiple of the bit width of the processor, and simultaneously considering the data storage mode, so that each signal can independently use each complete element data and the signals are in one-to-one correspondence; or expanding the signals of each data type into signals with the same bit width and the bit width being an integral multiple of the preset bit width, and considering the data storage mode and the like.
It should be noted that the processing of the signal is not limited to this, and it is only necessary to ensure that the processing is performed by using the preset bit width and the data storage mode during the processing. In the following description, this step will be described in detail.
And S14, establishing a mapping relation between the signals in the first signal list and the second signal list.
When the processor obtains the first signal list and the second signal list, the mapping relation of the signals is sequentially established according to the storage sequence of the signals, and therefore one-to-one correspondence of the signals on the two sides is achieved.
In the signal processing method provided by this embodiment, the inventor analyzes the data structures on both sides to find out that the reason for the incompatibility of the data structures on both sides is the bit width and the data storage mode of the signal, and therefore, the inventor proposes to process the signal of each data type in the to-be-processed signal list by using the preset bit width and the data storage mode, so as to obtain the data structures on both sides that are compatible, and ensure one-to-one correct mapping between the signals.
In this embodiment, a signal processing method is further provided, which can be used in the electronic device described above, and fig. 5 is a flowchart of the signal processing method according to the embodiment of the present invention, as shown in fig. 5, the flowchart includes the following steps:
and S21, acquiring a signal list to be processed.
Wherein the list of signals to be processed corresponds to a first language. Please refer to S11 in fig. 4 for details, which are not described herein.
And S22, inquiring the preset bit width and the data storage mode.
The data storage mode comprises a big end mode and a small end mode. Please refer to S12 in fig. 4 for details, which are not described herein.
And S23, processing the signals of each data type in the signal list to be processed according to the preset bit width and the data storage mode to obtain a first signal list and a second signal list.
Wherein the first signal list corresponds to a first language and the second signal list corresponds to a second language. The processor expands the bit width of the signal of each data type in the signal list to be processed by using the preset bit width, and then sorts and sorts the expanded signal of each data type to obtain a first signal list and a second signal list respectively. Specifically, the method comprises the following steps:
s231, expanding the bit width of the signal of each data type in the signal list to be processed based on the preset bit width.
When the bit width of the signal of each data type is expanded, the bit width of the signal of each data type may be expanded to an integer multiple of the preset bit width, or the bit width of the signal of each data type may be expanded to the same bit width, which is an integer multiple of the preset bit width.
S232, solidifying the position of each signal in the compressed data structure corresponding to the first language by using the expanded bit width to obtain a first signal list.
After the bit width of each signal in the signal list is expanded, the signals are sequentially arranged according to the size of the bit width, and specifically, the method may include the following steps:
(1) And comparing the bit widths corresponding to the signals.
(2) And sequentially solidifying signals with the bit width from large to small from the low bit to the high bit of the compressed data structure body to obtain a first signal list.
Solidifying each signal position in a compressed data structure according to the signal name, wherein the bit widths are the same and are arranged according to the letter sequence of the signals; a large bit width arranged at a lower level of a compressed data structure corresponding to a first language; a small bit width arranged at a high bit of the compressed data structure; big data composite data type, placed in the lowest order.
S233, the position of each signal is solidified in the structure corresponding to the second language based on the data storage pattern and the position of each signal in the compressed data structure corresponding to the first language to obtain a second signal list.
The data storage mode comprises a big end mode and a small end mode. The big-end mode means that the high order bits of data are stored in the low address of the memory and the low order bits of data are stored in the high address of the memory, and such a storage mode is similar to the sequential processing of data as a character string, the addresses increase from small to large, and the data is put from the high order bits to the low order bits. The small-end mode means that the high order bits of data are stored in the high address of the memory and the low order bits of data are stored in the low address of the memory.
Since the positions of the signals in the first signal list are fixed and the data storage corresponding to the second language is dependent on the data storage mode, when the second signal list is formed, if the one-to-one correspondence between the signals in the first signal list and the signals in the second signal list is to be ensured, the signals in the first signal list need to be rearranged in combination with the data storage mode, and the second signal list can be obtained. Specifically, when the data storage mode is the big-end mode, the positions of the signals are solidified in the structure body corresponding to the second language in the order of the positions of the signals in the first signal list; that is, in the big-end mode, the order of each signal in the second signal list is the same as the order of each signal in the first signal list.
When the data storage mode is the small-end mode, solidifying the positions of the signals in the structural body corresponding to the second language in the reverse order of the positions of the signals in the signal list; that is, in the small-end mode, the sequence of each signal in the second signal list is opposite to the sequence of each signal in the first signal list.
And S24, establishing a mapping relation between the signals in the first signal list and the second signal list.
Please refer to S14 in fig. 4 for details, which are not described herein.
Alternatively, the first signal list and the second signal list may be output in a text form.
The signal processing method provided in this embodiment expands the bit width of the signal of each data type, which is related to the preset bit width, so as to ensure the corresponding relationship between the signals on the two sides in different compression modes.
As an optional implementation manner of this embodiment, a specific application scenario is that the c-side is an instruction set model of a computing unit, and accepts an operation code, an operand, a control signal (a part of single bits), a register, an output status signal (a part of boolean types), and a register array on the systemverilog side; from the data type bit width alone, there are 1bit, less than 8bit, bytes, half word, word, double word, quad word,152 bit. When the sequence of the data elements of the compressed structure is arranged, if one type of data needs to be supplemented, a proper position is found for insertion; and in some single bit data rendezvous in a word, an additional shift and mask operation must be added when the c side is used. Therefore, it is necessary to expand the Bit width at this time, that is, signals of a data type of less than 32 bits on the system variation side are all defined as 32 bits. Greater than 32 bits but not integer multiples of 32 (e.g., some complexes 152 bits) to integer multiples of 32 (e.g., 192, sv side is gapless compressed; if the processors are 64-Bit aligned, to integer multiples of 32 to ensure data integrity after compression); c, the compressed structure body output by the side c, the data with the size smaller than 32 bits are all sent out by using the data type of 32 bits; thus, both sides can independently use each complete element data; and if the data to be newly supplemented is well positioned in the compression structure on both sides. Specifically, as shown in fig. 6, S231 includes the steps of:
and S3.1, judging whether the data type of the signal is the basic data type.
The script language can determine whether the data type is a basic data type or a composite data type by using the keywords of each data type. When the data type of the signal is the basic data type, S3.2 is executed; s3.3 is performed when the data type of the signal is a composite data type.
And S3.2, expanding the bit width of the signal by utilizing the size relation between the bit width of the basic data type and the preset bit width.
Specifically, when the bit width of the basic data type is smaller than the preset bit width, the bit width of the signal is expanded to the preset bit width. For example, if the predetermined bit width is 32 bits and the bit width of a signal is 13 bits, the bit width of the signal is extended to 32 bits.
And when the bit width of the basic data type is larger than the preset bit width, expanding the bit width of the signal to be integral multiple of the preset bit width. For example, if the predetermined bit width is 32 bits and the bit width of a signal is 45 bits, the bit width of the signal may be extended to 64 bits, or 96 bits. Further, in order to solve the data storage resource, the bit width of the signal may be extended to (M/N + 1), where M is the bit width of a certain signal and N is a preset bit width.
And S3.3, expanding the bit width of the composite data type by utilizing the size relation between the total bit width of all signals in the composite data type and the preset bit width.
Specifically, when the total bit width of all signals in the composite data type is a non-integer multiple of the preset bit width, the bit width of the composite data type is expanded to an integer multiple of the preset bit width. For example, referring to the example in S11 of the embodiment shown in fig. 4, in the composite data type struct packet, the total bit width of all signals is 8+16+128=152; when the preset bit width is 32 bits, the bit width of the composite data type can be extended to 192 bits. Similarly, in order to save data storage resources, the bit width may be extended to (M/N + 1), where M is the total bit width of all signals in the composite data type, and N is the preset bit width.
As a specific implementation manner of this embodiment, please refer to fig. 7 and 8, which are used to perform signal processing on the signal list of SV language to obtain signal lists of SV language and C language, and output the signal lists in text form. The method mainly comprises the following steps: (1) expanding the bit width of each signal in the signal list; (2) Sorting the signals by using the size relation between the expanded bit width and the bit width of the processor to obtain a signal list of an SV side; (3) Sorting the signals by using a data storage mode and a signal list of an SV side to obtain a signal list of a C side; (4) Two signal lists are output in text form (i.e., SV side is. SV, C side is. H). And directly calling the two signal lists in the text form by the subsequent verification platform in the verification process.
The signal processing method provided by this embodiment constructs a compressed data structure from several perspectives, such as data type of an interface signal, different compression modes of the systemverilog side and the c side, sequential characteristics of two-side structure elements when data in a shared memory area are stored uniformly, convenience of new signal expansion by an interface, and integrity of two-side used structure element data, when DPI is used. The data packet signal list is read in a script mode, the data structure body structures on two sides are automatically completed, and the signals are correctly mapped one to one under the condition that various data sets are integrated in two different compression modes. The compressed data structure bodies on two sides are constructed in a script automation flow mode, the DPI communication scene with a plurality of signals, large data volume and complex data types can be effectively solved, the input and output interface is more convenient to supplement and expand signals, and the structure bodies can be more conveniently used on both a systemverilog side and a c side, so that the system is particularly suitable for instruction set verification of a processor computing unit.
In accordance with an embodiment of the present invention, there is provided an embodiment of a method of authentication, it being noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
In this embodiment, an authentication method is provided, which can be used in the electronic device described above, and fig. 9 is a flowchart of a signal processing method according to an embodiment of the present invention, as shown in fig. 9, the flowchart includes the following steps:
and S41, sending a list of signals to be verified.
Specifically, the signals output from the hardware side of the verification platform may be stored in the form of a signal list, and the data in the signal list may be understood as data related to the data to be verified, and the set of the data is referred to as a signal list to be verified. Wherein, the list of the signals to be verified is represented in text form.
The script language can directly call the list of the signals to be verified, and the signals are processed to obtain a first signal list and a second signal list.
And S42, calling the first signal list and the second signal list, and verifying the signal to be verified by using the mapping relation between the first signal list and the second signal list.
Wherein the first signal list and the second signal list are obtained according to the signal processing method in any one of the above embodiments. For details of the specific steps of the signal processing method, please refer to the detailed description of the embodiments shown in fig. 4-6, which is not repeated herein.
The verification platform can realize the one-to-one corresponding calling of the signals by directly utilizing the first signal list, the second signal list and the corresponding relation in the verification process, so that the problem of mapping errors is avoided.
In the verification method provided by this embodiment, the signal processing method is used to process the signal of each data type in the signal list to be verified to obtain the data structure compatible on both sides, and construct the corresponding relationship between the data on both sides, and during verification, the constructed corresponding relationship is directly used to process the data in the corresponding language.
In this embodiment, a signal processing apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description of the apparatus is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
The present embodiment provides a signal processing apparatus, as shown in fig. 10, including:
an obtaining module 51, configured to obtain a list of signals to be processed; wherein the list of signals to be processed corresponds to a first language.
The query module 52 is configured to query a preset bit width and a data storage mode; the data storage mode comprises a big end mode and a small end mode.
The signal processing module 53 is configured to process signals of each data type in the to-be-processed signal list according to the preset bit width and the data storage mode to obtain a first signal list and a second signal list; wherein the first signal list corresponds to the first language and the second signal list corresponds to the second language.
A mapping relationship establishing module 54, configured to establish a mapping relationship between the signals in the first signal list and the signals in the second signal list.
In the signal processing apparatus provided in this embodiment, the inventor finds, through analysis on the data structures on the two sides, that the reason why the data structures on the two sides are incompatible is the bit width of the signal and the data storage mode, and therefore proposes to process the signal of each data type in the to-be-processed signal list by using the preset bit width and the data storage mode, so as to obtain the data structures on the two sides that are compatible, and ensure one-to-one correct mapping between the signals.
The present embodiment also provides an authentication apparatus, as shown in fig. 11, the apparatus including:
the sending module 61 is configured to send a list of signals to be verified.
A calling module 62, configured to call a first signal list and a second signal list, and verify the signal to be verified by using a mapping relationship between the first signal list and the second signal list; wherein the first signal list and the second signal list are obtained according to the first aspect of the present invention or the signal processing method described in any embodiment of the first aspect.
According to the verification device provided by the embodiment of the invention, the signal processing method is utilized to process the signals of each data type in the signal list to be verified to obtain the data structures compatible at two sides, the corresponding relation of the data at two sides is established, and the established corresponding relation is directly utilized to process the data of the corresponding language during verification.
The signal processing means or verification means in this embodiment is presented in the form of functional units, where a unit refers to an ASIC circuit, a processor and memory executing one or more software or fixed programs, and/or other devices that may provide the above-described functionality.
Further functional descriptions of the modules are the same as those of the corresponding embodiments, and are not repeated herein.
An embodiment of the present invention further provides an electronic device, which has the signal processing apparatus shown in fig. 10 or the verification apparatus shown in fig. 11.
Referring to fig. 12, fig. 12 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, and as shown in fig. 12, the electronic device may include: at least one processor 71, such as a CPU (Central Processing Unit), at least one communication interface 73, memory 74, at least one communication bus 72. Wherein the communication bus 72 is used to enable connection communication between these components. The communication interface 73 may include a Display (Display) and a Keyboard (Keyboard), and the optional communication interface 73 may also include a standard wired interface and a standard wireless interface. The Memory 74 may be a high-speed RAM Memory (volatile Random Access Memory) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The memory 74 may alternatively be at least one memory device located remotely from the processor 71. Wherein the processor 71 may be combined with the apparatus described in fig. 10 or fig. 11, the application program is stored in the memory 74, and the processor 71 calls the program code stored in the memory 74 for performing any of the method steps described above.
The communication bus 72 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus 72 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 12, but that does not indicate only one bus or one type of bus.
The memory 74 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: flash memory), such as a Hard Disk Drive (HDD) or a solid-state drive (SSD); the memory 74 may also comprise a combination of memories of the kind described above.
The processor 71 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP.
The processor 71 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
Optionally, the memory 74 is also used for storing program instructions. Processor 71 may invoke program instructions to implement a signal processing method as shown in the embodiments of fig. 4-6 of the present application or an authentication method as shown in the embodiment of fig. 8.
Embodiments of the present invention further provide a non-transitory computer storage medium, where computer-executable instructions are stored, and the computer-executable instructions may execute the signal processing method or the verification method in any of the above method embodiments. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims (10)

1. A signal processing method, comprising:
acquiring a list of signals to be processed; wherein the list of signals to be processed corresponds to a first language;
inquiring a preset bit width and a data storage mode; the data storage mode comprises a big end mode and a small end mode;
processing signals of each data type in the signal list to be processed according to the preset bit width and the data storage mode to obtain a first signal list and a second signal list; wherein the first signal list corresponds to the first language and the second signal list corresponds to the second language;
establishing a mapping relation between each signal in the first signal list and each signal in the second signal list;
wherein, according to the preset bit width and the data storage mode, processing the signals of each data type in the signal list to be processed to obtain a first signal list and a second signal list, including:
expanding the bit width of the signal of each data type in the signal list to be processed based on the preset bit width;
solidifying the position of each signal in a compressed data structure body corresponding to the first language by using the expanded bit width to obtain a first signal list;
solidifying the position of each signal in the structure corresponding to the second language based on the data storage pattern and the position of each signal in the compressed data structure corresponding to the first language to obtain the second signal list.
2. The method according to claim 1, wherein said extending, based on the preset bit width, the bit width of the signal of each data type in the to-be-processed signal list includes:
judging whether the data type of the signal is a basic data type;
when the data type of the signal is the basic data type, expanding the bit width of the signal by using the size relation between the bit width of the basic data type and the preset bit width;
and when the data type of the signal is a composite data type, expanding the bit width of the composite data type by using the size relation between the total bit width of all signals in the composite data type and the preset bit width.
3. The method according to claim 2, wherein the expanding the bit width of the signal by using the magnitude relationship between the bit width of the basic data type and the preset bit width comprises:
when the bit width of the basic data type is smaller than the preset bit width, expanding the bit width of the signal to the preset bit width;
and when the bit width of the basic data type is larger than the preset bit width, expanding the bit width of the signal to be integral multiple of the preset bit width.
4. The method according to claim 3, wherein expanding the bit width of the composite data type by using the size relationship between the total bit width of all signals in the composite data type and the preset bit width comprises:
and when the total bit width of all signals in the composite data type is non-integral multiple of the preset bit width, expanding the bit width of the composite data type to integral multiple of the preset bit width.
5. The method of claim 1, wherein said using the expanded bit width to solidify the position of each of the signals in the compressed data structure corresponding to the first language to obtain the first signal list comprises:
comparing the bit width corresponding to each signal;
and sequentially solidifying the signals with the bit widths from large to small from the low bit to the high bit of the compressed data structure body to obtain the first signal list.
6. The method of claim 5, wherein solidifying the location of each of the signals in the structure corresponding to the second language based on the data storage schema and the location of each of the signals in the compressed data structure corresponding to the first language comprises:
when the data storage mode is a big-end mode, solidifying the position of each signal in the structure body corresponding to the second language according to the sequence of the position of each signal in the first signal list;
and when the data storage mode is a small-end mode, solidifying the position of each signal in the structural body corresponding to the second language according to the reverse order of the position of each signal in the signal list.
7. The method according to any one of claims 1-6, further comprising:
outputting the first signal list and the second signal list in a text form.
8. A method of authentication, comprising:
sending a list of signals to be verified;
calling a first signal list and a second signal list, and verifying the signal to be verified by using the mapping relation between the first signal list and the second signal list; wherein the first signal list and the second signal list are obtained by the signal processing method according to any one of claims 1 to 7.
9. An electronic device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, and the processor executing the computer instructions to perform the signal processing method according to any one of claims 1 to 7, or the authentication method according to claim 8.
10. A computer-readable storage medium storing computer instructions for causing a computer to execute the signal processing method according to any one of claims 1 to 7 or the authentication method according to claim 8.
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