CN109960866A - Signal processing method, verification method and electronic equipment - Google Patents
Signal processing method, verification method and electronic equipment Download PDFInfo
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- CN109960866A CN109960866A CN201910213600.9A CN201910213600A CN109960866A CN 109960866 A CN109960866 A CN 109960866A CN 201910213600 A CN201910213600 A CN 201910213600A CN 109960866 A CN109960866 A CN 109960866A
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Abstract
The present invention relates to signal processing technology fields, and in particular to signal processing method, verification method and electronic equipment, wherein signal processing method includes obtaining signal list to be processed；The signal list to be processed corresponds to first language；Inquire default bit wide and data model storage；Wherein, data model storage includes big end mode and little endian mode；According to the default bit wide and data model storage, the signal of each data type in the signal list to be processed is handled, to obtain the first signal list and second signal list；Wherein, the first signal list corresponds to the first language, and second signal list corresponds to second language；Establish the mapping relations of each signal in the first signal list and the second signal list.The signal of each data type in signal train table to be processed is handled using default bit wide and data model storage, to obtain all compatible data structure in two sides, ensure that one-to-one correct mapping between signal.
Description
Technical field
The present invention relates to signal processing technology fields, and in particular to signal processing method, verification method and electronic equipment.
Background technique
In processor design, C model is often used to instruction set functional verification, Systemverilog introduces DPI,
C, c++ and other non-verilog programming languages can simply be connected；C code can read excitation, comprising reference model or
Sv function is extended, realizes the data access to shared section key.Therefore, DPI is widely used in digital hardware design in recent years, tests
Card aspect.
Less in some systemverilog and C interactive interface data volume, data type is less (such as support basic number
According to type, simple array, structural body) in the case where, DPI can very easily realize communication between the two；When interactive interface number
When according to measuring big, the mode of file reading is generallyd use at present, and this mode real-time is poor.
Therefore, the mode directly transmitted frequently with DPI interface in the prior art, but can be encountered in debugging it is many because
The problem of DPI communication introduces.Because one is by each variable of DPI transmitting there are two the definition to match
Systemveirlog language, one is c language, therefore, to assure that is used is all compatible data type, otherwise will be led
Communication mistake is caused, has a basic DATATYPES TO relationship between sv and c, but some mappings and inaccurate.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of signal processing method, verification method and electronic equipment, to solve
The inaccurate problem of mapping relations caused by macaronic data type.
According in a first aspect, the embodiment of the invention provides a kind of signal processing methods, comprising:
Obtain signal list to be processed；Wherein, the signal list to be processed corresponds to first language；
Inquire default bit wide and data model storage；Wherein, data model storage includes big end mode and small end mould
Formula；
According to the default bit wide and data model storage, to the letter of each data type in the signal list to be processed
It number is handled, to obtain the first signal list and second signal list；Wherein, the first signal list corresponds to described the
One language, second signal list correspond to second language；
Establish the mapping relations of each signal in the first signal list and the second signal list.
Signal processing method provided in an embodiment of the present invention, inventor have found by carrying out analysis to the data structure of two sides
The reason for causing two sides data structure incompatible is the bit wide and data model storage of signal, therefore proposes using default
Bit wide and data model storage handle the signal of each data type in signal train table to be processed, to obtain two sides all
Compatible data structure ensure that one-to-one correct mapping between signal.
With reference to first aspect, described to be deposited according to the default bit wide and data in first aspect first embodiment
Storage mode handles the signal of each data type in the signal list to be processed, to obtain the first signal list and
Binary signal list, comprising:
Based on the default bit wide, the bit wide of the signal of each data type in the signal list to be processed is expanded
Exhibition；
Using the bit wide after extension, solidify each signal in the compressed data structure body for corresponding to the first language
Position, to obtain the first signal list；
Memory module and corresponding to each letter in the compressed data structure body of the first language based on the data
Number position, solidify the position of each signal, in the structural body for corresponding to the second language to obtain second letter
Number list.
Signal processing method provided in an embodiment of the present invention, by the bit wide of the signal to each data type be extended with
The default relevant bit wide of bit wide, the corresponding relationship to guarantee under different compress modes, between the signal of two sides.
First embodiment with reference to first aspect, it is described to be based on the default position in first aspect second embodiment
Width is extended the bit wide of the signal of each data type in the signal list to be processed, comprising:
Whether the data type for judging the signal is basic data type；
When the data type of the signal be the basic data type when, using the basic data type bit wide with
The size relation of the default bit wide, is extended the bit wide of the signal；
When the data type of the signal is composite data type, all signals in the composite data type are utilized
The size relation of total bit wide and the default bit wide, is extended the bit wide of the composite data type.
Second embodiment with reference to first aspect, it is described to utilize the basic number in first aspect third embodiment
According to the bit wide of type and the size relation of the default bit wide, the bit wide of the signal is extended, comprising:
When the bit wide of the basic data type is less than the default bit wide, the bit wide of the signal is extended to described
Default bit wide；
When the bit wide of the basic data type is greater than the default bit wide, the bit wide of the signal is extended to described
The integral multiple of default bit wide.
Bit wide is extended to the integer of default bit wide or default bit wide by signal processing method provided in an embodiment of the present invention
Times, so that two sides independent can use each complete element data, can guarantee when wanting new supplementary data, two sides
Relatively good determination position in pressure texture body.
Second embodiment with reference to first aspect utilizes the complex data class in the 4th embodiment of first aspect
The size relation of total bit wide of all signals and the default bit wide, expands the bit wide of the composite data type in type
Exhibition, comprising:
When total bit wide of signals all in the compound type be the default bit wide it is non-integral multiple when, will be described compound
The bit wide of data type expands to the integral multiple of the default bit wide.
Bit wide is extended to the integer of default bit wide or default bit wide by signal processing method provided in an embodiment of the present invention
Times, so that two sides independent can use each complete element data, can guarantee when wanting new supplementary data, two sides
Relatively good determination position in pressure texture body.
First embodiment with reference to first aspect, in the 5th embodiment of first aspect, the position using after extension
Width solidifies the position of each signal, in the compressed data structure body for corresponding to the first language to obtain described first
Signal list, comprising:
Compare the corresponding bit wide of each signal；
From the low level of the compressed data structure body to a high position, successively solidify the descending signal of the bit wide,
To obtain the first signal list.
Signal processing method provided in an embodiment of the present invention arranges each signal by the size according to bit wide,
It can be realized the neat and regular of each signal arrangement, provide condition for the subsequent corresponding relationship established between two sides.
5th embodiment with reference to first aspect stores mould in first aspect sixth embodiment based on the data
Formula and position corresponding to each signal in the compressed data structure body of the first language are corresponding to second language
Solidify the position of each signal in the structural body of speech, comprising:
When the data model storage be big end mode when, according in the first signal list the position of each signal it is suitable
Sequence solidifies the position of each signal in the structural body for corresponding to the second language；
When the data model storage is little endian mode, according to opposite with the position of each signal in the signal list
Sequentially, solidify the position of each signal in the structural body for corresponding to the second language.
Signal processing method provided in an embodiment of the present invention, the data storage due to corresponding to second language depend on data
Memory module, therefore, on the basis of data model storage, in conjunction with the sequence of the position of each signal in the first signal list
Determine the position of each signal in the structural body corresponding to second language.
With reference to first aspect or in first aspect any embodiment, in the 7th embodiment of first aspect, also wrap
It includes:
The first signal list and the second signal list are exported in a text form.
Signal processing method provided in an embodiment of the present invention, by the first signal list and second signal list with text
Form output is needing use to call directly corresponding file, can ensure that the two sides data structure in subsequent authentication
Compatibility.
According to second aspect, the embodiment of the invention also provides a kind of verification methods, comprising:
Send signal list to be verified；
The first signal list and second signal list are called, and utilizes the first signal list and the second signal
Mapping relations between list verify the signal to be verified；Wherein, the first signal list and described second
Signal list is to be obtained according to signal processing method described in any one of first aspect present invention or first aspect embodiment
's.
Verification method provided in an embodiment of the present invention, using signal processing method by each number in signal list to be verified
It is handled to obtain the compatible data structure in two sides according to the signal of type, and constructs the corresponding relationship of two side datas, verified
When directly handled using data of the corresponding relationship constructed to corresponding language.
According to the third aspect, the embodiment of the invention also provides a kind of electronic equipment, comprising:
Memory and processor communicate with each other connection, deposit in the memory between the memory and the processor
Computer instruction is contained, the processor is by executing the computer instruction, thereby executing first aspect present invention or first
Verification method described in signal processing method described in any one of aspect embodiment or second aspect of the present invention.
According to fourth aspect, the embodiment of the invention also provides a kind of computer readable storage medium, the computer can
It reads storage medium and is stored with computer instruction, the computer instruction is used to that the computer to be made to execute first aspect present invention,
Or authentication described in signal processing method described in any one of first aspect embodiment or second aspect of the present invention
Method.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic diagram of the data flow of verification platform according to an embodiment of the present invention；
Fig. 2 is the schematic diagram of the signaling interface between the side C and the side SV in the prior art；
Fig. 3 is the pressure texture schematic diagram of C and SV in the prior art；
Fig. 4 is the flow chart of signal processing method according to an embodiment of the present invention；
Fig. 5 is the flow chart of signal processing method according to an embodiment of the present invention；
Fig. 6 is the flow chart of signal processing method according to an embodiment of the present invention；
Fig. 7 is the process flow diagram of data structure according to an embodiment of the present invention；
Fig. 8 is the flow chart of signal processing method according to an embodiment of the present invention；
Fig. 9 is the flow chart of verification method according to an embodiment of the present invention；
Figure 10 is the structural block diagram of signal processing apparatus according to an embodiment of the present invention；
Figure 11 is the structural block diagram of signal processing apparatus according to an embodiment of the present invention；
Figure 12 is the hardware structural diagram of electronic equipment provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
Signal processing method of the present invention can be applied in the design of processor, for example, testing for instruction set
In card.For example, referring to Figure 1, the data flow in instruction set verification process is shown in FIG. 1.Specifically, Power processor
In, VSU execution unit is as numerous fixed, floating-point, scalar, vector computations realization bodies, input (such as operation code iop,
The small data quantities such as operand operand), output (returning to the state of upstream, small data quantity) and internal register file
VRF (big data quantity), software architecture register SAR (big data quantity).Reference model (Reference) is used as above-mentioned corresponding instruction
Software realization, have same input, output, VRF and SAR.
As shown in Figure 1, corresponding respectively to hardware function and software algorithm module using the both ends that DPI is communicated, wherein
Hardware function (ISU and LSU), software algorithm module (Reference), since the two uses different programming languages
Realize corresponding function, correspond to hardware function using hardware description language verilog or
Systemverilog, corresponding to software algorithm module can be using C, C++, Matlab etc..Number of the two in verification environment
According to communication, the difference of hardware language and software language, the diversity of communication data, complexity, data volume size etc. are necessarily faced
Problem.The data flow of thick line needs to use DPI communication as shown in figure 1.
Such interface signal has a signal and the big data quantity VRF and SAR up to a hundred of various data types, using
The interval compression and non-gap compression of two sides, after DPI, the signal of two sides will match one by one, be difficult to accomplish, if after
Continuous there are also signals to delete, and debugging is even more difficulty.
Due to DPI one end connect be hardware function, that is, correspond to SV language, the other end connection be software journey
Sequence module corresponds to C, C++ etc., and software program module is described in detail by taking C language as an example in the following description, still
The scope of protection of the present invention is not limited thereto, is also possible to other programming languages.
Fig. 2 is referred to, when using simple interface data to be communicated between C model and SV, i.e., is carrying out interface using DPI
Extension is if carrying out according to the basic mapping relations of data type of the side C and the side SV, to be easy to appear extended error.Inventor is right
It is found in the research process of C and SV, SV and C can use structural body struct to model complicated data type；
When data type is more, it is suitble to use struct data type.For C, processor would generally by data according to ideal
The mode compressed storage of boundary alignment, i.e. byte-aligned Systemverilog side data structure use pressure texture body.That is, C
Pressure texture volume compression mode is different from the compressed data structure body of SV storage compress mode.If without a moment's thought, planned
Directly by DPI transmit, the data that both sides code takes out in memory are different.Because the side c is usually 32 alignment
Compression has interval (padding vacates some byte, allow data and boundary alignment)；And the compression of sv is compressed without interval.Please
Referring to Fig. 3, when transmitting from the side sv to the side c, a in the side c obtains the value less than a [24:31]；Equally, when the side c is transmitted to the side sv,
Sv's receives { a [8:24], 8 ' b0 }, and data have loss.Based on this, the invention proposes a kind of signal processing methods, originally
Itd is proposed signal processing method and verification method is invented to automatically process using script (python or perl).
According to embodiments of the present invention, a kind of embodiment of signal processing method is provided, it should be noted that in attached drawing
The step of process illustrates can execute in a computer system such as a set of computer executable instructions, although also,
Logical order is shown in flow chart, but in some cases, it can be to be different from shown by sequence execution herein or retouch
The step of stating.
A kind of signal processing method is provided in the present embodiment, can be used in above-mentioned electronic equipment, and Fig. 4 is according to this
The flow chart of the signal processing method of inventive embodiments, as shown in figure 4, the process includes the following steps:
S11 obtains signal list to be processed.
Wherein, the signal list to be processed corresponds to first language.Hereinafter first language is SV language, the second language
Speech is C language.
Specifically, signal list to be processed is the set of the signal of each data type, includes in data handling procedure
In, it needs to pass to reference model side from hardware function side, then the signal in the signal list to be processed is as hard
Part functional module side is formed by signal.Such as:
Bit[9:0]vs_p0_iop；
Bit[5:0]vs_p0_route；
Bit[2:0]vs_p0_thread_id；
Bit[7:0]vs_p0_itag；
Bit[63:0]fx_vx_lu0_data；
Typedef struct packed{
bit[7:0]flag；
bit[15:0]ecc；
bit[127:0]data；
}VRF_SAR_entry；
VRF_SAR_entry[7:0][127:0]SAR；
VRF_SAR_entry[143:0]VRF；
Involved data type has Bit, struct packed and 2-D data, signal in the signal list
Have: vs_p0_iop, vs_p0_route, vs_p0_thread_id, vs_p0_itag, fx_vx_lu0_data, flag etc..
S12 inquires default bit wide and data model storage.
Wherein, data model storage includes big end mode and little endian mode.Using the default of scripting language query processing
Bit wide and data model storage.Specifically, default bit wide can be 32,64 and 128 etc..
S13, according to default bit wide and data model storage, to the signal of each data type in signal train table to be processed into
Row processing, to obtain the first signal list and second signal list.
Wherein, the first signal list corresponds to first language, and second signal list corresponds to second language.
The data knot that the signal processing of each data type in signal list to be processed is all compatible at the side SV and the side C
Structure is handled the signal of each data type according to the bit wide and data model storage of processor, for example, by each data
The bit wide of the signal of type is expanded into the integral multiple of processor bit wide, combines data model storage, so that each letter
It number can be independent using each complete element data and signal corresponds；It is also possible to the letter of each data type
Number it is extended to bit wide is identical and bit wide is the integral multiple of default bit wide, and takes into account data model storage etc..
It should be noted that the processing to signal is not limited to this, need to only guarantee it is to utilize default position during processing
Wide and data model storage carries out.In the following description, which will be described in detail.
S14 establishes the mapping relations of each signal in the first signal list and second signal list.
Processor is successively established when obtaining the first signal list and second signal list according to the storage order of each signal
The mapping relations of each signal, to realize the one-to-one correspondence of two sides signal.
Signal processing method provided in this embodiment, inventor have found to cause by carrying out analysis to the data structure of two sides
Data structure incompatible reason in two sides is the bit wide and data model storage of signal, therefore proposes and utilize default bit wide
And data model storage handles the signal of each data type in signal train table to be processed, so that it is all compatible to obtain two sides
Data structure, ensure that one-to-one correct mapping between signal.
A kind of signal processing method is additionally provided in the present embodiment, can be used in above-mentioned electronic equipment, and Fig. 5 is basis
The flow chart of the signal processing method of the embodiment of the present invention, as shown in figure 5, the process includes the following steps:
S21 obtains signal list to be processed.
Wherein, the signal list to be processed corresponds to first language.The S11 for referring to embodiment illustrated in fig. 4,
This is repeated no more.
S22 inquires default bit wide and data model storage.
Wherein, data model storage includes big end mode and little endian mode.Refer to embodiment illustrated in fig. 4
S12, details are not described herein.
S23, according to default bit wide and data model storage, to the signal of each data type in signal train table to be processed into
Row processing, to obtain the first signal list and second signal list.
Wherein, the first signal list corresponds to first language, and second signal list corresponds to second language.Processor
It is extended using bit wide of the default bit wide to the signal of each data type in signal train table to be processed, then again respectively to expansion
The signal of each data type after exhibition carries out arranging order, respectively obtains the first signal list and second signal list.Specifically
Ground, comprising the following steps:
S231 is extended the bit wide of the signal of each data type in signal train table to be processed based on default bit wide.
When being extended, the bit wide of the signal of each data type can be extended to the integral multiple of default bit wide, it can also
It the bit wide of the signal of each data type is extended to same bit-width, and is the integral multiple of default bit wide.
S232 solidifies each signal in the compressed data structure body for corresponding to first language using the bit wide after extension
Position, to obtain the first signal list.
After the bit wide extension of each signal in signal list, successively arranged according to the size of bit wide, it specifically, can be with
The following steps are included:
(1) the corresponding bit wide of more each signal.
(2) from the low level of compressed data structure body to a high position, solidify the descending signal of bit wide, successively to obtain first
Signal list.
Solidify each signal location in compressed data structure body according to signal name, wherein bit wide is identical, according to signal
Lexicographic order arranged；Bit wide is big, is arranged in the low level of the compressed data structure body corresponding to first language；Bit wide is small
, it is arranged in a high position for compressed data structure body；Big data composite data type, is placed on lowest order.
S233, based on data model storage and corresponding to the position of each signal in the compressed data structure body of first language
It sets, solidifies the position of each signal, in the structural body for corresponding to second language to obtain second signal list.
Wherein, data model storage includes big end mode and little endian mode.Big end mode refers to that a high position for data is stored in
In the low address of memory, and the low level of data is stored in the high address of memory, and such memory module, which is similar to, works as data
Make character string sequential processes, address is increased from small to big, and data are put from high-order toward low level.Little endian mode refers to the height of data
Position is stored in the high address of memory, and the low level of data is stored in the low address of memory.
Since the position of each signal in the first signal list has been fixed, and the data storage for corresponding to second language is to take
Certainly in data model storage, then when forming second signal list, it is ensured that each signal and second in the first signal list
One-to-one relationship in signal list between each signal then needs combined data memory module to each in the first signal list
A signal is arranged again, and second signal list can be obtained.Specifically, it when data model storage is big end mode, presses
According to the sequence of the position of each signal in the first signal list, solidify the position of each signal in the structural body for corresponding to second language
It sets；That is, under big end mode, the sequence phase of the sequence of each signal and each signal in the first signal list in second signal list
Together.
When data model storage is little endian mode, according to the sequence opposite with the position of each signal in signal list,
Corresponding to the position for solidifying each signal in the structural body of second language；That is, under little endian mode, each signal in second signal list
Sequence it is opposite with the sequence of each signal in the first signal list.
S24 establishes the mapping relations of each signal in the first signal list and second signal list.
The S14 of embodiment illustrated in fig. 4 is referred to, details are not described herein.
It is alternatively possible to which the first signal list and second signal list are exported using textual form.
Signal processing method provided in this embodiment is extended and is preset by the bit wide of the signal to each data type
The relevant bit wide of bit wide, the corresponding relationship to guarantee under different compress modes, between the signal of two sides.
As a kind of optional embodiment of the present embodiment, concrete application scene is the instruction set mould that the side c is computing unit
Type receives operation code, the operand, control signal (part list bit), register of the side systemverilog, output status signal
(part Boolean type), register array；Only from the point of view of data type bit wide, just there is 1bit, less than 8bit, byte,
Half_word, word, double_word, quad_word, 152bit's.When occurring arranging pressure texture volume data element properly
After sequence, if as soon as suitable position insertion must be found when needing to be supplemented the data of a type；And in certain lists
The data of bit merge in some word, and the side c must add additional displacement, masking operation when using.Therefore, it just needs at this time
Bit wide is extended, i.e. the signal of the data type less than 32bit of the side systemverilog, be defined as 32Bit entirely
's.It greater than 32Bit but is not that 32 integral multiples (such as certain association 152Bit) add to 32 integral multiples (side such as 192, sv is nothing
Interval compression；If processor is 64 alignment it is necessary to mend to 32 integral multiples, to guarantee compressed data integrity)；c
The pressure texture body of side output, data of the size less than 32 are all sent out with 32 data types；Two sides are ok in this way
It is independent to use each complete element data；If wanting new supplementary data relatively good true in the pressure texture body of two sides
Positioning is set.Specifically, as described in Figure 6, S231 the following steps are included:
S3.1 judges whether the data type of signal is basic data type.
Scripting language can determine that data type for basic data type still using the keyword of each data type
Composite data type.When the data type of signal is basic data type, S3.2 is executed；When the data type of signal is compound
When data type, S3.3 is executed.
S3.2 is extended the bit wide of signal using the bit wide of basic data type and the size relation of default bit wide.
Specifically, when the bit wide of basic data type is less than default bit wide, the bit wide of the signal is extended to default
Bit wide.For example, default bit wide is 32, the bit wide of certain signal is 13, then is 32 by the bit wide extension of the signal.
When the bit wide of basic data type is greater than default bit wide, the bit wide of the signal is extended into the whole of default bit wide
Several times.For example, default bit wide is 32, the bit wide of certain signal is 45, then the bit wide of the signal can extend to 64, or
96.Further, in order to solve data storage resource, the bit wide of signal only can be extended to (M/N+1), wherein M is certain
The bit wide of signal, N are default bit wide.
S3.3, using total bit wide of signals all in composite data type and the size relation of default bit wide, to composite number
It is extended according to the bit wide of type.
Specifically, when total bit wide of signals all in composite data type be default bit wide it is non-integral multiple when, will be compound
The bit wide of data type expands to the integral multiple of default bit wide.For example, the example in the S11 of embodiment shown in Figure 4, multiple
It closes in data type struct packed, total bit wide of all signals is 8+16+128=152；When default bit wide is 32,
Then the bit wide of composite data type can be expanded to 192.It similarly, can be only by bit wide in order to save data storage resource
Expand to (M/N+1), wherein M is total bit wide of all signals in composite data type, and N is default bit wide.
As a kind of specific embodiment of the present embodiment, incorporated by reference to Fig. 7 and Fig. 8, to the signal list of SV language into
Row signal processing obtains the signal list of SV language and C language, while exporting in a text form respectively.It is main to include:
(1) bit wide of each signal in signal list is extended；(2) using big between the bit wide of bit wide and processor after extension
Small relationship is ranked up each signal, to obtain the signal list of the side SV；(3) data model storage and the letter of the side SV are utilized
Number list, is ranked up signal, to obtain the signal list of the side C；(4) in the form of text (that is, the side SV is .sv, the side C is .h)
Export two signal lists.Subsequent authentication platform calls directly the signal list of the two textual forms i.e. in verification process
It can.
Signal processing method provided in this embodiment, when using DPI, according to the data type of interface signal,
Structure on two sides volume elements when the side systemverilog is consistent with the different characteristic of the compress mode of the side c, the storage of shared section key data
Plain sequential nature, the convenience of Interface Expanding new signal, two sides are come using these angles of the integrality of structure element data
Construct the mechanism and method of compressed data structure.Data packet signal list is read in by script mode, is automatically performed the number of two sides
It is constructed according to structural body, ensure that being integrated under two different compress modes for all kinds of different data, it is one-to-one between signal
Correct mapping.The compressed data structure body that two sides are constructed by using the script automatic flow mode of this paper, can effectively solve
The DPI communication scenes that signal is more, data volume is big, data type is complicated, input/output interface supplement extension signal is more convenient,
The side systemverilog and c can more easily use the characteristics of structural body, be particularly suitable for the instruction of processor computing unit
Collection verifying.
According to embodiments of the present invention, a kind of embodiment of verification method is provided, it should be noted that in the process of attached drawing
The step of illustrating can execute in a computer system such as a set of computer executable instructions, although also, in process
Logical order is shown in figure, but in some cases, it can be to be different from shown or described by sequence execution herein
Step.
A kind of verification method is provided in the present embodiment, can be used in above-mentioned electronic equipment, and Fig. 9 is according to the present invention
The flow chart of the signal processing method of embodiment, as shown in figure 9, the process includes the following steps:
S41 sends signal list to be verified.
Specifically, it can be stored from the signal that the hardware side of verification platform exports with the form of signal list, signal
Data in list can be understood as data relevant to data to be verified, and set is referred to as signal list to be verified.Its
In, signal list to be verified is indicated using textual form.
Scripting language can call directly the signal list to be verified, and the first signal list is obtained after handling signal
And second signal list.
S42 calls the first signal list and second signal list, and utilizes the first signal list and second signal list
Between mapping relations, the signal to be verified is verified.
Wherein, the first signal list and the second signal list are according to any of the above-described embodiment
Signal processing method obtain.About the specific steps details of signal processing method, the detailed of Fig. 4-6 illustrated embodiment is referred to
Thin description, details are not described herein.
Verification platform directly utilizes the first signal list, second signal list and corresponding relationship in verification process
The problem of realizing the one-to-one calling of signal, and avoiding the occurrence of mapping error.
Verification method provided in this embodiment, using signal processing method by each data class in signal list to be verified
The signal of type is handled to obtain the compatible data structure in two sides, and constructs the corresponding relationship of two side datas, straight in verifying
It connects and is handled using data of the corresponding relationship constructed to corresponding language.
A kind of signal processing apparatus is additionally provided in the present embodiment, and the device is real for realizing above-described embodiment and preferably
Mode is applied, the descriptions that have already been made will not be repeated.As used below, the soft of predetermined function may be implemented in term " module "
The combination of part and/or hardware.Although device described in following embodiment is preferably realized with software, hardware, or
The realization of the combination of software and hardware is also that may and be contemplated.
The present embodiment provides a kind of signal processing apparatus, as shown in Figure 10, comprising:
Module 51 is obtained, for obtaining signal list to be processed；Wherein, the signal list to be processed corresponds to the first language
Speech.
Enquiry module 52, for inquiring default bit wide and data model storage；Wherein, data model storage includes big end
Mode and little endian mode.
Signal processing module 53 is used for according to the default bit wide and data model storage, to the signal to be processed
The signal of each data type is handled in list, to obtain the first signal list and second signal list；Wherein, described first
Signal list corresponds to the first language, and second signal list corresponds to second language.
Mapping relations establish module 54, for establishing each signal in the first signal list and the second signal list
Mapping relations.
Signal processing apparatus provided in this embodiment, inventor have found to cause by carrying out analysis to the data structure of two sides
Data structure incompatible reason in two sides is the bit wide and data model storage of signal, therefore proposes and utilize default bit wide
And data model storage handles the signal of each data type in signal train table to be processed, so that it is all compatible to obtain two sides
Data structure, ensure that one-to-one correct mapping between signal.
The present embodiment additionally provides a kind of verifying device, and as shown in figure 11, which includes:
Sending module 61, for sending signal list to be verified.
Calling module 62 for calling the first signal list and second signal list, and utilizes first signal train
Mapping relations between table and the second signal list verify the signal to be verified；Wherein, first signal
List and the second signal list are according to described in any one of first aspect present invention or first aspect embodiment
What signal processing method obtained.
Verifying device provided in an embodiment of the present invention, using signal processing method by each number in signal list to be verified
It is handled to obtain the compatible data structure in two sides according to the signal of type, and constructs the corresponding relationship of two side datas, verified
When directly handled using data of the corresponding relationship constructed to corresponding language.
Signal processing apparatus in the present embodiment or verifying device are presented in the form of functional unit, unit here
Refer to ASIC circuit, execute one or more softwares or fixed routine processor and memory and/or other can provide
State the device of function.
The further function description of above-mentioned modules is identical as above-mentioned corresponding embodiment, and details are not described herein.
The embodiment of the present invention also provides a kind of electronic equipment, has above-mentioned signal processing apparatus shown in Fig. 10 or Figure 11
Shown in verify device.
Figure 12 is please referred to, Figure 12 is the structural schematic diagram for a kind of electronic equipment that alternative embodiment of the present invention provides, and is such as schemed
Shown in 12, which may include: at least one processor 71, such as CPU (Central Processing Unit, in
Central processor), at least one communication interface 73, memory 74, at least one communication bus 72.Wherein, communication bus 72 is used for
Realize the connection communication between these components.Wherein, communication interface 73 may include display screen (Display), keyboard
(Keyboard), optional communication interface 73 can also include standard wireline interface and wireless interface.Memory 74 can be high speed
RAM memory (Random Access Memory, effumability random access memory), is also possible to non-labile storage
Device (non-volatile memory), for example, at least a magnetic disk storage.Memory 74 optionally can also be at least one
It is located remotely from the storage device of aforementioned processor 71.Wherein processor 71 can be deposited in conjunction with device described in Figure 10 or Figure 11
Application program is stored in reservoir 74, and processor 71 calls the program code stored in memory 74, for executing above-mentioned
One method and step.
Wherein, communication bus 72 can be Peripheral Component Interconnect standard (peripheral component
Interconnect, abbreviation PCI) bus or expanding the industrial standard structure (extended industry standard
Architecture, abbreviation EISA) bus etc..Communication bus 72 can be divided into address bus, data/address bus, control bus etc..
Only to be indicated with a thick line in Figure 12, it is not intended that an only bus or a type of bus convenient for indicating.
Wherein, memory 74 may include volatile memory (English: volatile memory), such as arbitrary access
Memory (English: random-access memory, abbreviation: RAM)；Memory also may include nonvolatile memory (English
Text: non-volatile memory), for example, flash memory (English: flash memory), hard disk (English: hard disk
Drive, abbreviation: HDD) or solid state hard disk (English: solid-state drive, abbreviation: SSD)；Memory 74 can also include
The combination of the memory of mentioned kind.
Wherein, processor 71 can be central processing unit (English: central processing unit, abbreviation: CPU),
The combination of network processing unit (English: network processor, abbreviation: NP) or CPU and NP.
Wherein, processor 71 can further include hardware chip.Above-mentioned hardware chip can be specific integrated circuit
(English: application-specific integrated circuit, abbreviation: ASIC), programmable logic device (English:
Programmable logic device, abbreviation: PLD) or combinations thereof.Above-mentioned PLD can be Complex Programmable Logic Devices
(English: complex programmable logic device, abbreviation: CPLD), field programmable gate array (English:
Field-programmable gate array, abbreviation: FPGA), Universal Array Logic (English: generic array
Logic, abbreviation: GAL) or any combination thereof.
Optionally, memory 74 is also used to store program instruction.Processor 71 can be instructed with caller, realize such as this Shen
It please verification method shown in signal processing method or Fig. 8 embodiment shown in Fig. 4-6 embodiment.
The embodiment of the invention also provides a kind of non-transient computer storage medium, the computer storage medium is stored with
Computer executable instructions, the computer executable instructions can be performed signal processing method in above-mentioned any means embodiment or
Verification method.Wherein, the storage medium can for magnetic disk, CD, read-only memory (Read-Only Memory, ROM),
Random access memory (Random Access Memory, RAM), flash memory (Flash Memory), hard disk (Hard
Disk Drive, abbreviation: HDD) or solid state hard disk (Solid-State Drive, SSD) etc.；The storage medium can also wrap
Include the combination of the memory of mentioned kind.
Although being described in conjunction with the accompanying the embodiment of the present invention, those skilled in the art can not depart from the present invention
Spirit and scope in the case where make various modifications and variations, such modifications and variations are each fallen within by appended claims institute
Within the scope of restriction.
Claims (11)
1. a kind of signal processing method characterized by comprising
Obtain signal list to be processed；Wherein, the signal list to be processed corresponds to first language；
Inquire default bit wide and data model storage；Wherein, data model storage includes big end mode and little endian mode；
According to the default bit wide and data model storage, to the signal of each data type in the signal list to be processed into
Row processing, to obtain the first signal list and second signal list；Wherein, the first signal list corresponds to first language
Speech, second signal list correspond to second language；
Establish the mapping relations of each signal in the first signal list and the second signal list.
2. the method according to claim 1, wherein described store mould according to the default bit wide and data
Formula handles the signal of each data type in the signal list to be processed, to obtain the first signal list and the second letter
Number list, comprising:
Based on the default bit wide, the bit wide of the signal of each data type in the signal list to be processed is extended；
Using the bit wide after extension, solidify the position of each signal in the compressed data structure body for corresponding to the first language
It sets, to obtain the first signal list；
Memory module and corresponding to each signal in the compressed data structure body of the first language based on the data
Position solidifies the position of each signal in the structural body for corresponding to the second language, to obtain the second signal column
Table.
3. according to the method described in claim 2, it is characterized in that, described be based on the default bit wide, to the letter to be processed
The bit wide of the signal of each data type is extended in number list, comprising:
Whether the data type for judging the signal is basic data type；
When the data type of the signal be the basic data type when, using the basic data type bit wide with it is described
The size relation of default bit wide, is extended the bit wide of the signal；
When the data type of the signal is composite data type, total position of all signals in the composite data type is utilized
The wide size relation with the default bit wide, is extended the bit wide of the composite data type.
4. according to the method described in claim 3, it is characterized in that, the bit wide using the basic data type with it is described
The size relation of default bit wide, is extended the bit wide of the signal, comprising:
When the bit wide of the basic data type is less than the default bit wide, the bit wide of the signal is extended to described default
Bit wide；
When the bit wide of the basic data type is greater than the default bit wide, the bit wide of the signal is extended to described default
The integral multiple of bit wide.
5. according to the method described in claim 3, it is characterized in that, using all signals in the composite data type total position
The wide size relation with the default bit wide, is extended the bit wide of the composite data type, comprising:
When total bit wide of signals all in the compound type be the default bit wide it is non-integral multiple when, by the complex data
The bit wide of type expands to the integral multiple of the default bit wide.
6. according to the method described in claim 2, it is characterized in that, the bit wide using after extension, is corresponding to described the
Solidify the position of each signal in the compressed data structure body of one language, to obtain the first signal list, comprising:
Compare the corresponding bit wide of each signal；
From the low level of the compressed data structure body to a high position, successively solidify the descending signal of the bit wide, with
To the first signal list.
7. according to the method described in claim 6, it is characterized in that, memory module and corresponding to described the based on the data
The position of each signal in the compressed data structure body of one language, solidification is each in the structural body for corresponding to the second language
The position of the signal, comprising:
When the data model storage is big end mode, according to the sequence of the position of each signal in the first signal list,
Solidify the position of each signal in the structural body for corresponding to the second language；
When the data model storage is little endian mode, according to opposite with the position of each signal in the signal list suitable
Sequence solidifies the position of each signal in the structural body for corresponding to the second language.
8. method according to any one of claims 1-7, which is characterized in that further include:
The first signal list and the second signal list are exported in a text form.
9. a kind of verification method characterized by comprising
Send signal list to be verified；
The first signal list and second signal list are called, and utilizes the first signal list and the second signal list
Between mapping relations, the signal to be verified is verified；Wherein, the first signal list and the second signal
List is obtained according to signal processing method of any of claims 1-8.
10. a kind of electronic equipment characterized by comprising
Memory and processor communicate with each other connection, are stored in the memory between the memory and the processor
Computer instruction, the processor is by executing the computer instruction, thereby executing of any of claims 1-8
Signal processing method or verification method as claimed in claim 9.
11. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has computer to refer to
It enabling, the computer instruction is used to that the computer perform claim to be made to require signal processing method described in any one of 1-8, or
Verification method as claimed in claim 9.
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| CN113343629A (en) * | 2021-06-25 | 2021-09-03 | 海光信息技术股份有限公司 | Integrated circuit verification method, code generation method, system, device, and medium |
| CN115630593A (en) * | 2022-11-11 | 2023-01-20 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for generating verification information data |
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| CN103576739A (en) * | 2012-08-02 | 2014-02-12 | 中兴通讯股份有限公司 | Digital chip, device provided with digital chip and little-endian big-endian mode configuration method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103576739A (en) * | 2012-08-02 | 2014-02-12 | 中兴通讯股份有限公司 | Digital chip, device provided with digital chip and little-endian big-endian mode configuration method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113343629A (en) * | 2021-06-25 | 2021-09-03 | 海光信息技术股份有限公司 | Integrated circuit verification method, code generation method, system, device, and medium |
| CN113343629B (en) * | 2021-06-25 | 2023-02-28 | 海光信息技术股份有限公司 | Integrated circuit verification method, code generation method, system, device, and medium |
| CN115630593A (en) * | 2022-11-11 | 2023-01-20 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for generating verification information data |
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