CN114281731A

CN114281731A - Low-speed bus data transmission method and device and computer storage medium

Info

Publication number: CN114281731A
Application number: CN202111408739.2A
Authority: CN
Inventors: 王红磊; 武丽伟
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2022-04-05

Abstract

The invention provides a transmission method and a device of low-speed bus data and a computer storage medium, wherein the transmission method comprises the steps that data signals needing to be transmitted to BMC are all accessed to a first programmable device on a main board side; the first programmable device analyzes the data signal and transmits the data content to be transmitted to a second programmable device on the BMC side through a high-speed differential bus; the second programmable device analyzes the data content, restores the data to a corresponding interface of the BMC, and completes communication with the BMC.

Description

Low-speed bus data transmission method and device and computer storage medium

Technical Field

The invention relates to the technical field of server data transmission, in particular to a method and a device for transmitting low-speed bus data and a computer storage medium.

Background

With the rapid development of the times, the traffic volume of industries such as finance, communication, internet and the like is increased day by day, the requirements on the reliability and manageability of a server are higher and higher, the application of a Baseboard Management Controller (BMC) is also more and more complex, the BMC needs to have a large amount of IO connection devices to acquire a large amount of sensor data and the running state of the devices, a CPU serving the BMC needs to be updated and replaced continuously, and a mainboard is changed accordingly.

However, the BMC chip and the peripheral circuit do not change much, and the development period and the development cost can be reduced by manufacturing the BMC into a single module. After the BMC is singly clamped, interfaces of the BMC are numerous, and how to conveniently lead the IO out of each device of the mainboard becomes important.

At present, IO interfaces of BMC are directly communicated with different devices to acquire different sensor data and interface data. These buses are relatively low speed buses; the data contents are different, buses cannot be combined, and a plurality of IO and connector PIN PINs are occupied. After a mature BMC chip is mature in application, the BMC chip can not be changed greatly, the upgrading is only carried out on a BMC card, the whole board card can not be changed any more, after the BMC is independently formed into a board, the PIN number of a connector connected with a mainboard of the BMC becomes a bottleneck for realizing the BMC, the IO of the BMC is large, the width and the PIN number of the connector are limited by structure, cost and the like, and if the existing connector is used, partial functions can only be abandoned, and the loss is not paid.

Disclosure of Invention

The invention provides a low-speed bus data transmission method and device and a computer storage medium, which are used for solving the problems that the existing BMC wiring mode occupies more IO and connector PIN PINs and limits BMC upgrading.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a transmission method of low-speed bus data in a first aspect, which comprises the following steps:

the master board side accesses data signals needing to be transmitted to the BMC to a first programmable device;

the first programmable device analyzes the data signal and transmits the data content to be transmitted to a second programmable device on the BMC side through a high-speed differential bus;

and the second programmable device analyzes the data content, restores the data to a corresponding interface of the BMC and completes communication with the BMC.

Further, the first programmable logic device and the second programmable logic device are both CPLDs.

Further, the first programmable logic device and the second programmable logic device are both FPGAs.

Further, the data signals include I2C data signals, SPI data signals, LPC data signals, SGPIO data signals, JTAG data signals, VGA data signals, and GPIO data signals.

Further, the specific process of analyzing the data signal by the first programmable device is as follows:

acquiring the data signal through a low-speed bus IO interface;

and classifying the data signals, and classifying and storing the data content into the device.

Further, the specific process of analyzing the data content by the second programmable device is as follows:

classifying data contents acquired through a high-speed differential bus;

and storing the classified data content into the device.

Further, the first programmable device and the second programmable device are both provided with a storage module for temporarily storing the data content.

The invention provides a transmission device of low-speed bus data, which comprises a mainboard and a BMC (baseboard management controller), and is characterized in that a first programmable device is arranged on the mainboard, and a second programmable device is arranged on the BMC board;

the first programmable device acquires a data signal required to be transmitted to the BMC on the main board side, analyzes the data signal, and transmits data content required to be transmitted to a second programmable device on the BMC side through a high-speed differential bus;

A third aspect of the invention provides a computer storage medium having stored thereon computer instructions which, when run on the transmission apparatus, cause the transmission apparatus to perform the steps of the transmission method.

The network service control apparatus according to the second aspect of the present invention can implement the methods according to the first aspect and the respective implementation manners of the first aspect, and achieve the same effects.

The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:

according to the invention, the programmable devices are respectively added on the mainboard and the BMC board, the characteristic that the programmable devices can define functions by self is memorized, the low-speed IO data is integrated in the programmable devices, and then the data content is transmitted to the BMC board through the limited PIN PINs, so that the PIN PINs of the connector and the cost are greatly saved.

Drawings

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic flow diagram of an embodiment of the method of the present invention;

FIG. 2 is a schematic diagram of the operation of a first programmable device in an embodiment of the method of the invention;

FIG. 3 is a schematic data processing flow diagram of a first programmable device in an embodiment of the method of the invention;

FIG. 4 is a schematic data processing flow diagram of a second programmable device in an embodiment of the method of the invention;

fig. 5 is a schematic structural diagram of an embodiment of the device of the present invention.

Detailed Description

In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.

The invention is composed of a main board and a BMC board which are respectively provided with a programmable device (CPLD is taken as an example for explanation below) to form a main part, wherein the characteristic that the functional module of the CPLD can define the function by self is mainly applied, pins such as SGPIO, SPI, LPC, SGPIO, JTAG, GPIO and the like on the main board are connected to the CPLD, an SPIO receiving and processing module is configured in the CPLD, the data content of the SGPIO is analyzed, a part of RAM area is marked out in the CPLD, the data is cached in the RAM area, and after the initialization of an uplink node is successful, the data content of the RAM is loaded on an uplink data bus and is transmitted to the CPLD on the BMC card. And the CPLD on the BMC card is used as a data receiving point again, the content transmitted on the data bus can be further cached at the same time, the content of the data bus can be transmitted to the BMC for data processing after the communication with the BMC is formally established, and in the same way, the data contents of the SPI, LPC, SGPIO, JTAG and GPIO on the mainboard are all cached on the CPLD at the mainboard end. And the data are respectively loaded on a high-speed data bus and transmitted to the CPLD on the BMC card. And establishing communication between the CPLD on the BMC card and the BMC to successfully send the data content to the BMC. In the same principle, the instruction content sent by the BMC is also transmitted between the CPLDs and finally transmitted to each component of the motherboard. Therefore, the problem that a low-speed bus occupies a large amount of IO is solved through communication between the CPLDs. The number of PIN legs of the connector is saved. And meanwhile, the data reliability is improved.

Specific examples are as follows.

As shown in fig. 1, an embodiment of the present invention provides a method for transmitting low-speed bus data, where the method includes the following steps:

s1, the main board side accesses the data signals to be transmitted to the BMC to the first programmable device;

s2, the first programmable device analyzes the data signal and transmits the data content to be transmitted to a second programmable device at the BMC side through a high-speed differential bus;

and S3, the second programmable device analyzes the data content, restores the data to a corresponding interface of the BMC, and completes communication with the BMC.

In an implementation manner of this embodiment, the first programmable logic device and the second programmable logic device are CPLDs.

In an implementation manner of this embodiment, the first programmable logic device and the second programmable logic device are FPGAs.

The data signals include an I2C data signal, an SPI data signal, an LPC data signal, an SGPIO data signal, a JTAG data signal, a VGA data signal, and a GPIO data signal.

Wherein I2C is information transfer bus of each sensor, Board ID, configuration information, FRU and the like on the mainboard; the SPI is used for reading and writing TPM and SPI flash data; the SGPIO is used for acquiring lighting data and state information of the backboard; LPC is used for acquiring debug and state information of PCH, CPU and the like; the GPIO is used for acquiring information such as PWM (pulse width modulation) and TACH (total internal control channel) of the fan; the VGA is used for the transfer of display data.

In step S1, the motherboard accesses the SGPIO, SPI, LPC, SGPIO, JTAG, GPIO, etc. signals to be transmitted to the BMC to the CPLD, which makes the corresponding bus to receive data content.

As shown in fig. 2 and 3, in step S2, the CPLD parses and translates the data content to be transferred from these low-speed buses, then divides a RAM in the CPLD, and temporarily stores the parsed data in the RAM. After the high-speed module establishes communication with the BMC board card, the data temporarily stored in the RAM is loaded to the high-speed differential bus and transmitted to the CPLD on the BMC card.

The specific process of analyzing the data signal by the first programmable device is as follows: acquiring the data signal through a low-speed bus IO interface; and classifying the data signals based on the logic analysis processing codes, and classifying and storing the data content into the RAM inside the device.

For example: SGPIO itself uses hard disk related commands, which require four data lines: SCLK, SLOAD, SDOUT, SDIN. The traditional application is that the four data lines are directly connected to the IO bus corresponding to the BMC. Based on the board splitting design of the existing BMC, the SGPIO needs to occupy 4 PINs of the connector to transmit data to the BMC, and occupies a large amount of space and PIN feet. In the embodiment, the SGPIO is accessed into the CPLD and is processed by the CPLD, and the SGPIO and other low-speed buses multiplex data transmission lines, so that the number of IO PIN PINs is greatly reduced, the PIN PINs of the connector can be used as other functions, and the product advantages are improved.

As shown in fig. 4, after receiving the data content of the IO bus inside the CPLD on the BMC board, the CPLD transmits and stores the high-speed data content into the temporary RAM area, and then sequentially loads and unloads the data content in the RAM area, recovers the data after parsing and translation, and transmits the data content to the BMC through the low-speed IO.

The specific process of analyzing the data content by the second programmable device is as follows: classifying data contents acquired through a high-speed differential bus; and storing the classified data content into the device.

As shown in fig. 5, an embodiment of the present invention further provides a low-speed bus data transmission device, which includes a motherboard and a BMC, and is characterized in that a first programmable device is disposed on the motherboard, and a second programmable device is disposed on the BMC board. In the figure, the first programmable device and the second programmable device are both illustrated by taking a CPLD as an example.

And the first programmable device and the second programmable device are respectively provided with a storage module for temporarily storing the data content.

The embodiment of the invention also provides a computer storage medium, wherein a computer instruction is stored in the computer storage medium, and when the computer instruction runs on the transmission device, the transmission device executes the steps of the transmission method.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims

1. A transmission method of low-speed bus data is characterized by comprising the following steps:

2. The method according to claim 1, wherein the first programmable logic device and the second programmable logic device are both CPLDs.

3. The method for transmitting low-speed bus data according to claim 1, wherein the first programmable logic device and the second programmable logic device are both FPGAs.

4. The method of claim 1, wherein the data signals include I2C data signals, SPI data signals, LPC data signals, SGPIO data signals, JTAG data signals, VGA data signals, and GPIO data signals.

5. The method for transmitting low-speed bus data according to claim 1, wherein the specific process of the first programmable device analyzing the data signal is as follows:

acquiring the data signal through a low-speed bus IO interface;

6. The method for transmitting the low-speed bus data according to claim 1, wherein the specific process of the second programmable device for analyzing the data content is as follows:

classifying data contents acquired through a high-speed differential bus;

and storing the classified data content into the device.

7. The method according to claim 1, wherein a memory module is disposed on each of the first programmable device and the second programmable device for temporarily storing the data content.

8. A transmission device of low-speed bus data comprises a mainboard and a BMC, and is characterized in that a first programmable device is arranged on the mainboard, and a second programmable device is arranged on the BMC;

9. The apparatus according to claim 8, wherein the first programmable device and the second programmable device are each provided with a storage module for temporarily storing the data content.

10. A computer storage medium having computer instructions stored thereon, which, when run on a transmission apparatus according to claim 8 or 9, cause the transmission apparatus to perform the steps of the transmission method according to any one of claims 1 to 7.