CN112306920A - Method for reducing hard disk logic controllers and server - Google Patents
Method for reducing hard disk logic controllers and server Download PDFInfo
- Publication number
- CN112306920A CN112306920A CN202011097356.3A CN202011097356A CN112306920A CN 112306920 A CN112306920 A CN 112306920A CN 202011097356 A CN202011097356 A CN 202011097356A CN 112306920 A CN112306920 A CN 112306920A
- Authority
- CN
- China
- Prior art keywords
- hard disk
- cpld
- control signal
- reducing
- backboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000011161 development Methods 0.000 abstract description 5
- 238000012356 Product development Methods 0.000 abstract 1
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/325—Display of status information by lamps or LED's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Hardware Redundancy (AREA)
Abstract
The invention discloses a method and a server for reducing hard disk logic controllers, wherein all hard disk control signals are processed by a CPLD of a mainboard, the CPLD of the mainboard outputs control signals required by each hard disk back plate in a serial mode, and a serial-in and parallel-out shift register on the hard disk back plate controls a state indicator lamp and a hot plug function of a hard disk. Through the mode, the development of CPLD hardware circuits and firmware on the hard disk backboard can be reduced, and the aim of reducing the product development cost can be fulfilled.
Description
Technical Field
The invention relates to the field of hardware design, in particular to a method for reducing hard disk logic controllers and a server.
Background
At present, in the big data era, the number of files is increased, the types and formats of novel files are continuously pushed out, the size of a single-file is continuously grown, a single server can store more data files, and the using number and the capacity of a storage device in the server are grown in multiples. The main products of the storage device comprise NVMe, SSD and HDD. In order to place the storage device in a server chassis, one or more hard disk backplanes must be designed and placed in the server chassis, a subsystem is required on the hard disk backplanes to serve as management of the hard disk backplanes, LEDs on the backplanes are controlled to display the state of the hard disk, and a common mode is to use a CPLD as a control chip for backplane management to control on and off of each LED indicator.
A basic architecture configured by a system motherboard and a storage device (NVMe) in the server, PCIe is a connection interface (interface) between a system CPU and the NVMe. PCIe signals on the motherboard pass from the CPU to the high-speed signal connector through the PCB. The back board of the storage device is connected to the HDD connector from the high-speed signal connector. PCIe signals are transmitted between the two PCB boards in a cable mode. In the present server supporting NVMe Hot plug function, the CPU provides a group of Hot plug (Hot plug) I2C Bus, and when the user executes the Hot plug operation, the Hot plug I2C Bus notifies the CPU that the CPU needs to execute the NVMe Hot plug program, thereby avoiding the unexpected hard disk plug operation from causing the system crash. In addition, the system can utilize the LED lamp number to show in the hard disk backplate with the state according to every NVMe state, and every NVMe has own exclusive LED state display lamp. NVMe has Locate, Active and Fail states, Locate represents the position of the hard disk, Active represents that the hard disk is running, and Fail represents that the hard disk has errors. The state of the NVMe in the system is displayed through the LED, so that a server user and a manager can know the state of the NVMe in real time. In the design of the hard disk backboard, a CPLD is used for communicating with the I2C Bus of the CPU hot plug, the CPLD transmits the plug state of the hard disk to the CPU, the CPU transmits the state of the system for the NVMe hard disk to the CPLD, and the CPLD converts the NVMe state into a signal for controlling the LED lamp. The server requirement and the system novelty may exist in the chassis simultaneously with a plurality of hard disk backplates, at this time, because one CPU only has a pair of Hot plug I2C Bus, the pair of Hot plug I2C Bus is connected to more than 2 hard disk backplates simultaneously, and because of respective CPLD on the hard disk backplates, if the CPU PCIe Port can not be known which hard disk backplane corresponds to, the CPLD on the backplates can not correctly display the state of the hard disk, and whether the action of Hot plug with the hard disk is done or not can not be known. The CPLDs on the two hard disk backplanes under the same CPU need to be connected with each other for communication, so as to control the LED display of the hard disk state and the hot plug state of the hard disk.
Disclosure of Invention
The invention mainly solves the technical problem of providing a hard disk backplane CPLD which can reduce the complexity of hardware circuit design on the backplane, reduce the firmware development of the hard disk backplane CPLD, and reduce the development cost of products and board card maintenance after production.
In order to solve the technical problems, the invention adopts a technical scheme that: a method for reducing hard disk logic controllers is provided, and comprises the following steps: the method comprises the following steps that firstly, a shift register in a serial-in parallel-out mode is arranged on a hard disk backboard to control hot plug of a hard disk and display an LED lamp of a hard disk state; secondly, after receiving the hard disk control signal, the CPU in the mainboard converts the hard disk control signal into a serial signal format through the CPLD and writes the hard disk control signal into the shift register in a serial mode; and thirdly, controlling the hard disk backboard to output a hard disk control signal by the shift register.
Further, in the third step, the shift register controls the hard disk backplane to output the hard disk control signal, namely, the shift register decodes the hard disk control signal first, and outputs the hard disk control signal through the hard disk backplane in a parallel manner after decoding is completed.
Further, the hard disk control signal comprises a signal for controlling a hard disk state LED lamp and a signal for controlling a hot plug function.
A server for reducing hard disk logical controllers, comprising: a main board and a hard disk back board; the mainboard is provided with a plurality of CPUs and CPLDs; the CPU is connected to the CPLD through an I2C bus; the number of the hard disk back plates is multiple; the hard disk back plate is internally provided with an integrated circuit and a plurality of hard disk connectors; each hard disk connector is connected with one hard disk; the CPU is connected to the hard disk connector through a PCIe bus; the CPLD is connected to the integrated circuit in the hard backplane through an I2C bus.
Furthermore, the integrated circuit is a shift register which is connected in series and in parallel.
Furthermore, the pin number in the integrated circuit is not less than the pin number in the CPLD.
Further, the hard disk backplane comprises an HDD hard disk backplane, an SSD hard disk backplane and an SSHD hard disk backplane.
The invention has the beneficial effects that: the invention integrates the CPLD circuits for controlling the hard disk state on one or more hard disk back plates in the server onto the CPLD of the mainboard, all hard control signals are processed by the CPLD on the mainboard, the complex CPLD signals on the hard disk back plates are replaced by the shift registers which are connected in series and in parallel, the processed signals are converted into serial signals, and then the signals are decoded by the shift registers which are connected in series and in parallel, thereby achieving the control of the hard disk LED state lamp, reducing the complexity of hardware circuit design on the back plates and the firmware development of the CPLD of the hard disk back plates, and reducing the development cost of products and the maintenance of board cards after production.
Drawings
FIG. 1 is a prior art server architecture diagram;
FIG. 2 is a flow chart of a preferred embodiment of a method for reducing hard disk logical controllers in accordance with the present invention;
FIG. 3 is a diagram of a server architecture for reducing hard disk logical controllers in accordance with the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
Referring to fig. 2 to 3, an embodiment of the present invention includes:
referring to fig. 2, a method for reducing hard disk logical controllers includes:
the method comprises the following steps that firstly, a shift register in a serial-in parallel-out mode is arranged on a hard disk backboard to control NVMe hard disk hot plug and a hard disk state display LED lamp;
secondly, after receiving the hard disk control signal, the CPU in the mainboard converts the hard disk control signal into a serial signal format through the CPLD and writes the hard disk control signal into the shift register in a serial mode;
and thirdly, decoding the shift register, and outputting the hard disk control signals in a parallel mode after decoding.
The hard disk control signal comprises a hard disk state LED lamp signal and a hot plug function control signal.
In the third step, the NVMe state display function and the hot plug function of all the backplanes are integrated into the CPLD on the motherboard for processing, so that the CPLD on the motherboard needs a lot of pins to be connected with the hard disk backplane. In order to reduce the use number of the mainboard and the hard disk backplane connector, all control signals of NVMe processed by the mainboard are output in a serial mode, and the same function can be achieved only by using two or three pins. And because all control signals are controlled by the CPLD of the mainboard, the CPLD of the mainboard can correctly distribute signals to the corresponding hard disk backboard, and the CPLD processing of the control signals on the hard disk backboard is reduced.
In the embodiment, the CPLD controller for controlling the state display and hot plug of the hard disk is moved to the system mainboard, the consumption of the CPLD is reduced, the hard disk backboard corresponding to the PCIe ports of the CPU on the mainboard can be planned in advance, and the phenomenon that the independent CPLD on the hard disk backboard needs to be added with a plurality of PCIe ports for judging which CPU is connected with the PCIe ports is avoided. And the signals to be controlled and processed on the hard disk backboard are all processed by the CPLD on the mainboard.
And the CPLD on the original hard disk backboard is replaced by the Integrated Circuit with low cost. Once the CPLD on the mainboard completes the processing of the hot plug and NVMe state display signals and then transmits the processed signals to the Integrated Circuit on the hard disk backboard, so as to reduce the design complexity and the manufacturing cost of the hard disk backboard.
Referring to fig. 3, based on the same inventive concept as the method for reducing the hard disk logic controller in the foregoing embodiment, an embodiment of the present specification further provides a server for reducing the hard disk logic controller, including: a main board and a hard disk back board; the mainboard is provided with a plurality of CPUs and CPLDs; the CPU is connected to the CPLD through an I2C bus; the number of the hard disk back plates is multiple; the hard disk back plate is internally provided with an integrated circuit and a plurality of hard disk connectors; each hard disk connector is connected with one hard disk; the CPU is connected to the hard disk connector through a PCIe bus; the CPLD is connected to the integrated circuit in the hard backboard through an I2C bus; the integrated circuit is a shift register which is connected in series and in parallel; the number of pins in the integrated circuit is not less than that of the pins in the CPLD; the hard disk backboard comprises an HDD hard disk backboard, an SSD hard disk backboard and an SSHD hard disk backboard.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A method for reducing hard disk logical controllers, comprising: the method comprises the following steps that firstly, a shift register in a serial-in parallel-out mode is arranged on a hard disk backboard to control hot plug of a hard disk and display an LED lamp of a hard disk state; secondly, after receiving the hard disk control signal, the CPU in the mainboard converts the hard disk control signal into a serial signal format through the CPLD and writes the hard disk control signal into the shift register in a serial mode; and thirdly, controlling the hard disk backboard to output a hard disk control signal by the shift register.
2. The method for reducing hard disk logic controllers according to claim 1, wherein: in the third step, the shift register controls the hard disk backboard to output the hard disk control signal, namely the shift register decodes the hard disk control signal first, and the hard disk control signal is output through the hard disk backboard in a parallel mode after decoding is finished.
3. The method for reducing hard disk logic controllers according to claim 2, wherein: the hard disk control signal comprises a hard disk state LED lamp signal and a hot plug function control signal.
4. A server for reducing hard disk logical controllers, comprising: a main board and a hard disk back board; the mainboard is provided with a plurality of CPUs and CPLDs; the CPU is connected to the CPLD through an I2C bus; the number of the hard disk back plates is multiple; the hard disk back plate is internally provided with an integrated circuit and a plurality of hard disk connectors; each hard disk connector is connected with one hard disk; the CPU is connected to the hard disk connector through a PCIe bus; the CPLD is connected to the integrated circuit in the hard backplane through an I2C bus.
5. The server for reducing hard disk logic controllers as claimed in claim 4, wherein: the integrated circuit is a shift register which is connected in series and in parallel.
6. The server for reducing hard disk logic controllers as claimed in claim 4, wherein: the number of pins in the integrated circuit is not less than that of the pins in the CPLD.
7. The server for reducing hard disk logic controllers as claimed in claim 4, wherein: the hard disk backboard comprises an HDD hard disk backboard, an SSD hard disk backboard and an SSHD hard disk backboard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011097356.3A CN112306920A (en) | 2020-10-14 | 2020-10-14 | Method for reducing hard disk logic controllers and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011097356.3A CN112306920A (en) | 2020-10-14 | 2020-10-14 | Method for reducing hard disk logic controllers and server |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112306920A true CN112306920A (en) | 2021-02-02 |
Family
ID=74326735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011097356.3A Withdrawn CN112306920A (en) | 2020-10-14 | 2020-10-14 | Method for reducing hard disk logic controllers and server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112306920A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114185721A (en) * | 2022-02-17 | 2022-03-15 | 浪潮(山东)计算机科技有限公司 | Thermal storage backup system and method for server |
-
2020
- 2020-10-14 CN CN202011097356.3A patent/CN112306920A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114185721A (en) * | 2022-02-17 | 2022-03-15 | 浪潮(山东)计算机科技有限公司 | Thermal storage backup system and method for server |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100541444C (en) | The management system of multiple main board system | |
| WO2019062218A1 (en) | Design method for implementing backplane lighting for multiple nvme hard disks | |
| CN107832199A (en) | Hard disk monitoring system based on CPLD | |
| US20080126597A1 (en) | Alternative Local Card, Central Management Module and System Management Architecture For Multi-Mainboard System | |
| US10445279B1 (en) | Automatic PCIe operating mode configuration | |
| CN110795317A (en) | Method and system for realizing lighting of self-adaptive hard disk backboard by using CPLD (complex programmable logic device) | |
| CN114579500B (en) | System, interposer and method for high-speed data communication | |
| CN109033009B (en) | Circuit board and system supporting universal and cabinet type servers | |
| CN211427338U (en) | Server mainboard based on explain majestic treaters | |
| CN102236381A (en) | Reinforced computer based on Loongson 3A processor | |
| CN111198831A (en) | NVME hard disk management system and method based on uninstalling card | |
| CN113190084B (en) | Method and device for connecting hard disk backboard supporting multiple-bit-width hard disks | |
| CN112306920A (en) | Method for reducing hard disk logic controllers and server | |
| CN212541318U (en) | Board card function test system | |
| CN108153624B (en) | Test circuit board suitable for NGFF slot | |
| CN112948316A (en) | AI edge computing all-in-one machine framework based on network interconnection | |
| CN112306938A (en) | Hot plug method and device for OCP card and multi-host card | |
| CN104460857A (en) | Peripheral component interconnect-express card and method and device for using same | |
| CN112000545A (en) | Graphics processor board card and graphics processor management method | |
| WO2023016379A1 (en) | Computer system, control method based on pcie device, and related device | |
| CN216352292U (en) | Server mainboard and server | |
| CN215599631U (en) | Double-circuit server mainboard based on Shenwei 3231 processor | |
| CN107704403B (en) | Device and method for optimizing signal transmission of main back plate | |
| CN107145213A (en) | A kind of device and method being multiplexed for PCH MEdebug and USB port | |
| CN112000189A (en) | Server mainboard based on S2500 processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20210202 |
|
| WW01 | Invention patent application withdrawn after publication |