CN117172296A - Data processing device, method, chip and electronic equipment - Google Patents
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Abstract
The application provides a data processing device, a method, a chip and electronic equipment, wherein the data processing device is used for executing machine learning calculation; the data processing apparatus includes: the data processing device comprises a processing circuit and a control circuit, wherein a first input end of the processing circuit is connected with a first output end of the processing circuit, the processing circuit comprises a decompression module, and the data processing device can improve the decompression accuracy; in addition, the data processing device can effectively save the operation amount and the storage cost of the decompression module, and improve the operation efficiency of the data processing device.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a data processing apparatus, a data processing method, a chip, and an electronic device.
Background
With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (Artificial Intelligence, AI) chips has also been increasingly demanded for high-performance digital processing devices. As one of algorithms widely used for smart chips, a neural network algorithm generally requires different arithmetic processing for a large amount of data. At present, a data processing device can compress a large amount of data and then perform operation processing, and the compressed data needs to be decompressed before the operation processing, so that normal operation processing can be performed.
However, in the existing data processing apparatus, all the compressed data is directly decompressed by one of the circuit modules, so that the decompression accuracy of the decompressed data is lower than that of the corresponding original data.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a data processing apparatus, a data processing method, a chip, and an electronic device.
The embodiment of the invention provides a data processing device which is used for executing machine learning calculation; the data processing device comprises a processing circuit and a control circuit, wherein a first input end of the processing circuit is connected with a first output end of the control circuit; the processing circuit comprises a decompression module;
the control circuit is used for analyzing the instruction of decompression processing to obtain decompression processing parameters, and inputting the decompression processing parameters to the decompression module;
the decompression module is used for performing decompression processing on the data to be decompressed input into the decompression module according to the decompression processing parameters, and obtaining data information in the decoded data; and the decompression module is also used for taking the data to be decompressed as target decompressed data when the data to be decompressed meets the condition of triggering a decompression bypass according to the data information.
In one embodiment, the decompression module is further configured to, when it is determined that the to-be-decompressed data does not meet a condition for triggering a decompression bypass according to the information in the decoded data, continue to decompress the to-be-decompressed data.
In one embodiment, the data processing apparatus further includes a storage circuit, where the storage circuit is configured to store raw data, and the control circuit is configured to obtain a calculation instruction, parse the calculation instruction to obtain a plurality of operation instructions, and input the plurality of operation instructions into the decompression module.
In one embodiment, the first output end of the storage circuit is connected to the second input end of the processing circuit, the second output end of the storage circuit is connected to the input end of the control circuit, the first input end of the storage circuit is connected to the output end of the processing circuit, and the second input end of the storage circuit is connected to the second output end of the control circuit.
In one embodiment, the decompression module respectively comprises a decompression processing unit and a selector, wherein the output end of the decompression processing unit is connected with the input end of the selector;
The decompression processing unit is used for performing decompression processing on the data to be decompressed according to the decompression processing parameters to obtain information in decoded data, judging whether the data to be decompressed meets the condition of triggering a decompression bypass according to the information of the decoded data, if not, performing subsequent decompression processing on the data to be decompressed, and determining whether to receive the data to be decompressed or the decompressed data obtained after the subsequent decompression processing is performed on the data to be decompressed by the decompression processing unit according to the received logic judgment signals, wherein the data to be decompressed is used as target decompressed data and is output.
The data processing device provided by the embodiment comprises a processing circuit and a control circuit, wherein the processing circuit comprises a decompression module, the decompression module can decompress data to be decompressed according to decompression processing parameters input by the control circuit, if the data to be decompressed meets the condition of triggering a decompression bypass, the decompression module can directly output the data to be decompressed as target decompression data, and subsequent decompression processing is not needed for the data to be decompressed, so that the decompression accuracy can be improved; in addition, the data processing device can effectively save the operation amount and the storage cost of the decompression module, so that the operation efficiency of the data processing device is improved.
The embodiment of the invention provides a data processing method, which comprises the following steps:
receiving data to be processed;
decompressing the data to be processed according to the processing parameters to obtain the information of the decoded data;
judging whether the data to be processed meets the condition of triggering a decompression bypass or not according to the information of the decoded data, wherein the condition of triggering the decompression bypass comprises a signal corresponding to a compression flag bit contained in the data to be processed, and the signal indicates that the data to be processed is not processed by adopting a specific compression algorithm;
and if yes, taking the data to be processed as target decompressed data.
In one embodiment, the processing parameters include decompression processing parameters.
In one embodiment, the decompressing the data to be processed according to the processing parameter to obtain the information of the decoded data includes: and carrying out decompression processing on the data to be processed according to the decompression processing parameters to obtain the information of the decoded data.
In one embodiment, after determining whether the to-be-processed data meets a condition for triggering a decompression bypass according to the information of the decoded data, the method further includes: and if the data to be processed does not meet the condition of triggering the decompression bypass, taking the data to be processed as target decompression data.
In one embodiment, after the step of taking the data to be processed as target decompressed data, the method further includes: and carrying out parallel operation processing on the target decompressed data through a processing circuit.
According to the data processing method provided by the embodiment, the data to be processed is received, whether the data to be processed meets the condition of triggering the decompression bypass or not is judged according to the information of the decoded data, if yes, the data to be processed is taken as target decompression data, the operation amount of decompression processing performed by the data processing device and the storage expense of the data processing device are saved, and further the data to be processed can be processed in parallel to obtain the target decompression data, so that the decompression efficiency is effectively improved; in addition, the method can directly take the data to be processed as target decompressed data, so that the decompressed data has higher accuracy than corresponding original data.
The machine learning operation device provided by the embodiment of the invention comprises one or more data processing devices; the machine learning operation device is used for acquiring data to be operated and control information from other processing devices, executing specified machine learning operation and transmitting an execution result to the other processing devices through an I/O interface;
When the machine learning arithmetic device comprises a plurality of data processing devices, the data processing devices can be linked through a specific structure and data can be transmitted;
the data processing devices are interconnected through the PCIE bus and transmit data so as to support larger-scale machine learning operation; the plurality of data processing devices share the same control system or have respective control systems; a plurality of data processing devices share a memory or have respective memories; the interconnection mode of the plurality of data processing devices is any interconnection topology.
The embodiment of the invention provides a combined processing device, which comprises the machine learning processing device, a universal interconnection interface and other processing devices; the machine learning operation device interacts with the other processing devices to jointly complete the operation appointed by the user; the combination processing device may further include a storage device connected to the machine learning operation device and the other processing device, respectively, for storing data of the machine learning operation device and the other processing device.
The neural network chip provided by the embodiment of the invention comprises the data processing device, the machine learning computing device or the combined processing device.
The embodiment of the invention provides a neural network chip packaging structure, which comprises the neural network chip.
The board provided by the embodiment of the invention comprises the neural network chip packaging structure.
The embodiment of the invention provides an electronic device which comprises the neural network chip or the board card.
The chip provided by the embodiment of the invention comprises at least one data processing device as described in any one of the above.
The electronic equipment provided by the embodiment of the invention comprises the chip.
Drawings
FIG. 1 is a schematic diagram of a data processing apparatus according to an embodiment;
FIG. 2 is a schematic diagram of a data processing apparatus according to another embodiment;
FIG. 3 is a schematic flow chart of a method for decompressing data according to an embodiment;
FIG. 4 is a block diagram of a combined processing apparatus according to an embodiment;
FIG. 5 is a block diagram of another combination processing apparatus according to one embodiment;
fig. 6 is a schematic structural diagram of a board according to an embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The data processing device provided by the application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips or other hardware circuit devices for compressing data, and the specific structure diagram is shown in FIG. 1.
Fig. 1 is a schematic structural diagram of a data processing apparatus according to an embodiment. As shown in fig. 1, the data processing apparatus is configured to perform machine learning calculation; the data processing device comprises a processing circuit 11 and a control circuit 12, wherein a first input end of the processing circuit 11 is connected with a first output end of the control circuit 12, and the processing circuit 11 comprises a decompression module 111; the control circuit 12 is configured to parse the instruction of decompression to obtain a decompression parameter, and input the decompression parameter to the decompression module 111, where the decompression module 111 is configured to decompress data to be decompressed according to the decompression parameter, and obtain information in decoded data; and the decompression module is also used for taking the data to be decompressed as target decompressed data when the data to be decompressed meets the condition of triggering a decompression bypass according to the data information.
Optionally, the decompression module 111 is further configured to, when it is determined that the to-be-decompressed data does not meet a condition for triggering a decompression bypass according to the information in the decoded data, continue to decompress the to-be-decompressed data.
Optionally, the machine learning calculation includes: and (5) operating an artificial neural network. Optionally, as shown in fig. 2, the data processing apparatus further includes a storage circuit 13, where the storage circuit 13 is configured to store original data, and the control circuit 12 is configured to obtain a calculation instruction, parse the calculation instruction to obtain a plurality of operation instructions, and input the plurality of operation instructions into the processing circuit 11.
The first output end of the storage circuit 13 is connected with the second input end of the processing circuit 11, the second output end of the storage circuit 13 is connected with the input end of the control circuit 12, the first input end of the storage circuit 13 is connected with the output end of the processing circuit 11, and the second input end of the storage circuit 13 is connected with the second output end of the control circuit 12.
Specifically, the processing circuit 11 in the data processing apparatus may perform decompression processing on the received data to be decompressed by using a decompression module 111, and may obtain information in the decoded data in the decompression process, determine whether the data to be decompressed satisfies a condition for triggering a decompression bypass according to the information, and if so, the data to be decompressed may exit the decompression processing process, and the decompression module 111 may directly output the data to be decompressed as corresponding target decompressed data; if the decompression module 111 determines, according to the information in the obtained decoded data, that the data to be decompressed does not meet the condition for triggering the decompression bypass, the decompression module 111 may continue to perform subsequent decompression processing on the data to be decompressed by adopting a specific decompression algorithm; that is, when the decompression module 111 obtains information in the decoded data, a part of the decompression processing has been performed, and when the decompression module 111 determines that the data to be decompressed does not satisfy the condition for triggering the decompression bypass based on the information in the decoded data, the decompression module 111 may perform the remaining decompression processing on the data to be decompressed. The remaining decompression process may be referred to as the subsequent decompression process referred to above. After the decompression module 111 obtains the target decompressed data, the processing circuit 11 may perform different parallel arithmetic processing on the decompressed data. Optionally, the data to be decompressed may be data in a compressed format, where the data in the compressed format may include two parts of header data and trailer data, the information included in the trailer data may be compressed specific data, and the information included in the header data may include information such as a length of the compressed data, a compression flag bit, and an address of the trailer data. Alternatively, the processing circuit 11 may include a master processing circuit and/or a slave processing circuit, and if the processing circuit includes a master processing circuit and a slave processing circuit, the slave processing circuit may include a plurality of slave processing circuits. The master processing circuit and the slave processing circuit each include a decompression module 111, and the decompression module 111 can decompress the data to be decompressed.
Alternatively, the decompression module 111 in the processing circuit 11 may receive the data to be decompressed output from the storage circuit 13, and may also receive the decompression processing parameters input from the control circuit 12. Alternatively, the decompression module 111 may decompress the data to be decompressed according to the received decompression parameters. Optionally, the decompression processing parameters may include a header data address in the data to be decompressed, a length of the decompressed data, parameters required by a decompression algorithm, and the like. Alternatively, the parameters required by the decompression algorithm may include a huffman decoding table, a run-length decoding table, a dictionary-based decoding table, a decompression algorithm, and the like. In general, the decompression module 111 may decompress the data to be decompressed by adopting a corresponding decompression algorithm according to parameters required by the decompression algorithm, so as to obtain information contained in tail data and information contained in head data in the data to be decompressed, that is, the information contained in the tail data may be compressed specific data, and the information contained in the head data may include information such as a length of compressed data, a compression flag bit, an address of the tail data, and the like. Alternatively, the data processing device may comprise a plurality of processing circuits 11, only one processing circuit 11 being shown in fig. 2. Alternatively, the control circuit 12 may receive an instruction of the decompression process, parse the instruction to obtain a decompression process parameter, and input the decompression process parameter to the decompression module 111. Optionally, the compression flag bit included in the header data of the data to be decompressed may represent whether the data to be decompressed is obtained by processing through a specific compression algorithm or not, and meanwhile, the compression flag bit may include two signals, which are respectively represented by 0 and 1, where 0 may represent the data to be decompressed obtained after processing by using a specific compression algorithm, and 1 may represent the data to be decompressed which is directly obtained without performing a specific compression process.
In addition, if the to-be-decompressed data is judged to meet the condition for triggering the decompression bypass according to the information in the decoded data, the decompression module 111 can directly output the to-be-decompressed data as target decompressed data without adopting any decompression algorithm, and meanwhile, if the to-be-decompressed data is judged not to meet the condition for triggering the decompression bypass according to the information in the decoded data, the decompression module 111 needs to continue adopting a specific decompression algorithm to perform subsequent decompression processing on the to-be-decompressed data. Optionally, the condition for triggering the decompression bypass may be a compression flag bit signal included in header data of the data to be decompressed, where the corresponding representation of the data to be decompressed is obtained without specific compression processing.
It should be noted that, according to the decompression parameters input by the control circuit 12, the decompression module 111 in the processing circuit 11 may perform decompression processing on the data to be decompressed by using a specific decompression algorithm, so as to obtain corresponding target decompressed data. Alternatively, the decompression module 111 may perform parallel processing on the data to be decompressed. Alternatively, each piece of data to be decompressed may obtain one piece of target decompressed data. Alternatively, the target decompressed data may be block data before the data to be decompressed is not compressed. Optionally, the compression flag bit may indicate whether the target decompressed data is obtained by processing the complete decompression algorithm, or not performing specific compression processing to directly obtain the target decompressed data, or it may be understood that the compression flag bit may include two signals, which are respectively represented by a low-level signal 0 and a high-level signal 1, where 0 may indicate that the data to be decompressed is obtained by processing the complete decompression algorithm, and 1 may indicate that the data to be decompressed is directly obtained without performing specific compression processing. Optionally, the distribution type of the tail data in the data to be decompressed may be one-dimensional compact, two-dimensional compact, three-dimensional compact, or any other compact dimension.
For example, if the tail data in the data to be decompressed contains a plurality of data, one data is continuously connected with the next data, and so on, the plurality of data are continuously distributed, and the distribution form can be called one-dimensional compact form; if the multiple data distribution forms are matrix distribution forms with fixed bit width, namely, the multiple data distribution forms can be 8-bit wide, if the first data are 6-bit wide data '010100', the second compressed format data can be 6-bit wide data '101101', the high 2-bit numerical value '10' of the second compressed format data can be continuously connected with the first data, namely, the 8 numerical values of '01010010' are positioned in the same row, the low 4-bit numerical value '1101' of the second data can be distributed in the second row, then the third data are connected, and then the like, the number of numerical values stored in each row is fixed, redundant numerical values can be distributed in the next row, and the distribution forms can be called two-dimensional compact type; if the plurality of data distribution forms can be a plurality of matrix distribution forms with fixed sizes, namely a plurality of matrix distribution forms with 8 bits and 8 bits respectively, if the first data is 6 bits wide data "101101", the second compressed format data can be 6 bits wide data "101101", then the upper 2 bit value "10" of the second compressed format data can be continuously connected with the first data, namely the 8 values of "01010010" are located in the same row, the lower 4 bit value "1101" of the second data can be distributed in the second row, then the third data is connected, and then the number of bits stored in each row can be fixed, the redundant number can be distributed in the next row, after the first fixed size matrix frame is distributed, the data can be continuously distributed in the second fixed size matrix frame, and then the like until all the data are distributed completely, and the distribution form can be called three-dimensional compact.
Alternatively, if the processing circuit 11 includes a master processing circuit and a slave processing circuit, the decompression module 111 in the master processing circuit may input the target decompressed data to the slave processing circuit, and may return the target decompressed data to the storage circuit 13 to write into the external storage for waiting for subsequent reading by performing subsequent different parallel arithmetic processing on the target decompressed data by the slave processing circuit. Alternatively, if the processing circuit 11 includes only a plurality of slave processing circuits, the decompression module 111 in each slave processing circuit may perform subsequent operation processing on the target decompressed data.
With continued reference to fig. 2, the data processing apparatus may further include a direct memory access unit. Optionally, the storage circuit 13 in the data processing apparatus may include: registers, caches. The cache may store input data, the register may store tag data in the input data, and the cache may include a scratch pad cache. Alternatively, the control circuit 12 may include: the instruction buffer unit 121, the instruction processing unit 122, and the storage queue unit 123, where the instruction buffer unit 121 may store a calculation instruction associated with an artificial neural network operation, the instruction processing unit 122 may parse the calculation instruction to obtain a plurality of operation instructions, the storage queue unit 123 may store an instruction queue, and the instruction queue may include: a plurality of arithmetic instructions or calculation instructions to be executed in the order of the queue.
Optionally, the control circuit 12 may further include a dependency processing unit 124, where the dependency processing unit 124 is configured to determine whether a first operation instruction has an association relationship with a zeroth operation instruction before the first operation instruction when the first operation instruction has a plurality of operation instructions, and if the first operation instruction has an association relationship with the zeroth operation instruction, cache the first operation instruction in the instruction storage unit, and extract the first operation instruction from the instruction storage unit and transmit the first operation instruction to the operation unit after the execution of the zeroth operation instruction is completed.
The determining whether the association relationship exists between the first operation instruction and the zeroth operation instruction before the first operation instruction includes: extracting a first storage address interval of required data (for example, a matrix) in the first operation instruction according to the first operation instruction, extracting a zeroth storage address interval of the required matrix in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have overlapping areas, determining that the first operation instruction and the zeroth operation instruction have an association relationship, if the first storage address interval and the zeroth storage address interval do not have overlapping areas, and determining that the first operation instruction and the zeroth operation instruction do not have an association relationship.
The data processing device provided by the embodiment comprises a processing circuit and a control circuit, wherein the processing circuit is provided with a decompression module, the decompression module can decompress data to be decompressed according to decompression processing parameters input by the control circuit, and if the data to be decompressed meets the condition of triggering a decompression bypass, the decompression module can directly output the data to be decompressed as target decompression data without carrying out subsequent decompression processing on the data to be decompressed, so that the decompression accuracy can be improved; in addition, the data processing device can effectively save the operation amount and the storage cost of the decompression module, so that the operation efficiency of the data processing device is improved.
Fig. 2 is a schematic diagram of a specific structure of a processing circuit in a data processing apparatus according to another embodiment, where the decompression module 111 in the processing circuit includes a decompression processing unit 1111 and a selector 1112, and an output end of the decompression processing unit 1111 is connected to an input end of the selector 1112. The decompression processing unit 1111 is configured to perform decompression processing on data to be decompressed according to the decompression processing parameters to obtain information in decoded data, determine whether the data to be decompressed meets a condition for triggering a decompression bypass according to the information of the decoded data, if not, perform subsequent decompression processing on the data to be decompressed, and the selector 1112 is configured to determine, according to the received logic determination signal, whether to receive the data to be decompressed, or whether the decompression processing unit 1111 performs subsequent decompression processing on the data to be decompressed to obtain decompressed data as target decompressed data, and output the decompressed data.
Specifically, when the decompression module 111 performs decompression processing on data to be decompressed, the data to be decompressed may be input to the decompression processing unit 1111 by default to perform decompression processing, after a part of the decompression processing is performed, information in the decoded data may be obtained, the decompression processing unit 1111 may determine whether the data to be decompressed meets a condition for triggering a decompression bypass according to the information, a logic determination signal may be input to the selector 1112 according to the determination result, the selector 1112 may determine according to the received logic determination signal, the decompression module 111 may receive the data to be decompressed as target decompression data, or the decompression processing unit 1111 may continue to use a specific decompression algorithm to obtain a decompression result after performing subsequent decompression processing on the data to be decompressed, and receive the decompression result output by the decompression processing unit 1111 as target decompression data output. Alternatively, the logic determination signal may include two types, which respectively indicate that the condition for triggering the decompression bypass is satisfied and that the condition for triggering the decompression bypass is not satisfied. If the signal received by the selector 1112 indicates that the condition for triggering the decompression bypass is satisfied, the selector 1112 may directly receive the data to be decompressed and output the data as target decompressed data; if the signal received by the selector 1112 indicates that the condition for triggering the decompression bypass is not satisfied, the selector 1112 may receive the decompression processing unit 1111 and continue to use a specific decompression algorithm to perform subsequent decompression processing on the data to be decompressed to obtain a decompression result, and output the decompression result as the target decompressed data. Alternatively, the decompression algorithm may include huffman decoding, run-length decoding, dictionary-based decoding algorithm, and the like. Alternatively, the second decompression module 111 may perform parallel decoding processing on a plurality of data to be decompressed. Alternatively, the above decoding process may also be referred to as decompression process. Alternatively, the selector 1112 may be a two-way selector.
Taking the huffman decoding algorithm as an example, the decompression algorithm may be described, if the decompression processing unit 1111 in the decompression module 111 performs decompression processing on a piece of data to be decompressed by using the huffman decoding algorithm, and the decompression module 111 may learn that the specific decompression algorithm is the huffman decoding algorithm according to the received decompression processing parameters. If the decompression processing unit 1111 performs decompression processing on only one data to be decompressed at this time, according to the huffman decoding table in the decompression processing parameter and the start address of the tail data in the actually known data to be decompressed, the decompression processing unit 1111 may search the tail data of the data to be decompressed for the decompressed data, and before performing the search processing, the decompression processing unit 1111 may further obtain information included in the header data of the data to be decompressed, that is, the compressed flag bit signal corresponding to the tail data in the data to be decompressed, where the decompressed data may be the block data obtained before performing the compression processing on the original data. Optionally, if the compression flag bit signal received by the decompression processing unit 1111 may indicate that the data to be decompressed is directly obtained without performing compression processing, the data to be decompressed may not continue to perform subsequent search processing (i.e. subsequent decompression processing), and exit the decompression processing process, where the decompression module 111 may directly receive the data to be decompressed through the selector 1112, and output the data as target decompressed data; if the compression flag bit signal received by the decompression processing unit 1111 can characterize that the data to be decompressed is obtained by performing compression processing through a specific compression algorithm, the data to be decompressed can continue to perform subsequent searching processing (i.e. subsequent decompression processing), at this time, the decompression processing unit 1111 can input the decompression result received by the subsequent decompression processing into the selector 1112, and the selector 1112 uses the decompression result as target decompressed data and outputs the target decompressed data.
According to the data processing device, if the decompression bypass unit and the decompression processing unit are included in the decompression module, the data to be decompressed, which meets the trigger decompression bypass condition, can be directly output as decompressed data through the decompression bypass unit, at the moment, decompression processing of the data to be decompressed is not needed, the calculation amount and the storage cost of the decompression module are further saved, the calculation amount and the storage cost of the data processing device are further saved, the decompression module can decompress a plurality of data to be decompressed in a parallel mode, and the decompression efficiency is effectively improved; in addition, the data processing device can directly take the data to be decompressed as the decompressed data, so that the decompressed data has higher accuracy compared with the corresponding original data.
Fig. 3 is a flow chart of a data processing method according to an embodiment, where the method may be processed by the data processing apparatus shown in fig. 1, and the embodiment relates to a process of decompressing data. As shown in fig. 3, the method includes:
s101, receiving data to be processed.
Specifically, the processing circuit in the data processing device can receive the data to be processed input by the storage circuit through the decompression module. Wherein the data format to be processed may be consistent with the compressed data format.
S102, decompressing the data to be processed according to the processing parameters to obtain the information of the decoded data.
Alternatively, the processing parameters may include decompression processing parameters.
Optionally, the decompressing processing is performed on the data to be processed according to the processing parameter to obtain the information of the decoded data, including: and carrying out decompression processing on the data to be processed according to the decompression processing parameters to obtain the information of the decoded data.
Specifically, the decompression processing parameters may include a header data address of the compressed format data, a length of the decompressed data, parameters required by a decompression algorithm, and the like. Alternatively, the decompression processing parameters may be obtained by parsing the decompression module by the receiving control circuit, or may be stored in advance in the decompression module. Optionally, the decompression module in the data processing device may decompress the data to be decompressed according to the received decompression parameters to obtain the information of the decoded data. In this embodiment, the decompression module may perform a part of the decompression process on the data to be decompressed according to a specific compression algorithm, so as to obtain the information of the decoded data. Alternatively, the information of the decoded data may be equal to the information contained in the header data in the data to be decompressed, that is, the compressed flag bit signal.
S103, judging whether the data to be processed meets the condition of triggering a decompression bypass or not according to the information of the decoded data, wherein the condition of triggering the decompression bypass comprises a signal corresponding to a compression flag bit contained in the data to be processed, and the signal indicates that the data to be processed is not processed by adopting a specific compression algorithm.
Specifically, the condition for triggering the decompression bypass may be a signal corresponding to a compression flag bit included in header data of the data to be decompressed, which indicates that the data to be decompressed is obtained without specific compression processing.
And S104, if the data to be processed is satisfied, taking the data to be processed as target decompressed data.
Specifically, if the data to be processed meets the condition of triggering the decompression bypass, the decompression module may directly output the data to be processed as target decompressed data. Optionally, the decompression module may perform parallel decoding processing on the multiple data to be processed to obtain multiple target decompressed data.
According to the data processing method provided by the embodiment, the data to be processed is received, whether the data to be processed meets the condition of triggering the decompression bypass or not is judged according to the information of the decoded data, if yes, the data to be processed is taken as target decompression data, the operation amount of decompression processing performed by the data processing device and the storage expense of the data processing device are saved, and further the data to be processed can be processed in parallel to obtain the target decompression data, so that the decompression efficiency is effectively improved; in addition, the method can directly take the data to be processed as target decompressed data, so that the decompressed data has higher accuracy than corresponding original data.
In one embodiment, the step S103 further includes, after determining whether the to-be-processed data satisfies a condition for triggering a decompression bypass according to the information of the decoded data: and if the data to be processed does not meet the condition of triggering the decompression bypass, taking the data to be processed as target decompression data.
Optionally, after the step of taking the data to be processed as target decompressed data, the method further includes: and carrying out parallel operation processing on the target decompressed data through a processing circuit.
Specifically, if the data to be processed does not meet the condition of triggering the decompression bypass, the decompression module can continue to perform subsequent decompression processing on the data to be processed by adopting a specific decompression algorithm through the decompression processing unit to obtain a decompression result, and the decompression result is used as target decompression data. Alternatively, the decompression processing parameters may include a specific decompression algorithm for decompressing the data to be processed, where the decompression algorithm may be huffman decoding, run-length decoding, dictionary-based decoding algorithm, and the like. Optionally, the decompression processing parameter may be a decompression processing parameter obtained by the decompression module receiving an instruction of the control circuit for resolving the decompression operation, or may be a decompression processing parameter stored in advance by the decompression module. Alternatively, the above-mentioned operation processing may include a vector accumulation operation, a vector inner product operation, a vector comparison operation, a matrix transposition process, and the like.
It should be noted that, the decompression module in the processing circuit may decompress the data to be decompressed according to the decompression processing parameters to obtain the decoded data information, if the data to be processed meets the condition of triggering the decompression bypass according to the decoded data information, the decompression module may directly use the data to be decompressed as the target decompression data, otherwise, the decompression module needs to perform subsequent decompression processing on the data to be decompressed to obtain the decompressed data, the decompressed data is used as the target decompression data, the processing circuit may perform different operation processing on the target decompression data to obtain the operation result, and the processing circuit may perform some subsequent operation processing on the operation result and return the result of the subsequent operation processing to the block compression circuit, and finally the block compression circuit may perform the block processing and the compression processing on the result of the subsequent operation processing and then send the compressed result to the storage circuit, and the storage circuit may further perform the operation processing of the next stage on the compressed result. Alternatively, the processing circuit may decompress and multiply the target compressed data, and the subsequent processing may include decompression, multiplication, and the like.
In addition, the decompression module in the processing circuit can decompress the data to be decompressed according to the decompression processing parameters to obtain target decompressed data, the processing circuit can perform different types of operation processing on the target decompressed data to obtain operation results, the processing circuit can return the different types of operation results to the storage circuit, and the storage circuit can further perform the next stage of operation processing on the target decompressed data. Alternatively, the processing circuit may perform the accumulation and activation operation on the target decompressed data, and the different types of operation results may include the accumulation and activation operation.
According to the data processing method provided by the embodiment, if the data to be processed does not meet the condition of triggering the decompression bypass, the decompression algorithm is continuously adopted to perform subsequent decompression processing on the data to be processed to obtain target decompressed data, otherwise, the data to be processed can be directly output as the target decompressed data, and at the moment, the subsequent decompression processing is not required to be continuously performed on the data to be decompressed, so that the operand of the decompression processing and the storage expense of a data processing device can be saved.
The embodiment of the application also provides a machine learning operation device which comprises one or more data processing devices, wherein the data processing devices are used for acquiring data to be operated and control information from other processing devices, executing specified machine learning operation and transmitting an execution result to peripheral equipment through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one data processing device is included, the data processing devices may be linked and data transferred by a specific structure, such as by interconnecting and transferring data via a fast external device interconnect bus, to support larger scale machine learning operations. At this time, the same control system may be shared, or independent control systems may be provided; the memory may be shared, or each accelerator may have its own memory. In addition, the interconnection mode can be any interconnection topology.
The machine learning arithmetic device has high compatibility and can be connected with various types of servers through a quick external equipment interconnection interface.
The embodiment of the application also provides a combined processing device which comprises the machine learning operation device, a general interconnection interface and other processing devices. The machine learning operation device interacts with other processing devices to jointly complete the operation designated by the user. Fig. 4 is a schematic diagram of a combination processing apparatus.
Other processing means include one or more processor types of general-purpose/special-purpose processors such as Central Processing Units (CPU), graphics Processing Units (GPU), neural network processors, etc. The number of processors included in the other processing means is not limited. Other processing devices are used as interfaces between the machine learning operation device and external data and control, including data carrying, and complete basic control such as starting, stopping and the like of the machine learning operation device; other processing devices may cooperate with the machine learning computing device to perform the computing task.
And the universal interconnection interface is used for transmitting data and control instructions between the machine learning operation device and other processing devices. The machine learning operation device acquires required input data from other processing devices and writes the required input data into a storage device on a machine learning operation device chip; the control instruction can be obtained from other processing devices and written into a control cache on a machine learning operation device chip; the data in the memory module of the machine learning arithmetic device may be read and transmitted to other processing devices.
Optionally, as shown in fig. 5, the structure may further include a storage device, where the storage device is connected to the machine learning operation device and the other processing device, respectively. The storage device is used for storing data in the machine learning arithmetic device and the other processing devices, and is particularly suitable for data which cannot be stored in the machine learning arithmetic device or the other processing devices in the internal storage of the machine learning arithmetic device or the other processing devices.
The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle, video monitoring equipment and the like, so that the core area of a control part is effectively reduced, the processing speed is improved, and the overall power consumption is reduced. In this case, the universal interconnect interface of the combined processing apparatus is connected to some parts of the device. Some components such as cameras, displays, mice, keyboards, network cards, wifi interfaces.
In some embodiments, a chip is also disclosed, which includes the machine learning computing device or the combination processing device.
In some embodiments, a chip package structure is disclosed, which includes the chip.
In some embodiments, a board card is provided that includes the chip package structure described above. As shown in fig. 6, fig. 6 provides a board that may include other mating components in addition to the chips 389, including but not limited to: a storage device 390, a receiving device 391 and a control device 392;
The memory device 390 is connected to the chip in the chip package structure through a bus for storing data. The memory device may include multiple sets of memory cells 393. Each group of storage units is connected with the chip through a bus. It is understood that each set of memory cells may be DDR SDRAM (English: double Data Rate SDRAM, double Rate synchronous dynamic random Access memory).
DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include 4 sets of the memory cells. Each set of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers inside, where 64 bits of the 72-bit DDR4 controllers are used to transfer data and 8 bits are used for ECC verification. It is understood that the theoretical bandwidth of data transfer can reach 25600MB/s when DDR4-3200 granules are employed in each set of memory cells.
In one embodiment, each set of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each storage unit.
The receiving device is electrically connected with the chip in the chip packaging structure. The receiving means is used for realizing data transmission between the chip and an external device (such as a server or a computer). For example, in one embodiment, the receiving means may be a standard fast external device interconnect interface. For example, the data to be processed is transferred from the server to the chip through a standard rapid external device interconnection interface, so as to realize data transfer. Preferably, the theoretical bandwidth can reach 16000MB/s when using a fast peripheral interconnect 3.0X10 interface transport. In another embodiment, the receiving device may be another interface, and the present application is not limited to the specific form of the other interface, and the interface unit may be capable of implementing a switching function. In addition, the calculation result of the chip is still transmitted back to the external device (e.g., server) by the receiving apparatus.
The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may comprise a single chip microcomputer (Micro Controller Unit, MCU). The chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, and may drive a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light-load. The control device can realize the regulation and control of the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the chip.
In some embodiments, an electronic device is provided that includes the above board card.
The electronic device may be a data processor, a robot, a computer, a printer, a scanner, a tablet, an intelligent terminal, a cell phone, a vehicle recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.
The vehicle comprises an aircraft, a ship and/or a vehicle; the household appliances comprise televisions, air conditioners, microwave ovens, refrigerators, electric cookers, humidifiers, washing machines, electric lamps, gas cookers and range hoods; the medical device includes a nuclear magnetic resonance apparatus, a B-mode ultrasonic apparatus, and/or an electrocardiograph apparatus.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of circuit combinations, but those skilled in the art should appreciate that the present application is not limited by the described circuit combinations, as some circuits may be implemented in other manners or structures according to the present application. Further, it should be understood by those skilled in the art that the embodiments described in the specification are all alternative embodiments, and the devices and modules involved are not necessarily required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (17)
1. A data processing apparatus for performing machine learning calculations; the data processing device comprises a processing circuit and a control circuit, wherein a first input end of the processing circuit is connected with a first output end of the control circuit; the processing circuit comprises a decompression module;
the control circuit is used for analyzing the instruction of decompression processing to obtain decompression processing parameters, and inputting the decompression processing parameters to the decompression module; the decompression processing parameters comprise a header data address in the data to be decompressed, the length of the decompressed data and parameters required by a decompression algorithm;
The decompression module is used for performing decompression processing on the data to be decompressed input into the decompression module according to the decompression processing parameters, and obtaining data information in the decoded data; and the decompression module is also used for taking the data to be decompressed as target decompressed data when the data to be decompressed meets the condition of triggering a decompression bypass according to the data information.
2. The data processing apparatus according to claim 1, wherein the decompression module is further configured to continue to decompress the data to be decompressed when it is determined that the data to be decompressed does not satisfy a condition for triggering a decompression bypass according to the information in the decoded data.
3. The data processing apparatus according to claims 1-2, further comprising a storage circuit for storing raw data, wherein the control circuit is configured to obtain a calculation instruction, parse the calculation instruction to obtain a plurality of calculation instructions, and input the plurality of calculation instructions into the decompression module.
4. A data processing device as claimed in claim 3, characterized in that the first output of the memory circuit is connected to the second input of the processing circuit, the second output of the memory circuit is connected to the input of the control circuit, the first input of the memory circuit is connected to the output of the processing circuit, and the second input of the memory circuit is connected to the second output of the control circuit.
5. The data processing apparatus according to claim 1, wherein the decompression module includes a decompression processing unit and a selector, respectively, an output terminal of the decompression processing unit being connected to an input terminal of the selector;
the decompression processing unit is used for performing decompression processing on the data to be decompressed according to the decompression processing parameters to obtain information in decoded data, judging whether the data to be decompressed meets the condition of triggering a decompression bypass according to the information of the decoded data, if not, performing subsequent decompression processing on the data to be decompressed, and determining whether to receive the data to be decompressed or the decompressed data obtained after the subsequent decompression processing is performed on the data to be decompressed by the decompression processing unit according to the received logic judgment signals, wherein the data to be decompressed is used as target decompressed data and is output.
6. A method of data processing, the method comprising:
receiving data to be processed;
decompressing the data to be processed according to the processing parameters to obtain the information of the decoded data;
judging whether the data to be processed meets the condition of triggering a decompression bypass or not according to the information of the decoded data, wherein the condition of triggering the decompression bypass comprises a signal corresponding to a compression flag bit contained in the data to be processed, and the signal indicates that the data to be processed is not processed by adopting a specific compression algorithm;
And if yes, taking the data to be processed as target decompressed data.
7. The method of claim 6, wherein the processing parameters comprise decompression processing parameters.
8. The method according to claim 7, wherein the decompressing the data to be processed according to the processing parameters to obtain the information of the decoded data comprises: and carrying out decompression processing on the data to be processed according to the decompression processing parameters to obtain the information of the decoded data.
9. The method according to claim 6, wherein after determining whether the data to be processed satisfies a condition for triggering a decompression bypass based on the information of the decoded data, further comprising: and if the data to be processed does not meet the condition of triggering the decompression bypass, taking the data to be processed as target decompression data.
10. The method of claim 9, further comprising, after the step of taking the data to be processed as target decompressed data: and carrying out parallel operation processing on the target decompressed data through a processing circuit.
11. A machine learning computing device, characterized in that the machine learning computing device comprises one or more data processing devices according to any one of claims 1-5, and is configured to obtain input data and control information to be computed from other processing devices, execute specified machine learning computation, and transmit execution results to other processing devices through I/O interfaces;
When the machine learning computing device comprises a plurality of data processing devices, the plurality of computing devices can be connected through a specific structure and transmit data;
the data processing devices are interconnected through the PCIE bus and transmit data so as to support larger-scale machine learning operation; the plurality of data processing devices share the same control system or have respective control systems; a plurality of data processing devices share a memory or have respective memories; the interconnection mode of the plurality of data processing devices is any interconnection topology.
12. A combination processing device, comprising the machine learning computing device of claim 11, a universal interconnect interface, and other processing devices;
the machine learning operation device interacts with the other processing devices to jointly complete the calculation operation designated by the user.
13. The combination processing device of claim 12, further comprising: and a storage device connected to the machine learning operation device and the other processing device, respectively, for storing data of the machine learning operation device and the other processing device.
14. A neural network chip, characterized in that the machine learning chip includes the machine learning arithmetic device according to claim 11 or the combination processing device according to claim 12.
15. An electronic device comprising the chip of claim 14.
16. A board, characterized in that, the board includes: a memory device, a receiving means and a control device, and a neural network chip as claimed in claim 14;
the neural network chip is respectively connected with the storage device, the control device and the receiving device;
the storage device is used for storing data;
the receiving device is used for realizing data transmission between the chip and external equipment;
the control device is used for monitoring the state of the chip.
17. The board card of claim 16, wherein the board card comprises,
the memory device includes: each group of storage units is connected with the chip through a bus, and the storage units are as follows: DDR SDRAM;
the chip comprises: the DDR controller is used for controlling data transmission and data storage of each storage unit;
The receiving device is as follows: standard PCIE interfaces.
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