JPH01102647A - Load control system for test program - Google Patents

Abstract

PURPOSE:To increase the loading speed of a test program and also the overall test processing speed by transferring and loading a test program used in common to plural devices to be tested into a memory. CONSTITUTION:A test program which is used in common to plural devices to be tested is loaded into a memory 11 from a test program storing means 22 for a first device to be tested. Thus, the test programs of other devices to be tested are loaded when the test program loaded in the memory 11 is transferred over the memory 11. The data are transferred at high speed via the same memory 11 compared with a case the data are loaded from the exter nal means 22. Thus, it is possible to increase the loading speed of the test program as well as the overall test processing speed.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a test program load control method for loading a program for testing a plurality of input/output devices under an information processing device into the device's internal memory, by speeding up the test program loading process and improving overall performance. In a test program load control method in which a test program is loaded into memory within an information processing device from a means for storing test programs for multiple devices under test, the test program loaded into memory is When loading a test program for the device under test into the memory, refer to the management information in the table and check whether the test program that can be used for the device under test is loaded into the memory. In this case, the test program is configured to speed up the loading process by providing means for transferring the test program to the test program storage area of the device under test on the memory.

[Industrial application field]

The present invention relates to a test program load control method for loading a program for testing a plurality of input/output devices under an information processing device into a memory within an information processing system.

[Conventional technology]

In an information processing system in which multiple input/output devices such as terminals and devices are connected to a single information processing device, the At the specified date and time, the information processing device tests the normality of each input/output device.

Each input/output device is tested by loading a test program into the memory within the information processing device from an external test program storage means. In this case, a common test program is used for the same type of input/output device, and there are two types of test program load control methods: serial type and parallel type.

The serial type test program load control method loads a set of common test programs for each input/output device with the same specifications into the memory of the information processing device, and uses that test program to serially load each input/output device under test. This is a sequential testing method.

This serial test program load control method requires only a small number of test programs to be loaded into the memory of the information processing device, but since each input/output device is tested serially and sequentially, all input/output devices can be tested. This has the disadvantage that it takes a long time to complete.

The parallel test program load control method improves the above-mentioned drawbacks of the serial test program load control method and enables efficient test processing.

Next, a parallel test program load control method will be described with reference to FIG. FIG. 6 is an explanatory diagram of the principle of a parallel test program load control method.

In FIG. 6, reference numeral 30 denotes an information processing device, which includes a memory 31 and a test execution control section 32.

The memory 31 stores test programs TP, 'rpb, etc. The test execution control unit 32 uses the memo IJ32
The storage and execution of each test program TP, 'rpb, etc. are controlled.

41 and 411 are devices to be tested, which are input/output devices such as terminals and devices.

42 is a test program storage means;
Test program TP,,'rp, for L~417
etc. are stored. In the case of a test program common to a plurality of devices under test, only one set of common test programs is stored. In the case of FIG. 6, the test program TP,
is the device under test 41. ．． Common to 41□ and 41.1. TPb is a test program for the device under test 413.

In this configuration, the device under test 41. When testing the devices under test 411 to 4111, the test execution control unit 32 uses the test program storage unit 42 to test the devices under test 411 to 41. Take out the test program for each device under test 41
．． ~41. is loaded into the memory 31 in correspondence with the above. Device under test 41. .

Test program TP for 41g and 417.

are common, but all of them are connected to the device under test 41. as shown in the figure. ．． 41□ and 41. Corresponding to memory 3
1.

Each device under test 41. is stored in the memory 31. ~41. When the loading of the test programs for the test program is completed, the test execution control unit 32 causes the n test programs TP, TPb, etc. in the memory 31 to be executed in parallel by multi-programming processing.

As a result, the device under test 41. Since the tests for 417 are performed in parallel, the tests can be executed at a higher speed than in the serial test program load control method described above.

[Problem that the invention seeks to solve]

As mentioned above, the parallel test program load control method loads test programs for each device under test into the information processing memory and processes them in parallel to execute tests on the device under test at high speed. was completed. However, on the other hand, even if the test program is common to multiple devices under test, it is necessary to load the test program for each device under test each time.
Since it is necessary to load n test programs corresponding to the number of test programs, there is an inconvenience that loading takes a long time. In particular, when the number of devices under test increases, the time required to load the test program into the memory, which occupies the test program execution time, cannot be ignored, which is disadvantageous in that speeding up of the test process is hindered.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved parallel test program load control method that speeds up the loading process of common test programs and improves the overall test processing speed.

[Means for solving problems]

The solution adopted by the present invention will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, reference numeral 10 denotes an information processing device, which includes a memory 11, a memory management table 12, and a test execution control section 13 inside.

21 and 217 are devices to be tested, which are input/output devices such as devices and terminals.

Reference numeral 22 denotes a test program storage means, which stores the device under test 21
．． -21, test programs are stored.

The memory 11 stores the device under test 21. The test program for ~211° is loaded. Management information regarding test programs loaded into the memory 11 is registered in the memory management table 12.

The test execution control unit 13 stores the device under test f in the memory 11.
When loading a test program to the device under test 21i, refer to the management information in the memory management table 12 and load the test program to the device under test 2.
When a usable test program is loaded in the memory 11, the test program loaded in the memory 11 is transferred to the test program storage area of the device under test 21i.

[For production]

The test program storage means 22 stores in advance the device under test W21. ~21. ．． In the memory management table 12, management information regarding the test programs already loaded into the memory 11 is registered by the test execution control unit 13.

When loading a test program for a new device under test 21i (nai≧1) into the memory 11, the test execution control unit 13 first refers to the management information in the memory management table 12 and determines which programs can be used for the device under test 21i. Check whether the test program is loaded into memory 11.

When a test program usable for the device under test 21i has already been loaded into the memory 11, the test program stored in the memory 11 is transferred to the test program area of the device under test 21i without loading it from the test program storage means 22. .

Equipment under test! When the test program usable for 21i is not loaded into the memory 11, the test program is loaded from the test program storage means 22, and the management information regarding the test program of the device under test 21i loaded into the memory 11 is registered in the memory management table 12. .

゛ By doing the above, a test program that can be commonly used for multiple devices under test can be loaded onto the memory 11 from the test program storage means 22 for the first device under test, and then it can be used for other devices under test. The test program can be loaded by transferring the test program loaded into the memory 11 onto the memory 11.

Since data transfer on the memory 11 is processed at a higher speed than when loading from the external test program storage means 22, the loading process can be speeded up and the overall test process can be sped up.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 2 to 5. FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention, FIG. 3 is an explanatory diagram of a memory management table of the embodiment, and FIG. 4 is an explanation of the contents of loading request program information of the embodiment. FIG. 5 is a processing flowchart of the same embodiment.

(A) Configuration of Embodiment In FIG. 2, the information processing device 10, memory 11, memory management table 12, test execution control unit 13, devices under test 211 to 217, and test program storage means 22 are as shown in FIG. As explained. Reference numeral 14 denotes a bus that connects each section and each device and transfers data and control signals.

In the memory 11, 1111 to 1111. is a test program storage area in which test programs for the devices under test 211 to 21,1 are stored.

In this example, the device under test 211.

21□ and 21. It is assumed that the test program TP is commonly used for the test device 213, and the test program T P b is used for the device under test 213.

The test program storage means 22 is an input/output device composed of a magnetic disk, a magnetic tape, etc., and stores test programs TP, 'rpb, etc.

FIG. 3 shows the structure of the memory management table 12. As management information of the test program loaded into the memory 11, the program name, the location address of the test program on the memory 11, and the program size are registered.

FIG. 4 shows the load request program information, in which the program name and location address are specified.

When the load request program information and the program name indicated by the memory management table 12 match, it is detected that the desired test program has already been loaded into the memory 11.

(B) Operation of the Embodiment The operation of the embodiment shown in FIG. 2 will be explained according to its steps with reference to the processing flowchart shown in FIG. 5.

■ Step S+, Sz The test execution control unit 13 executes the program, and when there is a load request, refers to the memory management table 12 and uses the management information and the program name in the load request program information (see Figure 4). Compare (step S,).

When the two match, it is determined that the test program requested to be loaded has already been loaded into the memory 11, and when they do not match, it is determined that it has not been loaded (
step SZ).

■ Step S.

When it is determined in step St that the load has been completed,
The test execution control unit 13 extracts the location address and program size from the memory management table 13 and checks for errors such as address exceptions (if an address exception is detected, a program interrupt occurs and processing is interrupted). ).

(2) Step S4 If the location address is valid in step Sol, the test execution control unit 13 reads the test program loaded in the memo I 711 and transfers it to the location address indicated by the load request program information.

As a result, the test program T of the device under test 21+
'P, is loaded into the memory 11, the devices under test 21□ and 21. The test program for the devices under test 21□ and 21. % test program storage areas 111□ and 111.1. In this way, the test program can be loaded faster than when loading from the test program storage means 22.

■ Step SS If it is determined in step S that the test program requested to be loaded has not been loaded into the memory 11, a predetermined test program is stored in the memory 11 from the test program storage means 22, as in the conventional method. Load.

As a result, the test program T of the device under test 213
Pb is stored in the test program storage area 111 . loaded into.

The test execution control unit 13 stores management information regarding the test program T P b newly loaded into the memory 11 .

Thereafter, test programs are loaded to other devices under test (not shown) in the same manner.

When the loading process of the test program for the devices under test 21+ to 21n is completed, the test execution control unit 1
3, n devices under test 211 to 21 . Run tests in parallel.

By doing the above, the devices under test 21, to 2
11 can be speeded up.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) A test program common to multiple devices under test is loaded by transferring it on memory.
Test program loading processing can be sped up.

(2) Due to (11) above, the load time of the test program can be shortened, and the overall test processing can be sped up.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the basic configuration of the present invention, Fig. 2 is an explanatory diagram of the configuration of an embodiment of the invention, Fig. 3 is an explanatory diagram of the memory management table of the embodiment, and Fig. 4 is an explanatory diagram of the same implementation. FIG. 5 is an explanatory diagram of the contents of load request program information in the example, FIG. 5 is a processing flowchart of the same embodiment, and FIG. 6 is an explanatory diagram of a conventional parallel test program load control method. 1 and 2, 10...information processing device, 11...memory, 12...
-Memory management table, 13...Test execution control unit,
14... bus, 21. ~21. ．． . . . Device under test, 22 . . . Test program storage means. i, invention f) 〓 fj - 1st figure U ζ J6 也 Aaya 6Q 5 hai φ Rimo now Te1 Toflag→Muro-1”4I
Figure 6

Claims (1)

[Scope of Claims] Test program storage means (for storing test programs for a plurality of devices under test (21_1 to 21_n))
In a test program load control method in which a test program is loaded from 22) to a memory (11) in an information processing device (10), (a) a memory in which management information regarding the test program loaded in the memory (11) is registered; (b) When loading the test program for the device under test (21i) into the memory (11), refer to the management information in the memory management table (12) and load the test program for the device under test (21i) into the memory (11).
The test program that can be used for 1i) is memory (11)
A test program comprising: a test execution control unit (13) that transfers the test program to a test program storage area of a device under test (21i) on a memory (11) when the test program is loaded into the test program. Load control method.