CN117851306B

CN117851306B - Method for determining operation mode, chip module and storage medium

Info

Publication number: CN117851306B
Application number: CN202410253174.2A
Authority: CN
Inventors: 张林生
Original assignee: Niuxin Semiconductor Shenzhen Co ltd
Current assignee: Niuxin Semiconductor Shenzhen Co ltd
Filing date: 2024-03-06
Publication date: 2024-05-31
Anticipated expiration: 2044-03-06

Abstract

The embodiment of the application provides a method for determining an operation mode, a chip module and a storage medium, which are applied to the chip and comprise the following steps: acquiring an input signal through a first input/output (IO) interface of a chip, and acquiring a channel associated clock signal corresponding to the input signal through a second IO interface of the chip; input data is obtained from the input signal based on the associated clock signal, and a target operating mode of the chip is determined based on the input data. By adopting the embodiment of the application, the selection of multiple modes of the chip is realized only through one IO interface for receiving data input and one IO interface for inputting the corresponding channel clock signal of the data input, namely, the mode switching of the chip can be realized through two IO interfaces without being limited by the number of the modes, the requirement on the switching of the operation modes of the chip can be met, and after the mode selection is finished, the IO interface for switching the operation modes of the chip can be used for transmitting other data, thereby improving the utilization rate of the IO interface and being beneficial to reducing the waste of resources.

Description

Method for determining operation mode, chip module and storage medium

Technical Field

The present application relates to the field of chips, and in particular, to a method for determining an operation mode, a chip system, and a storage medium.

Background

With the development and maturity of electronic industry automation, devices integrated with chips are gradually increased, and the chips are gradually widely applied to aspects of life of people. The Chip may be understood as a System on Chip (SoC), which may also be referred to as a System on Chip (SoC), and is a micro-System, where the SoC can be switched to different operation modes in different scenarios, so as to provide different functions. The SOC includes one or more Input/Output (IO or I/O) circuits, where the IO circuits, which are interfaces for the SOC to communicate with the outside, are also called IO interfaces, and may be used to obtain signals transmitted by an external device and determine an operation mode of the SOC.

Currently, a technician typically configures several pins as IO interfaces for implementing the determination of the operation modes of the SOC, for example, 3 parallel IO interfaces are configured in the SOC for receiving 3 parallel static signals, and then the determination of up to 8 operation modes can be implemented through binary encoding. However, in this way, the determination of the SOC operation mode is limited by the number of IO interfaces in the SOC, and in the case where the number of IO interfaces is small, the determination requirement of the SOC operation mode cannot be satisfied. In addition, as the operation modes of the SOC increase, more IO interfaces in the SOC need to be configured for selection and switching of the operation modes, resulting in resource waste.

Therefore, how to switch the operation mode of the SOC when the number of IO interfaces is small is a technical problem to be solved.

Disclosure of Invention

In a first aspect, an embodiment of the present application provides a method for determining an operation mode, where the method is applied to a chip, and the method includes:

Acquiring an input signal through a first input/output (IO) interface of the chip, and acquiring a channel associated clock signal corresponding to the input signal through a second IO interface of the chip;

And acquiring effective data from the input signal based on the channel associated clock signal, and determining a target operation mode of the chip according to the effective data.

In one possible implementation manner, the acquiring valid data from the input signal based on the channel-associated clock signal includes:

receiving and storing initial input data in the input signal based on the associated clock signal;

And under the condition that the initial input data meets a preset check rule, determining the initial input data as the valid data.

In one possible implementation, the method further includes:

acquiring password data in the initial input data;

And under the condition that the password data is matched with preset password data, determining that the initial input data meets the preset check rule.

In one possible implementation manner, the determining the target operation mode of the chip according to the valid data includes:

Acquiring mode data in the effective data;

and according to the mode data, presetting a corresponding relation between the mode data and the operation mode, determining the operation mode corresponding to the mode data, and obtaining the target operation mode of the chip.

In one possible implementation manner, after the determining the target operation mode of the chip according to the valid data, the method further includes:

And configuring a third IO interface of the chip to be used for transmitting data corresponding to the target operation mode.

and generating a mode selection completion flag, and outputting mode information for indicating the target operation mode and the mode selection completion flag to a control module of the chip.

In a second aspect, an embodiment of the present application provides a chip, including a first IO interface, a second IO interface, and a mode generating module; the first IO interface is a transmission interface between a printed circuit PCB integrated with the chip and the mode generation module, the second IO interface is a transmission interface between the PCB and the mode generation module, and the first IO interface and the second IO interface are different;

the first IO interface is used for acquiring an input signal;

the second IO interface is used for acquiring a channel associated clock signal corresponding to the input signal;

the mode generation module is used for acquiring effective data from the input signal based on the associated clock signal and determining a target operation mode of the chip according to the effective data.

In one possible implementation manner, the mode generating module is configured to obtain valid data for indicating an operation mode from the input signal based on the associated clock signal, and specifically is configured to:

and receiving and storing initial input data in the input signal based on the channel associated clock signal, and determining the initial input data as the valid data under the condition that the initial input data meets a preset check rule.

In a possible implementation manner, the pattern generating module is further configured to obtain the password data in the initial input data, and determine that the initial input data meets the preset check rule when it is determined that the password data matches with preset password data.

In one possible implementation manner, the mode generating module is configured to determine, according to the valid data, a target operation mode of the chip, and specifically is configured to:

Acquiring mode data in the effective data;

In one possible implementation, the chip further includes an Input/output multiplexer (Input/Output Multiplexer, IOMUX) and a third IO interface;

the IOMUX is used for configuring the third IO interface to transmit data corresponding to the target operation mode.

In a possible implementation manner, the mode generating module is further configured to generate a mode selection completion flag, and output mode information for indicating the target operation mode and the mode selection completion flag to the control module of the chip.

In a third aspect, an embodiment of the present application provides a chip, including a memory and a processor, where the memory stores a computer program, the computer program including program instructions, and the processor is configured to execute the program instructions to implement a method according to the first aspect.

In a fourth aspect, an embodiment of the present application provides a chip module, including a communication interface and a chip, where: the communication interface is used for carrying out internal communication of the chip module or carrying out communication between the chip module and external equipment; the chip is for performing the method of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer readable storage medium storing a computer program comprising program instructions which, when executed, cause the method of the first aspect to be implemented.

In a sixth aspect, embodiments of the present application provide a computer program product comprising a computer program or instructions which, when run on a computer, cause the computer to perform the method according to the first aspect.

In the embodiment of the application, after the input signal is obtained through the first IO interface of the chip and the associated clock signal corresponding to the input signal is obtained through the second IO interface of the chip, the effective data can be obtained from the input signal based on the associated clock signal, and then the target operation mode of the chip is determined according to the effective data. On the one hand, selection of multiple running modes of the SOC can be realized only through two IO interfaces, the selection is not limited by the number of the IO interfaces in the SOC, and the requirement of selection of the running modes of the SOC can be met under the condition that the number of the IO interfaces is small. On the other hand, the switching of the SOC operation mode can be realized only through two IO interfaces, and after the mode switching, the IO interfaces can also be used for transmitting other data, so that the utilization rate of the IO interfaces can be improved, and the waste of resources is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for determining an operation mode according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an initial input data provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a method for determining an operation mode according to an embodiment of the present application;

FIG. 4 is another schematic diagram of a method for determining an operation mode according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a method for determining an operation mode according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a device for determining an operation mode according to an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another operation mode determining device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a module device according to an embodiment of the present application.

Detailed Description

It should be noted in advance that, in order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the embodiments of the present application will be clearly and completely described in connection with one or more drawings. Moreover, the drawings shown in the embodiments of the present application are only exemplary, and for example, the execution sequence of each step in the drawings may be adaptively adjusted according to the actual application scenario. Furthermore, in the embodiments of the present application, the block diagrams shown in the drawings are merely functional entities, and do not necessarily correspond to physically independent entities. That is, the functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

During the determination of the operating mode of the SOC, it is found that: the SOC may be switched to different operation modes in different scenarios, respectively, to provide different functions, and exemplary operation modes of the SOC may include, for example: functional mode, design for Test (DFT) mode, intellectual property core (Intellectual Property Core, IP) Test (IP Test) mode, eFuse burn mode, etc. In the case where the operation mode of the SOC has a plurality of modes, several IO interfaces in the SOC are generally configured to determine the operation mode of the SOC, and the process of determining the operation mode of the SOC may also be referred to as a process of operation mode selection of the SOC. For example, a technician may configure 3 parallel IO interfaces (i.e., 3 parallel IO pins) for receiving parallel static signals, and 8 may be implemented based on binary encoding (based onCalculated) switching of the operating mode. However, as the functions of the SOC gradually increase, the modes that the SOC can switch gradually increase, and under the condition that the number of IO interfaces is small, the determining requirement of the running modes of the SOC cannot be met, for example, 3 parallel IO interfaces cannot meet the selection of more than 8 running modes. Moreover, if more IO interfaces are configured for implementing selection of the operation mode of the SOC, resource waste may be caused.

The application thus proposes a determination scheme of an operation mode, which can be applied in the scenario of switching an operation mode of an SOC. The determination scheme of the operation mode may be applied to an SOC, which may be a chip or a processor having two or more IO interfaces, or the like, and may also be applied to a computer device including two or more IO interfaces, which is not limited in the present application. For convenience of description, the method for determining the operation mode is applied to the SOC for explanation, specifically, the SOC may obtain an input signal through a first IO interface of the SOC, and obtain a corresponding associated clock signal of the input signal through a second IO interface of the SOC. Further, the SOC may obtain valid data from the input signal based on the associated clock signal and determine a target operating mode of the SOC based on the input data. Therefore, only the input signal and the associated clock signal corresponding to the input signal are respectively received through the two IO interfaces, and the selection of the SOC operation mode can be realized based on the dynamic data serially input by the input signal, so that the requirement for selecting multiple SOC operation modes under the condition of fewer SOC interfaces can be met. And after the operation mode of the SOC is selected, the IO interface for receiving input data and the associated clock signal can also be used for data transmission in specific function implementation, so that the utilization rate of the IO interface is improved.

Based on the above description, the embodiment of the present application provides a method for determining an operation mode, which may be executed by a chip, referring to fig. 1, fig. 1 is a schematic flow chart of a method for determining an operation mode, provided in the embodiment of the present application, the method for determining an operation mode includes the following steps S101 to S102:

s101, acquiring an input signal through a first IO interface of a chip, and acquiring a channel associated clock signal corresponding to the input signal through a second IO interface of the chip.

In the embodiment of the application, the IO interface in the SOC can be understood as an IO circuit, which is a circuit positioned at the outermost periphery of the SOC, is a transmission structure between the SOC and external equipment (external equipment) outside the SOC, and can realize the functions of data (signal) transmission, level conversion, driving capability improvement and the like through the IO circuit. For convenience of description, the embodiment of the application takes the SOC including two IO interfaces as an example for explanation, which are a first IO interface and a second IO interface respectively. The first IO interface and the second IO interface may respectively correspond to IO pins (pins) of two parallel SOCs in the SOC, and are respectively configured to receive different data (signals).

The SOC may acquire an input signal through the first IO interface, where the input signal is a signal including a signal for determining an operation mode, and is a serial dynamic input signal. By serial dynamic input signal is understood that data to be input (i.e. data indicating the operation mode) is transmitted sequentially as a data sequence to the first IO interface, the characters in the data sequence may be the same or different, and thus the input signal may be a serial dynamic signal. For example, if the input data carried by the input signal is 0001, 0, and 1 may be sequentially transmitted in the input signal, so that the SOC obtains 0001 input data (i.e., the data to be input as described above).

In contrast, in the conventional scheme, parallel static signals are generally received through a plurality of IO interfaces, where the parallel static signals mean that a plurality of IO interfaces can simultaneously receive input signals, and the content (characters) of the input signals received by each IO interface are the same. Illustratively, 0001 input data is received in parallel through 2 IO interfaces, the first IO interface may receive 00 and the second IO interface may receive 01, so that the SOC may also obtain 0001 input data. In this way, the input data received by each IO interface is fixed over time, i.e., a static signal. Therefore, more IO interfaces are needed to meet the selection requirements of a plurality of operation modes in the mode, and different input data are received at different moments through the IO interface of one input signal by inputting serial dynamic input signals, so that the limitation of the IO interface on the number of the operation modes is reduced.

The SOC may acquire a corresponding associated clock signal of the input signal through the second IO interface of the SOC, and since the input signal is a serial dynamic input signal, the associated clock signal corresponding to the input signal is required to indicate input data in the input signal. The associated clock signal may correspond to an input signal, meaning that the associated clock signal is a proprietary clock signal of the input signal. The associated clock signal may be a pulse signal, where the pulse signal includes a rising edge signal and a falling edge signal. The rising edge signal may be a signal at a start timing of a change from a low level to a high level in the pulse signal, for example, the pulse signal includes only 0 and 1, i.e., two level signals, and periodically switches between the level signals of 0 and 1, and the rising edge signal is a signal at a timing of switching from 0 (low level) to 1 (high level). Similarly, the falling edge signal may be a start time of a change from a high level to a low level in the pulse signal. For example, in the pulse signals including only 0 and 1, the falling edge signal is a signal at the timing of switching from 1 (high level) to 0 (low level).

It should be noted that, the input signal needs to be transmitted to the SOC together with the corresponding along-path clock signal, and this is because the along-path clock signal may be used to indicate the input data in the input signal, and specifically may be a rising edge signal or a falling edge signal in the along-path clock signal, so that the SOC may acquire the input data based on the along-path clock signal.

In one possible implementation manner, the input signal received by the first IO interface of the SOC and the associated clock signal corresponding to the input signal received by the second IO interface may be sent by a printed circuit (Printed Circuit Board, PCB) board integrated with the SOC, and the PCB board integrated with the SOC may be connected to a computer device, and control software installed in the computer device controls the PCB board. The plurality of SOCs can be integrated in the PCB, other SOCs can also send input signals and associated clock signals corresponding to the input signals to the SOCs, and it can be understood that signals sent to the SOCs by the other SOCs are transmitted through the PCB. The input signal received by the SOC and the associated clock signal corresponding to the input signal may also be transmitted by other computer devices (SOCs), which is not limited in this application.

S102, acquiring effective data from the input signal based on the channel associated clock signal, and determining a target operation mode of the chip according to the effective data.

In the embodiment of the application, the associated clock signal is a clock signal corresponding to an input signal and is used for indicating to acquire input data from the input signal, the input signal is a signal used for bearing the input data, and the SOC is a serial dynamic input signal, so that the SOC can acquire the input data from the input signal based on the associated clock signal and further determine whether the input data is valid data, wherein the valid data is data used for indicating the running mode of the SOC, and therefore the SOC can determine the target running mode of the chip based on the valid data. The valid data (input data) may be a binary coded character, such as 0011, or may be other characters, which is not limited in the present application. The target operation mode of the SOC refers to a specific operation mode of the SOC, for example, any one of the above-described function mode, DFT mode, IP TEST mode, eFuse programming mode, and the like.

The associated clock signal may be a pulse signal, including a rising edge signal and a falling edge signal, and in the transmission process of the input signal, the SOC may acquire input data from the input signal according to a preset level signal, and determine whether the input data is valid, that is, determine whether the input data is valid. The preset level signal may be a rising edge signal or a falling edge signal, which is not limited in the present application. Taking rising edge signals as an example for explanation, since the input signals are serial dynamic input signals, after the SOC acquires the input signals, the SOC can acquire the input data in the input signals once when each rising edge signal in the associated clock signals (pulse signals). Similarly, the SOC may acquire the input data in the input signal once at the time of each falling edge signal in the associated clock signal. It should be noted that, the precondition that the SOC acquires the input data from the input signal according to the preset level signal is that the transmitting end, such as the PCB board, transmits the input signal and the associated clock signal according to the preset level signal.

In one possible implementation, since the input signal is a serial dynamic input signal, the SOC cannot acquire the input data at one time, and one bit of character needs to be acquired at each rising edge signal or falling edge signal in the along-the-path clock signal, for example, if the input signal is 0001, then 0, 0 and 1 need to be acquired sequentially at the four rising edge signals (falling edge signals) of the along-the-path clock signal, that is, the SOC needs to receive and store the input data in the input signal based on the along-the-path clock signal, and the SOC needs to store the input data for 4 times in an accumulated manner, that is, when 0001 is obtained, the initial input data is obtained. Note that, the register in the SOC is not infinitely stored, for example, the register in the SOC may store the latest 32 BITs (BIT), and when new data is stored, the data stored in the earliest time may be deleted, and the data stored in the register may be kept at 32 BITs.

Further, a pattern generation module, such as an SOC, may verify the received initial input data within the SOC. The mode generation module of the SOC is a mode generation circuit, and can be used for verifying input data and determining an operation mode of the SOC. The SOC mode generating module may check whether the initial input data satisfies a preset check rule, determine that the initial input data is valid data for indicating an operation mode when it is checked that the initial input data satisfies the preset check rule, and continuously acquire the input data from the input signal based on the channel clock signal if it is checked that the initial input data does not satisfy the preset check rule, update the initial input data stored in the register, obtain updated input data, and further check the updated input data.

Specifically, for example, taking 0001 as mode data for indicating an operation mode as an example, the verification method may be to detect whether the initial input data is 4 bits, for example, 0001 includes 4 bits, and its value covers the number of operation modes, that is, detect whether the initial data is valid, and perform other verification, which is not limited in this application. After the mode generating unit of the SOC determines that the initial data check is passed, it may be determined that the initial input data satisfies a preset check rule, and then the initial input data may be determined as valid data, and further, a target operation mode of the SOC may be determined based on the valid data.

In another possible implementation manner, in order to make the bit error rate of the SOC receiving input data lower, the input data carried in the input signal may include other information, the SOC may receive and store initial input data in the input signal based on the random clock signal, where the initial input data may be transmitted by a transmitting end (as transmitted by the PCB board) after adding other information on the basis of the mode data for indicating the operation mode. The SOC may verify the initial input data obtained.

In particular, other data in the initial input data may include a pattern prefix (mode_ PREIFX), which may precede the pattern data, and may also include a pattern suffix (mode_ SUFFIX), which may follow the pattern data, and may further include other redundant information, which may be located in the pattern data. Other information may also be included in the initial input data, as the application is not limited in this regard.

Referring to fig. 2 together, fig. 2 is a schematic diagram of an input data provided in an embodiment of the present application, as shown in fig. 2, for convenience of description, the initial input data stored in the register is 32bit data, and the initial input data only includes a mode prefix and a mode suffix for explanation. The initial input data shown in fig. 2 includes three parts, a first part of a 20-bit pattern prefix (20bits MODE_PREIFX) that can be used to indicate the start of transmission of the input data (initiator), a second part of a 4-bit pattern data (4-bit mode_code) that can be used to indicate the operation mode, and a third part of an 8-bit pattern suffix (8bits MODE_SUFFIX) that can be used to indicate the end of transmission of the data (terminator).

The mode generating module of the SOC may be configured to store preset password data, where the mode prefix and/or the mode suffix may include the password data, and then the mode generating module of the SOC may acquire the password data from the mode prefix or the mode suffix, compare the acquired password data with the preset password data stored in the mode generating module, and determine that the initial input data is valid data if the comparison result indicates that the password data matches with the preset password data, and if the comparison result indicates that the comparison result is the same as the preset password data, the mode generating module may determine that the initial input data meets a preset check rule, that is, the check passes. Further, the SOC may determine a target operating mode of the SOC based on the valid data.

Specifically, the mode generating module in the SOC may acquire mode data in the effective data, where the mode data may include a mode identifier of a certain operation mode of the SOC, and the mode generating module may determine, based on a correspondence between preset mode data and the operation mode and the mode data, a target operation mode corresponding to the mode data. The corresponding relation between the preset mode data and the operation modes can be understood as a corresponding relation table of the mode data of each operation mode and each operation mode thereof, and further the mode generating module can query in the corresponding relation table based on the mode data in the effective data to obtain the operation mode corresponding to the mode data, namely the target operation mode.

In one possible implementation, the mode generation module of the SOC may generate a mode selection complete flag indicating validity of the mode information after determining the target operation mode. Further, the mode generation module may output mode information for indicating the target operation mode, which may include a mode identification of the target operation mode, and the mode selection completion flag to the control module of the SOC. Further, the control module of the SOC may switch the operation mode of the SOC based on the mode information. The control module of the SOC may be a power management unit (Power Management Unit, PMU) of the SOC, or may be other working modules of the SOC, which is not limited in this disclosure, that is, the control module is a control module that executes different threads in a target operation mode relative to a current operation mode.

The mode generation module may send the mode selection completion flag together with the mode information to the control module, or may send the mode information first and then send the mode selection completion flag. This is because, in the SOC circuit, the control module of the SOC confirms, by default, the value at the time of receiving the mode selection completion flag as a valid value when the mode selection completion flag is received. Therefore, the mode generating module transmits the mode information first, the control module of the SOC switches to the target running mode based on the mode information, and the control module of the SOC can receive the mode selection completion mark transmitted by the mode generating module, and confirms that the current value is valid.

In a possible implementation manner, the SOC further includes a plurality of iomoxes, each IOMUX corresponds to a pin of the SOC, and is configured to configure a plurality of different functions for the pin, so that the pin of the SOC can multiplex the plurality of different functions, and the multiplexing rate of the pin of the SOC is improved. In response to receiving a selection instruction of an operation mode (a switching instruction of the operation mode), a first IO mux corresponding to the first IO interface may configure the first IO interface to obtain an input signal, and a second IO mux corresponding to the second IO interface may configure the second IO interface to obtain a channel associated clock signal corresponding to the input signal. The first IO interface and the second IO interface may be default two interfaces, or may be two interfaces selected randomly, which is not limited in the present application.

In one possible implementation, after the mode generating module outputs the mode information and the mode selection completion flag, in response to the mode switching instruction, the third IOMUX of the SOC may configure a third IO interface corresponding to the third IOMUX to transmit data corresponding to the target operation mode. The third IO interface may be any other interface in the SOC, other than the first IO interface and the second IO interface, for implementing a function in the target operation mode, and the third IO interface may be one IO interface or a plurality of IO interfaces, which is not limited in the present application. The third IO interface may be the same IO interface as the first IO interface, and the third IO interface may also be the same IO interface as the second IO interface. Therefore, after the target operation mode is determined, the first IO interface and the second IO interface can be used for realizing other functions, so that the multiplexing rate of pins of the SOC is improved, and the waste of resources is reduced.

Based on the above method for determining the operation mode, the embodiment of the application provides a chip, which may be an SOC or other chips, such as a micro control unit (Microcontroller Unit, MCU), which is not limited in this regard. For convenience of description, the embodiment of the application takes the chip as an example of the SOC. Referring to fig. 3 together, fig. 3 is a schematic diagram of a method for determining an operation mode according to an embodiment of the present application, as shown in fig. 3, the SOC includes: a first IO interface 30, a second IO interface 31, an IOMUX1, an IOMUX2, a pattern generation module 33, and a control module 32. The first IO interface 30 corresponds to the IOMUX1, the second IO interface 31 corresponds to the IOMUX2, and the IOMUX1 and the IOMUX2 are connected with the mode generation module 33, where the IOMUX1 may communicate with the first IO interface 30 and the mode generation module 33, the IOMUX2 may communicate with the second IO interface 31 and the mode generation module 33, and the mode generation module 33 may be directly or indirectly connected with the control module 32 of the SOC.

In one possible implementation, the first IO interface 30 may be a transmission interface between a PCB board integrated with the SOC and a mode generation module of the SOC, and the second IO interface 31 may also be a transmission interface between a PCB board integrated with the SOC and a mode generation module of the SOC, where the first IO interface 30 and the second IO interface 31 are different. The first IO interface 30 may be configured to obtain an input signal, where the input signal may be a signal transmitted by the PCB board and including valid data indicating an operation mode, and the input signal may be a serial dynamic input signal, where the SOC is required to continuously receive and accumulate the input data. The second IO interface 31 may be configured to obtain a channel associated clock signal corresponding to the input signal, where the channel associated clock signal is used to instruct the SOC to obtain valid data (obtained by determining and processing the input data) based on the input signal. The mode generation module 33 may be configured to obtain valid data from the input signal based on the associated clock signal, and determine a target operation mode of the chip according to the valid data. That is, the pattern generation module 33 may obtain valid data by acquiring data in the input signal when the SOC is a rising edge signal or a falling edge signal of the associated clock signal based on the associated clock signal.

The input signal is transmitted to the mode generating module 33 through the first IO interface 30 and the IOMUX1, the path clock signal is transmitted to the mode generating module 33 through the second IO interface and the IOMUX2, and the mode generating module may obtain valid data based on the path clock signal, so as to determine a target operation mode of the SOC based on the valid data. Specifically, in the process of acquiring the valid data for indicating the operation mode from the input signal based on the associated clock signal, the mode generating module 33 may sequentially receive and store the initial input data based on the serial dynamic input signal in the input signal until the register of the mode generating module 33 stores data of a preset data amount, for example, 32 bits of data, and the mode generating module 33 may check the initial input data, and in the case that the check meets the preset check rule, may determine that the initial input data is valid data, and may determine the target operation mode of the SOC based on the valid data.

In one possible implementation, the verification manner may be to verify whether the mode data in the initial input data is of a preset size, whether its value exceeds the number of operation modes, or the like, and other verification may be performed, which is not limited in the present application. In the case of verification passing, the pattern generation module 33 may determine that the initial input data is valid data, and otherwise determine that the initial input data is invalid data.

The initial input data may include other information, such as the initial input data shown in fig. 2, including a pattern prefix, pattern data, and pattern suffix, among others. The pattern generating module 33 may obtain the password data in the initial input data, where the password data may be included in a pattern prefix or may be included in a pattern suffix, and if the pattern generating module 33 has preset password data, the pattern generating module 33 may compare the two to obtain a comparison result, and if the comparison result indicates that the password data in the initial input data matches the preset password data, the pattern generating module 33 may determine that the initial input data is valid data (i.e., determine that the initial input data meets a preset verification rule).

In a possible implementation manner, the mode generating module 33 may further obtain mode data in the valid data, where the mode data may include a mode identifier for indicating a target operation mode, so as to further obtain a corresponding relationship between preset mode data and an operation mode according to the mode data, and determine a target operation mode corresponding to the mode data, that is, a target operation mode of the SOC. It will be appreciated that the mode generation module 33 may determine the final target operating mode to be selected based on a table of correspondence between mode data and operating modes, and mode data in the input signal. After determining the target operation mode, the mode generating module 33 may send a mode selection completion flag and mode information for indicating the target operation mode to the control module 32 of the SOC, so that the control module 32 switches to the target operation mode and executes a thread corresponding to the target operation mode.

In one possible implementation, the SOC further includes a third IO interface, where the third IO interface corresponds to the IOMUX3, and after the mode generating module 33 determines the target operation mode, the IOMUX3 may configure the third IO interface to receive data corresponding to the target operation mode. The third IO interface may be the same interface as the first IO interface, or may be the same interface as the second IO interface, or may be other interfaces in the SOC except for the first IO interface and the second IO interface, which is not limited in the present application.

In a possible implementation manner, the determining method of the operation mode uses an SOC that includes one IO interface to obtain an input signal, another IO interface obtains a corresponding associated clock signal of the input signal as an example to explain, and the SOC may further include a plurality of IO interfaces to obtain the input signal. Referring to fig. 4 together, fig. 4 is another schematic diagram of a method for determining an operation mode according to an embodiment of the present application, and it should be noted that fig. 4 is only an example, and may further include a plurality of IO interfaces for obtaining input signals, respectively.

As shown in fig. 4, on the basis of fig. 3, the SOC further includes a fourth IO interface 34, and an iommu 4 corresponding to the fourth IO interface 34, the input signal 1 is transmitted to the pattern generation module 33 through the first IO interface 30 and the iommu 1, the input signal 2 is transmitted to the pattern generation module 33 through the fourth IO interface 34 and the iommu 4, and the path clock signal is transmitted to the pattern generation module 33 through the second IO interface and the iommu 2. Wherein the mode generation module 33 may obtain valid data from the input signal 1 and the input signal 2 based on the associated clock signal and determine the target operation mode of the SOC based on the valid data.

In another possible implementation manner, the determining method of the operation mode shown in fig. 3 takes an SOC including an IO interface to obtain an input signal, another IO interface to obtain a corresponding associated clock signal of the input signal as an example to explain, and takes one input signal and the corresponding associated clock signal as a group of inputs. Referring to fig. 5 together, fig. 5 is a schematic diagram of a method for determining an operation mode according to an embodiment of the present application, and it should be noted that fig. 5 is only an example, and may further include three or more input groups, and the number of the input groups is not limited in the present application.

As shown in fig. 5, the SOC further includes, on the basis of fig. 3, a fourth IO interface 34, an IOMUX4 corresponding to the fourth IO interface 34, a fifth IO interface 35, an IOMUX5 corresponding to the fifth IO interface 35, and a pattern generation module b36, the pattern generation module 33 shown in fig. 3 is a pattern generation module a33 shown in fig. 5, and the pattern generation module b36 is different from the pattern generation module a 33. A set of inputs: the input signal 1 is transmitted to the pattern generation module a33 (corresponding to the input signal in fig. 3) through the first IO interface 30 and the IOMUX1, and the trace clock signal 1 is transmitted to the pattern generation module a33 (corresponding to the trace clock signal in fig. 3) through the second IO interface and the IOMUX 2. Another set of inputs: the input signal 2 is transmitted to the pattern generation module b36 via the fourth IO interface 34 and the IOMUX4, and the associated clock signal 2 is transmitted to the pattern generation module b36 via the fifth IO interface and the IOMUX 5.

The pattern generation module a33 may obtain the first input data from the input signal 1 based on the random clock signal 1, and perform processing based on the first input data. The pattern generating module b33 may obtain the second input data from the input signal 2 based on the associated clock signal 2, and perform processing based on the second input data, for example, determine whether the first input data and the second input data meet a preset check rule, that is, whether the first input data and the second input data are valid data. The pattern generation module a33 and the pattern generation module b36 may perform data interaction, and thus the pattern generation module a33 and the pattern generation module b36 may collectively determine a target operation pattern of the SOC, generate a pattern selection completion flag through one or more of the pattern generation module a33 and the pattern generation module b36, and output the pattern selection completion flag and pattern information indicating the target operation pattern to the control module 32 of the SOC.

It should be noted that, in the SOC, the IOMUX generally refers to a case where there are multiple inputs and one output, and in the embodiment of the present application, the IOMUX refers to a case where there are multiple outputs, one output is that data transmitted by the IO interface is transmitted to the mode generating module, and the other outputs are that other modules for indicating that the other modules connected to the IOMUX maintain a default value (fixed value), because in the circuit of the SOC, the IOMUX is not selected to function in determining the target operation mode, but needs to maintain the default value. Indicated by "other function" in fig. 3-5, indicates that the iommu is connected to other circuit blocks of the SOC for instructing the other circuit blocks to maintain a default value (fixed value) upon receipt of an input signal or a random clock signal.

Referring to fig. 6, fig. 6 is a schematic structural diagram of an operation mode determining device according to an embodiment of the application. As shown in fig. 6, the operation mode determining apparatus 600 includes an acquisition unit 601 and a processing unit 602. Wherein:

An obtaining unit 601, configured to obtain an input signal through a first input/output IO interface of the chip, and obtain a random clock signal corresponding to the input signal through a second IO interface of the chip;

And the processing unit 602 is configured to obtain valid data from the input signal based on the associated clock signal, and determine a target operation mode of the chip according to the valid data.

In a possible implementation manner, the processing unit 602 is configured to obtain valid data from the input signal based on the associated clock signal, specifically configured to:

In a possible implementation manner, the obtaining unit 601 is further configured to obtain password data in the initial input data;

The processing unit 602 is further configured to determine that the initial input data meets the preset check rule if it is determined that the password data matches preset password data.

In a possible implementation manner, the processing unit 602 is configured to determine, according to the valid data, a target operation mode of the chip, specifically configured to:

Acquiring mode data in the effective data;

Specifically, in this case, the operations performed by the acquisition unit 601 and the processing unit 602 may be described with reference to the above-described embodiments corresponding to fig. 2.

The operation mode determining device 600 may also be used to implement other functions in the corresponding embodiment of fig. 2, which are not described herein. Based on the same inventive concept, the principle and the beneficial effects of the operation mode determining device 600 provided in the embodiment of the present application for solving the problem are similar to those of the method embodiment of the present application, and may refer to the principle and the beneficial effects of the implementation of the method, which are not described herein for brevity.

According to the embodiment of the present application, each unit in the determining device of the operation mode shown in fig. 6 may be separately or completely combined into one or several other units, or some unit(s) thereof may be further split into a plurality of units with smaller functions, which may achieve the same operation without affecting the achievement of the technical effects of the embodiment of the present application. The above units are divided based on logic functions, and in practical applications, the functions of one unit may be implemented by a plurality of units, or the functions of a plurality of units may be implemented by one unit. In other embodiments of the present application, the operation mode determining apparatus 600 may also include other units, and in practical applications, these functions may also be implemented with assistance of other units, and may be implemented by cooperation of multiple units.

The above-mentioned determination means of the operation mode may be, for example: a chip, or a chip module. With respect to each apparatus and each module included in the product described in the above embodiments, it may be a software module, or may be a hardware module, or may be a software module partially, or may be a hardware module partially. For example, for each device or product applied to or integrated on a chip, each module included in the device or product may be implemented in hardware such as a circuit, or at least some modules may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) some modules may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module contained in the device and product can be realized in a hardware mode such as a circuit, different modules can be located in the same component (such as a chip and a circuit module) of the chip module or in different components, or at least part of the modules can be realized in a software program, the software program runs in a processor integrated in the chip module, and the rest (if any) of the modules can be realized in a hardware mode such as a circuit; for each device and product applied to or integrated in the terminal, each module included in the device and product may be implemented by hardware such as a circuit, different modules may be located in the same component (for example, a chip, a circuit module, etc.) or different components in the computer device, or at least part of the modules may be implemented by software programs running on a processor integrated in the terminal, and the rest (if any) of the modules may be implemented by hardware such as a circuit.

Referring to fig. 7, fig. 7 is a schematic diagram of another operation mode determining apparatus according to an embodiment of the present application. Can be used to implement the functions of the determining means of the operating mode in the method embodiments described above. The operation mode determining means 700 may comprise a processor 701 and a transceiver 702. Optionally, the operation mode determining device 700 may further include a memory 703. Wherein the processor 701, transceiver 702, and memory 703 may be connected by a bus 704 or otherwise. The bus is shown in bold lines in fig. 7, and the manner in which other components are connected is merely illustrative and not limiting. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 7, but not only one bus or one type of bus.

The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be in electrical, mechanical, or other forms for information interaction between the devices, units, or modules. The specific connection medium between the processor 701 and the memory 703 is not limited in the embodiments of the present application.

Memory 703 may include read only memory and random access memory and provides instructions and data to processor 701. A portion of the memory 703 may also include non-volatile random access memory.

The Processor 701 may be a central processing unit (Central Processing Unit, CPU), and the Processor 701 may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSPs), application SPECIFIC INTEGRATED Circuits (ASICs), field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor, but in the alternative, the processor 701 may be any conventional processor or the like. Wherein: a memory 703 for storing program instructions.

A processor 701 for invoking program instructions stored in memory 703 for performing the steps of:

Acquiring an input signal through a first IO interface of the chip, and acquiring a channel associated clock signal corresponding to the input signal through a second IO interface of the chip;

In a possible implementation manner, the processor 701 is configured to invoke the program instructions stored in the memory 703, so as to perform the acquisition of valid data from the input signal based on the channel clock signal, specifically configured to:

In a possible implementation manner, the processor 701 is configured to invoke the program instructions stored in the memory 703 and further configured to perform obtaining the password data in the initial input data;

In a possible implementation manner, the processor 701 is configured to invoke the program instructions stored in the memory 703, so as to determine the target operation mode of the chip according to the valid data, specifically:

Acquiring mode data in the effective data;

In the embodiment of the present application, the method provided by the embodiment of the present application can be implemented by running a computer program (including program code) capable of executing the steps involved in the respective method as shown in fig. 2 on a general-purpose computing device such as a computer including a Central Processing Unit (CPU), a random access storage medium (RAM), a read only storage medium (ROM), etc., and a storage element. The computer program may be recorded on, for example, a computer-readable recording medium, and loaded into and run in the above-described computing device through the computer-readable recording medium.

Based on the same inventive concept, the principle and the beneficial effects of the device for determining the operation mode provided in the embodiment of the present application are similar to those of the device for determining the operation mode in the embodiment of the method of the present application, and may refer to the principle and the beneficial effects of the implementation of the method, and are not repeated herein for brevity.

The operation mode determining device (e.g., the operation mode determining device 600, the operation mode determining device 700) may be, for example: a chip, or a chip module. Referring to fig. 8, fig. 8 is a schematic structural diagram of a chip module according to an embodiment of the application. The module apparatus 800 may perform the relevant steps of the foregoing method embodiments, where the module apparatus 800 includes: communication module 801, power module 802, memory module 803, and chip module 804.

The communication module 801 is used for performing internal communication of the module equipment or performing communication between the module equipment and external equipment; the power module 802 is configured to provide power to the module device; the storage module 803 is configured to store data and instructions; the chip module 804 is configured to perform the following steps:

In one possible implementation manner, the chip module 804 is configured to, when acquiring valid data from the input signal based on the associated clock signal, specifically perform the following steps:

In one possible implementation, the chip module 804 is further configured to perform the following steps:

acquiring password data in the initial input data;

In one possible implementation manner, the chip module 804 is configured to, when determining the target operation mode of the chip according to the valid data, specifically perform the following steps:

Acquiring mode data in the effective data;

For each device and product applied to or integrated in the chip module, each module included in the device and product may be implemented by hardware such as a circuit, and different modules may be located in the same component (e.g. a chip, a circuit module, etc.) of the chip module or different components, or at least some modules may be implemented by software programs running on a processor integrated inside the chip module, where the remaining (if any) modules may be implemented by hardware such as a circuit.

The embodiment of the application also provides a computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, the computer program comprises one or more program instructions, and when the one or more program instructions are executed, the method provided by the embodiment of the method is executed.

The present application also provides a computer program product comprising a computer program or instructions which, when run on a computer device, cause the computer device to perform the method provided by the method embodiments described above.

With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least some modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) part of modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented in hardware such as a circuit, where different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least some modules/units may be implemented in a software program, where the software program runs on a processor integrated within the terminal, and the remaining (if any) some modules/units may be implemented in hardware such as a circuit.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of action described, as some steps may be performed in other order or simultaneously according to the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be implemented by program instructions and associated hardware, and that the program instructions may be stored in a computer-readable storage medium, which may include: flash disk, ROM, RAM, magnetic or optical disk, etc.

The foregoing disclosure is merely an example of one embodiment of the present application, and is not intended to limit the scope of the claims.

Claims

1. A method for determining an operation mode, wherein the method is applied to a chip, and comprises:

Acquiring an input signal through a first input/output (IO) interface of the chip, and acquiring a channel associated clock signal corresponding to the input signal through a second IO interface of the chip, wherein the input signal is a serial dynamic signal for carrying a data sequence of initial input data, and the channel associated clock signal is a pulse signal and is a special clock signal for indicating the initial input data in the input signal based on a rising edge signal or a falling edge signal;

Receiving and storing the initial input data in the input signal based on the associated clock signal;

under the condition that the initial input data meets a preset check rule, determining the initial input data as effective data, and determining a target operation mode of the chip according to the mode data included in the effective data and the corresponding relation between the preset mode data and the operation mode;

The effective data are data for indicating the running mode of the chip, and are initial input data meeting the preset check rule; the preset check rule is used for checking whether the password data included in the initial input data are matched with preset password data or not.

2. The method according to claim 1, wherein the method further comprises:

Acquiring the password data in the initial input data;

and under the condition that the password data is matched with the preset password data, determining that the initial input data meets the preset check rule.

3. The method according to claim 1 or 2, wherein said determining a target operating mode of the chip from the validity data comprises:

Acquiring mode data in the effective data;

4. The chip is characterized by comprising a first IO interface, a second IO interface and a mode generation module; the first IO interface is a transmission interface between a printed circuit PCB integrated with the chip and the mode generation module, the second IO interface is a transmission interface between the PCB and the mode generation module, and the first IO interface and the second IO interface are different;

The first IO interface is used for acquiring an input signal, wherein the input signal is a serial dynamic signal used for bearing a data sequence of initial input data;

The second IO interface is configured to obtain an associated clock signal corresponding to the input signal, where the associated clock signal is a pulse signal, and is a proprietary clock signal that is used to instruct the initial input data in the input signal based on a rising edge signal or a falling edge signal;

The mode generation module is used for acquiring effective data from the input signal based on the associated clock signal, and determining a target operation mode of the chip according to the mode data included in the effective data, the corresponding relation between preset mode data and the operation mode, wherein the effective data is data for indicating the operation mode of the chip, and is initial input data meeting a preset check rule, and the preset check rule is a check rule for checking whether the password data included in the initial input data are matched with the preset password data.

5. The chip of claim 4, wherein the chip further comprises a plurality of chips,

The mode generating module is configured to obtain valid data for indicating an operation mode from the input signal based on the associated clock signal, and specifically is configured to:

and receiving and storing initial input data in the input signal based on the channel associated clock signal, and determining the initial input data as the valid data under the condition that the initial input data meets the preset check rule.

6. The chip of claim 5, wherein the chip comprises a plurality of chips,

The mode generating module is further configured to obtain the password data in the initial input data, and determine that the initial input data meets the preset check rule when determining that the password data matches the preset password data.

7. The chip according to any one of claim 4 to 6, wherein,

The mode generating module is configured to determine a target operation mode of the chip according to the valid data, and is specifically configured to:

Acquiring mode data in the effective data;

8. A chip module, characterized in that the chip module comprises a communication interface and a chip, wherein: the communication interface is used for carrying out internal communication of the chip module or carrying out communication between the chip module and external equipment; the chip is configured to perform the method of any one of claims 1-3.

9. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed, cause the method according to any one of claims 1-3 to be performed.