KR20180038388A - Control device, in particular control device for a motor vehicle - Google Patents

Abstract

The present invention relates to a control device (10) especially for a vehicle. The control device (10) includes a calculation unit (12) for periodically transmitting a data frame (17) to one or more surrounding units (14) to be controlled by using a control signal through a serial bus (16). The calculation unit (12) inserts first data (22) specifying the control signal in each data frame (17).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a control device,

The invention relates to a control device according to the preamble of claim 1 and to a method according to an equivalent independent claim.

BACKGROUND OF THE INVENTION Control devices for automobiles that perform a large amount of complicated control tasks with high computational performance are known in the market. In this case, data exchange between the various parts of the control apparatus is required. As miniaturization or power enhancement advances, the construction space available for electrical wiring becomes less and more expensive. An example of a patent disclosure document belonging to this specialization is DE 10 2005 042 493 A1.

The basic problem of the present invention is solved by a control device according to claim 1 and a method according to an equivalent independent claim. Preferred improvements are set forth in the dependent claims. Also, important features of the present invention can be seen in the following description and drawings, wherein the features may be important for the present invention, whether alone or in various combinations.

The present invention particularly relates to a control apparatus for an automobile, and the control apparatus includes an operation unit configured to periodically transmit a data frame through a serial bus to one or more peripheral units controlled using a control signal. In this case, the arithmetic unit is configured to insert the first data characterizing the control signal into each data frame.

For example, a data frame is generated using an N-bit serial shift register. In this case, the N-bit serial shift register is loaded in parallel with the first data periodically after each N serial shift clocks, such that the serial shift clocks are inserted into each data frame. An "operational unit" is characterized in particular by including all means required for the formation of a data frame and for the serial transmission of a data frame. For a broader understanding, the arithmetic unit comprises means for at least partially generating the first data. Similarly, the arithmetic unit may comprise means for generating second data in a manner suitable for serial transmission and inserting it into a data frame as described in more detail below. In one configuration, the computing unit is at least partially a portion of the processor core, or at least part of the microcontroller.

The present invention has the advantage that the first data is successively transmitted to the peripheral unit in the time raster of the periodically formed data frame, and the frame-by-frame interruption during transmission does not occur according to the present invention. That is, the transmission of the first data does not have a time gap. Thus, jitter (clock fluctuation or clock jitter) characterizing the transmission of the first data can be preferably minimized. Because of the minimized jitter in this way, the first data can be transmitted jointly, preferably using a serial bus, instead of using each electrical connection, so that the lines and wiring area on the substrate can be saved. In addition, terminals ("pins") for the integrated semiconductor circuit of the control device can be saved or used for other purposes.

In one configuration of the control apparatus, in addition to the first data, the operation unit is configured to insert the second data into one or more portions of the data frame, and in particular, the second data may include configuration data and / or control data and / . Thereby, preferably the second data can also be transmitted together, in which case the transmission of the first data is not further offset, interrupted, or otherwise adversely affected in any way. In particular, this does not cause jitter of the first data. In one configuration, the computing unit also includes means for at least partially generating configuration data and / or control data and / or diagnostic data.

The second data may include, for example, so-called " commands ", or may include any other data that needs to be transferred from the operation unit to the peripheral unit. In this case, the second data does not necessarily have to be transmitted continuously. For example, the second data is only temporarily (i. E., Is not present in each data frame unlike the first data) and / or only partially, and transmission is only required in such a case.

In addition, the configuration data and / or control data and / or diagnostic data may comprise any structure. For example, such data may exist, at least in part, as parallel data, e.g., as bytes. Likewise, such data may exist as a plurality of single signals, at least partially independent of one another.

A first number N1 of data bits of each data frame is assigned to the first data and a second number N2 of data bits of the data frame is assigned at least partially to the second data, Preferably, the first number N1 is greater than the second number N2. Thereby, the first data is transmitted in each data frame, and in the first data, a larger overall transmission capacity is possible, preferably in relation to the second data.

In one configuration, the arithmetic unit is configured such that the number Nl and / or the number N2 are calculated differently in time-different data frames. For example, a (temporally specified) group of data frames may have a specific number (N1, N2), and a (temporally specified) subsequent group of data frames may have a different number (N1 and / Lt; / RTI > In one embodiment, the numbers N1 and / or N2 may even differ for each data frame. Thereby, the transmission capacity, which is characterized by the number of bits of the data frame, can be preferably distributed for each request for the first data and the second data.

In another configuration, a peripheral unit is arranged in the control unit, which includes in particular one or more control modules for the actuator. This allows the arithmetic unit to perform relatively time-critical control of the actuator, preferably via the serial bus. For example, the actuator may be an electromagnetic actuator for the injection valve of the internal combustion engine.

In another configuration, the first data characterizes one or more real-time control signals, particularly one or more pulse width modulation control signals. For example, the pulse width modulation control signal may preferably be used for control of the electromagnetic actuator. The arithmetic unit can transmit a control signal having a relatively small offset and a relatively small jitter to each control module of the peripheral unit via the serial bus.

According to one embodiment, this "real time control signal" is characterized in that offsets and / or jits can continue to be allowed within approximately two time periods of the data frame at most. Which will be described in more detail below.

In one preferred configuration, the second data does not include a real-time signal of this type. Thereby, the second data can preferably be serialized, at least in part, as will be described in detail below. Thereby, preferably the additional first data may be transmitted together within the data frame.

In another configuration, the control device includes one or more converters configured to generate a second number of second data (N2) from existing configuration data and / or control data and / or diagnostic data. Thereby, configuration data and / or control data and / or diagnostic data can be advantageously processed before being inserted into the data frame. For example, frame information for the second data or other additional information may be inserted.

In another configuration, the transducer is configured as a parallel-to-serial converter and the configuration data and / or the control data and / or the diagnostic data are transmitted at least temporarily, individually or collectively, to a bit width Respectively. For example, configuration data and / or control data and / or diagnostic data ("data") may be presented as a plurality of single signals at least partially as bytes and / or at least partially independent of each other. The above-described data can then preferably be at least partially serialized. Correspondingly, the number N2 of the second data becomes small and the number N1 of the first data becomes large. In one embodiment, the number N2 is 1, whereby the data is "fully serialized" for transmission.

In another arrangement, the transducer or parallel / serial converter is configured to insert frame information and / or control information in the second data for serial transmission. Thereby, the configuration data and / or the control data and / or the diagnostic data can preferably be accurately identified after the transmission without the need for additional synchronization lines or the like.

In another configuration, the transducer or parallel / serial converter includes a Universal Asynchronous Receiver Transmitter (UART) interface. Thereby, highly desirable generation of the second data from the configuration data and / or the control data and / or the diagnostic data is possible.

In another configuration, the serial bus is an MSC (Micro Second Channel). Thereby, the intrinsic characteristics of the MSC can be preferably used also for the control apparatus.

In addition, the present invention particularly relates to a method of operating a control apparatus for an automobile, and the control apparatus includes an operation unit configured to periodically transmit a data frame through a serial bus to one or more peripheral units to be controlled using a control signal . In this case, the arithmetic unit inserts the first data characterizing the control signal in each data frame. Advantages comparable to those already described for the control device according to the invention are obtained.

In one configuration of the method, the second data is inserted into one or more portions of the data frame in addition to the first data by the computing unit, and in particular the second data includes configuration data and / or control data and / or diagnostic data .

In another configuration of the method, the configuration data and / or the control data and / or the diagnostic data have a bit width greater than the number of second data (N2) at least temporarily, either individually or collectively, Or the control data and / or the diagnostic data are converted into the number of second data (N2) according to the type of the parallel / serial converter.

In the case of the method arrangements, advantages similar to those already described for the configurations of the control device are obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Fig. 1 shows a first embodiment of a control apparatus having an arithmetic unit and a peripheral unit connected to each other via a serial bus.
Fig. 2 shows a second embodiment of a control apparatus having an arithmetic unit and a peripheral unit connected to each other via a serial bus.
3 is a flow chart of a method of operating the control device according to Fig. 1 or Fig.

The same reference numerals are used for functionally equivalent elements and variables in different embodiments than in all figures.

1 shows in particular a first embodiment of a control device 10 for an automobile, in which the control device 10 is connected in series to one or more peripheral units 14 (right in Fig. 1) (Left side of Figure 1) configured to periodically transmit a data frame 17 via a bus 16. [ In this case, the arithmetic unit 12 is configured to insert, within each data frame 17, the first data 22 characterizing the control signal. In this embodiment, the peripheral unit 14 is disposed in the control device 10, and the peripheral unit 14 includes one or more control modules (not shown) specifically for an actuator (not shown).

The computing unit 12 includes a first device 18 for periodically transmitting a data frame 17 to the peripheral unit 14 via the serial bus 16. [ Expressed simply, the device 18 may continuously convert the total number (N) of data bits that can be periodically supplied into a data frame 17 and transmit it serially.

The remaining elements of the control device 10 are not shown in Fig. 1 for the sake of simplicity. Thus, the control device 10 is shown as a dotted frame. In one embodiment, the serial bus 16 is a Micro Second Channel (MSC).

The computing unit 12 is further configured to insert the second data 24 in one or more portions of the data frame 17 in addition to the first data 22, Or configuration data and / or control data and / or diagnostic data. The configuration data and / or control data and / or diagnostic data are denoted by a common reference numeral 28.

In this case a first number N1 of data bits of each data frame 17 is assigned to the first data 22 and a second number N2 of data bits of the data frame 17 is at least transient To the second data 24, and preferably the first number N1 is greater than the second number N2. For example, the first number N1 is 12 and the second number N2 is 4. In one embodiment, the second number N2 is one. Thus, the number Nl can be increased, for example by 3, so that a very large number of first data 22 per hour can be transmitted over the serial bus 16. [

In this embodiment, the first data 22 represents one or more real-time control signals, in particular one or more pulse width modulation control signals. For example, these pulse width modulation control signals can be used respectively for control of the driver stage for the injection valve of the internal combustion engine.

Control device 10 includes a transducer 26 configured to generate a second number N2 of second data 24 from existing configuration data and / or control data and / or diagnostic data (28) do.

In FIG. 1, the converter 26 is configured as a parallel-to-serial converter 26 and the configuration data and / or control data and / or diagnostic data are transmitted, at least temporarily, And has a bit width larger than the number N2. For example, in Fig. 1, the bit width is 8 bits. In addition, the transducer 26 is configured to insert frame information 30a and / or control information 30b into the second data 24 for serial transmission. The frame information 30a and the control information 30b are transmitted by the device 18 in a transparent manner, in other words, the devices 18,20 do not evaluate or change the information.

The number N of data bits is stored in the peripheral unit 14 in correspondence with the first device 18 of the calculation unit 12 using the data frame 17 periodically transmitted through the serial bus 16 To generate again in parallel form, there is a second device 20. In this case information is transferred from the arithmetic unit 12 to the peripheral unit 14 so that the first and second data 22 and 24 contained in the data frame 17 are again clearly and seamlessly transferred to the peripheral unit 14. [ Lt; / RTI >

For example, this information is sent with additional bits inserted into the data frame 17 complementarily. In a preferred embodiment, this information is transmitted over an additional line, and the data frame 17 preferably includes only first and second data 22, 24 (see FIG. 2).

For example, the serial bus 16 may comprise one, two, three or more electrical lines or conductor strips of a substrate. The number of required or used lines may depend, inter alia, on the degree of coding of the serial data of the data frame 17. For example, a clock signal 36, a data signal 42 and optionally a synchronization signal may be required. This also refers to the lower end of Fig.

A single line for the serial bus 16 may be sufficient if the data signal 42 includes one clock, data in the data frame 17, and synchronization information or frame information in coded form. To this end, additional bits are inserted which are optionally inserted in the data frame 17 in some cases. However, this additional bit is not shown in FIG.

The serial / parallel converter 32 is arranged in the peripheral unit 14 in correspondence with the parallel-to-serial converter 26 of the calculation unit 12. The serial-to-parallel converter 32 again outputs the first configuration data and / or the control data and / or the second control data 30b, using the frame information 30a and / or the control information 30b from the re-acquired second data 24 ' Data (reference numeral 28 ') can be clearly determined without error. Likewise, the first data 22 'is clearly reacquired using the second device 20 without error.

Fig. 2 shows a second embodiment for the control device 10. Fig. 1, a computing unit 12 is shown in the left area and a peripheral unit 14 is shown in the right area. The serial bus 16 is shown in the lower central region of FIG.

In the embodiment of Figure 2, the serial bus 16 is the so-called "MSC (Micro Second Channel) ".

A clock generator 34 for generating a clock signal 36 is disposed in the operation unit 12, and the clock signal clocks a plurality of elements shown in Fig. In particular, the clock signal 36 forms a serial shift clock for the shift register 18a of the first device 18. Using the shift register 18a, a data frame 17 for transmission to the peripheral unit 14 is periodically generated.

Also, the clock signal 36 is divided by the first factor using the clock divider 38. [ This first argument is 16 in this embodiment and corresponds to the number of bits of the serial shift register 18a. Thereby, a divided clock signal 40 is formed which enables the simultaneous transfer of the first and second data 22, 24 to the serial shift register 18a in particular.

The serial bus 16 of the embodiment of Figure 2 includes in this embodiment a clock signal 36 of the clock generator 34, a clock signal 40 divided by the clock divider 38, And a data signal 42, which in turn comprises a first data 22 and a second data 24 in bit order. That is, in the present embodiment, the data frame 17 has 16 bits. At the same time the divided clock signal 40 characterizes the synchronization information by which the first data 22 and the second data 24 are clearly reacquired in the device 20 of the peripheral unit 14 .

In addition, a total of five blocks 44a, 44b, 44c, 44d and 44e are implemented in the computing unit 12, which jointly generate or characterize six real-time control signals. In this embodiment, the real-time control signals of blocks 44a, 44b and 44c characterize three pulse width modulation control signals and the real-time control signals of blocks 44d and 44e characterize the total Characterizes three logic signals.

In the upper left area of FIG. 2, the blocks denoted by reference numeral 28 characterize the configuration data and / or control data and / or the diagnostic data, respectively, which are transferred into the shift register 26a of the parallel / Can be inserted in parallel. This process is represented by a vertical thick arrow in FIG. The shift register 26a has, for example, 16 bit positions and the bit length of the shift register 26a can be preset regardless of the bit length of the shift register 18a of the first device 18. [ In addition, the above-mentioned 16 bit positions already include the frame information 30a and / or the control information 30b described in Fig.

The divided clock signal 40 is supplied to the shift register 26a as a serial shift clock. Thereby, in this embodiment, the shift register 26a is 16 times slower than the shift register 18a of the first device 18.

In the embodiment of FIG. 2, the configuration data and / or control data and / or diagnostic data are converted into a 1-bit serial form using the shift register 26a. Thus, the second number N2 of the second data 24 (see FIG. 1) is one. In this embodiment, the second data 24 in relation to the transmitted data frame 17 is inserted into the serial shift register 18a of the first device 18 before the first data 22 in time. Alternatively, however, the second data 24 may be inserted into any bit position in the shift register 18a.

The computing unit 12 is configured to generate substantially three signals: a periodically generated data frame 17 of the first data signal 42, a second clock signal 36, and a third And transmits the clock signal (40) to the peripheral unit (14).

Due to the synchronization enabled by the divided clock signal 40, the data frame 17 contains only data, i.e., the first and second data 22 and 24, entirely in the embodiment of Fig. Therefore, frame information and the like need not be transmitted together in the data frame 17.

Similar to the first device 18, the second device 20 of the peripheral unit 14 similarly includes a shift register 20a having a 16-bit number of bits. With the use of the shift register 20a, the first and second data 22, 24 can be clearly reacquired from the data frame 17 without error.

Also, the peripheral unit 14 includes a serial-to-parallel converter 32 (upper right portion of FIG. 2), by which the second data 24 'is again supplied with the initial configuration data and / or control data and / Diagnostic data 28 '. To this end, the second data 24 'is read from the shift register 20a at a bit position comparable to that of the shift register 18a and written serially into the shift register 32a of the serial-to-parallel converter 32 .

In particular, the offset between the first first data 22 and the re-acquired first data 22 'is small, and corresponds to, for example, at most about the time length of approximately two data frames 17 in this embodiment . This characterizes the so-called "real-time control signal" that can also be used for the first data 22, i.e., a relatively time critical control signal.

The first possible rate of the offset characterizes the parallel transfer of the first data 22 into the shift register 18a. The parallel transfer is performed periodically by the divided clock signal 40, whereby a kind of "sampling " is performed. Thus, the first possible ratio of offsets can reach approximately the time length of the data frame 17.

The second possible rate of offset characterizes the serial shifting (to the right in FIG. 2) of the data signal 42 into the shift register 18a. After approximately the time length of the data frame 17 all the bits of the data signal 42 are shifted from the shift register 18a to the right and inserted into the shift register 20a of the peripheral unit 14 correspondingly .

The third possible rate of offset is characterized by the parallel transfer into and / or from the shift register 20a into the shift register 18a. The rate of such offsets is relatively small and reaches approximately one or two time periods of the clock signal 36 of the clock generator 34 approximately.

The frequency of the clock signal 36 is, for example, 40 MHz. It is understood that this frequency may include any other value. Likewise, the bit length of each of the shift registers (various reference numerals) used in Figs. 1 and 2 is merely exemplary and may also include any other desired value. Likewise, the configuration shown in FIGS. 1 and 2 and having a signal or information representative of the first data 22 and the second data 24, respectively, is merely exemplary and may alternatively be configured differently.

The operation of the elements of the control device 10 shown in Fig. 2 is preferably performed as follows. The clock generator 34 continuously generates a clock signal 36 for the serial shift clock of the shift registers 18a, 20a. At the same time, the clock signal 36 is distributed in 16 in the clock divider 38. The divided clock signal 40 forms a shift clock for the shift register 26a of the parallel-to-serial converter 26 and the shift register 32a of the serial-to-parallel converter 32.

The divided clock signal 40 is also used to cause all 16 clock stages of the clock signal 36 to carry out parallel shifting of the first and second data 22 and 24 in the shift register 18a do. At the same time, the contents of the shift register 26a are shifted serially one bit (to the right). Likewise, the divided clock signal 40 causes all sixteen clock stages of the clock signal 36 to read and output in parallel the bits actually present in the shift register 20a, and then the sixteen clocks of the clock signal 36 Are used to store them in parallel for the step. To this end, the shift register 20a comprises a corresponding parallel register, which is not shown in the drawing for reasons of simplicity.

Another clock divider, not shown in the figure, may again divide the divided clock signal 40 to generate a parallel input clock (not shown) for the shift register 26a of the parallel-to- Divide by the argument. As a first factor characterizes the size of the shift register 18a of the first device 18, the second factor correspondingly characterizes the size of the shift register 26a. Thus, in this embodiment, the second argument is 16.

In this manner, all 256 clock steps of the clock signal 36 perform parallel transfer of the configuration data and / or control data and / or diagnostic data into the shift register 26a. The serial-to-parallel converter 32 operates in a correspondingly opposite manner in the peripheral unit 14. The second data 24 'is read out from the shift register 20a according to the divided clock signal 40 and written in series into the shift register 32a.

(Or similar) generated within the peripheral unit 14, preferably using the frame information 30a and / or the control information 30b, used for the shift register 26a of the P / Clock) of the data contained in the shift register 32a for the parallel registers (not shown) in which all the 256 clock stages of the clock signal 36 in this embodiment are arranged in the block 28 ' It is used to enable parallel migration. In this manner, the configuration data and / or control data and / or diagnostic data are reacquired and optionally provided to the peripheral unit 14 for further processing.

As can be seen, in particular, the transmission of the first data 22 to the peripheral unit 14 in the time raster of the periodically formed data frame 17 is carried out continuously and in accordance with the invention, No interruption occurs. In particular, the transmission of the first data 22 does not include a time gap. In a comparable manner, if each second data is actually present, the second data 24 is transmitted without additional offsets and / or interrupts because the first data (e.g., 22 as well as possible second data 24 are also transmitted.

In one embodiment of the control device 10, the P / S converter 26 and the S / P converter 32 each include a Universal Asynchronous Receiver Transmitter (UART) interface.

Since the frames of the UART interface each start with a start bit "0 ", the receiver UART interface is synchronized to it and can recognize the start of the frame. Indeed, preferably, one bit may be transmitted if the configuration data and / or control data and / or diagnostic data are to be transmitted by the UART interface. Thereby, in contrast to the UART interface frame format, any other frame format or bit sequence in which each frame start is defined as 0 bits can be used. This is desirable, for example, if the standard UART interface (8-bit serial length) is too short.

In an application, if the transmission capacity for the second data 24 is too small, the number N2 may be increased to, for example, 2 or 4, unlike the value of 1 (FIG. 2) ). Corresponding to each number N2, the serial shifting into the shift registers 26a, 32a with respective clock stages of the divided clock signal 40 is performed with 1, 2, or 4 bits.

3 shows a flow chart of a method of operation of a control device 10 for an automobile in particular and the control device 10 is connected to at least one peripheral unit 14 controlled using a control signal via a serial bus 16 And an operation unit 12 configured to transmit the data frame 17 periodically. In this case, the arithmetic unit 12 is configured to insert, within each data frame 17, the first data 22 characterizing the control signal. The insertion of the first data 22 can be performed strictly periodically, and without interruption in this respect. This is illustrated in block 3 in FIG.

In a subsequent block 110 the second data 24 is further inserted into the first data 22 into one or more parts of the data frame 17 via the arithmetic unit 12 and the second data 24, Or configuration data and / or control data and / or diagnostic data.

In this case, the configuration data and / or the control data and / or the diagnostic data have a bit width greater than the number N2 of the second data 24, at least temporarily, individually or collectively, Or the control data and / or the diagnostic data are converted into the number N2 of the first data 24 according to the type of the parallel / This is illustrated through a subsequent block 120.

In a subsequent block 130, the data frame 17 is passed to the peripheral unit 14 in series. In subsequent block 140, the first data 22 'is read out and stored in parallel from the shift register 20a of the second device 20. At the same time, the actual bit of the second data 24 'is written into the shift register 32a of the S /

In subsequent block 150, the configuration data and / or control data and / or diagnostic data is reacquired from the second data 24 'by the S / P converter 32. The method is then continued cyclically at the beginning of block 100.

The steps entered in blocks 120 and 150 are the same as those described above where the parallel-to-serial converter 26 and the serial-to-parallel converter 32 are partly divided into 256 by one argument Is operated by the clock signal 36, and has a correspondingly slower processing period.

The transmission of the first and second data 22, 24 over the serial bus 16, as described using the control device 10 illustratively shown in Figures 1 and 2, Can also be preferably performed.

Claims (13)

A control device (10) comprising an arithmetic unit (12) configured to periodically transmit a data frame (17) via a serial bus (16) to one or more peripheral units (14) to be controlled using a control signal,
The computing unit (12) is configured to insert first data (22) characterizing a control signal in each data frame (17). 2. The apparatus of claim 1, wherein the computing unit (12) is further configured to insert second data (24) into one or more portions of the data frame (17) in addition to the first data (22) Characterized in that it comprises configuration data and / or control data and / or diagnostic data. Method according to claim 2, characterized in that a first number (N1) of data bits of each data frame (17) is assigned to a first data (22) and a second number of data bits (N2) of a data frame Is at least temporarily assigned to the second data (24), and the first number (N1) is greater than the second number (N2). A control device (10) according to any one of claims 1 to 3, characterized in that the peripheral unit (14) is arranged in the control device (10). 4. A control device (10) according to any one of claims 1 to 3, characterized in that the first data (22) characterizes one or more real time control signals. 4. The system according to claim 2 or 3, wherein the control device (10) is configured to generate a second number (N2) of second data (24) from existing configuration data and / or control data and / (26). ≪ / RTI > 7. The system according to claim 6, wherein the transducer is configured as a parallel-to-serial converter and wherein the configuration data and / or the control data and / or the diagnostic data are transmitted, at least temporarily, (N2) of the control signal (N2). 7. A control device (10) according to claim 6, characterized in that the transducer (26) is arranged to insert frame information (30a) and / or control information (30b) in the second data (24) for serial transmission. 7. A control device (10) according to claim 6, characterized in that the transducer (26) comprises a Universal Asynchronous Receiver Transmitter (UART) interface. 4. A control device (10) according to any one of claims 1 to 3, characterized in that the serial bus (16) is an MSC (Micro Second Channel). A method of operating a control device (10) comprising an arithmetic unit (12) configured to periodically transmit a data frame (17) via a serial bus (16) to one or more peripheral units (14) As a result,
Characterized in that the operating unit (12) is arranged to insert first data (22) characterizing the control signal in each data frame (17). 12. The apparatus of claim 11, wherein the computing unit (12) is configured to insert the second data (24) in one or more portions of the data frame (17) in addition to the first data (22) Wherein the control data includes configuration data and / or control data and / or diagnostic data. 13. The method of claim 12, wherein the configuration data and / or control data and / or diagnostic data has a bit width that is greater than the number (N2) of second data (24) at least temporarily, either individually or collectively, And / or the control data and / or the diagnostic data are converted to a number (N2) of the second data (24) according to the type of the P / S converter (26).

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