CN107918595B

CN107918595B - Control device, in particular for a motor vehicle

Info

Publication number: CN107918595B
Application number: CN201710905695.1A
Authority: CN
Inventors: A.克尼尔; A.奥厄; D.马奎特; E.贝克; R.亨纳; S.福克斯
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2016-10-06
Filing date: 2017-09-29
Publication date: 2024-03-08
Anticipated expiration: 2037-09-29
Also published as: KR102371270B1; KR20180038388A; CN107918595A; DE102016219347A1

Abstract

The invention provides a control device, in particular for a motor vehicle. The invention relates to a control device (10), in particular for a motor vehicle, wherein the control device (10) comprises a computing unit (12) which is designed to periodically transmit data frames (17) via a serial bus (16) to at least one peripheral unit (14) to be actuated by means of control signals. The computing unit (12) is designed to insert first data (22) representing the control signal into each data frame (17).

Description

Control device, in particular for a motor vehicle

Technical Field

The present invention relates to a control device according to the preamble of claim 1 and a method according to the parallel patent claims.

Background

Control devices for motor vehicles are known from the market, by means of which a plurality of complex control tasks are executed with high computing power. In particular, data needs to be exchanged between different parts of the control device. In the course of gradual miniaturization or performance improvement, the structural space available for electrical wiring is becoming more scarce and more expensive. Patent disclosures from this technical field are for example DE 10 2005 042 493 A1.

Disclosure of Invention

The problem on which the invention is based is solved by a control device according to claim 1 and by a method according to the parallel claim. Advantageous developments are specified in the dependent claims. Features which are essential for the invention can furthermore be found in the following description and in the drawings, wherein said features can be essential for the invention not only individually but also in different combinations, without this being explicitly pointed out again.

The invention relates to a control device, in particular for a motor vehicle, wherein the control device comprises a computing unit which is designed to periodically transmit data frames via a serial bus to at least one peripheral unit to be actuated by means of control signals. The calculation unit is configured to insert first data characterizing the control signal into each data frame.

For example, a data frame is generated using an N-bit serial shift register. The N-bit serial shift register is periodically loaded with first data, which are thus inserted into the corresponding data frame, in parallel after N serial shift clocks, respectively. The "calculation unit" is currently characterized in that it comprises all the devices required for forming a data frame and for serial transmission of the data frame. In a broader understanding, the computing unit further comprises means for generating, at least in part, the first data. Also, the calculation unit may comprise means for generating the second data in a manner suitable for serial transmission and for inserting together into the data frame, as will be explained further below. In one embodiment, the computing unit is at least partially part of the processor core or at least partially part of the microcontroller.

The invention has the following advantages: the first data is transmitted to the peripheral unit continuously in accordance with a time grid (master) of periodically formed data frames, wherein no frame-by-frame interruption occurs during the transmission according to the invention. Thus, the transmission of the first data has no time slots. Accordingly, jitter (clock fluctuations or vibrations) characterizing the transmission of the first data may advantageously be minimized. As a result of the jitter thus minimized, the first data can thus be transmitted jointly, advantageously by means of the serial bus, instead of by means of the corresponding electrical connection, whereby wiring and thus the wiring area on the circuit board can be saved. Furthermore, the connection terminals ("pins") at the integrated semiconductor circuit of the control device can be saved or used for other purposes.

In one embodiment of the control device, the computing unit is configured to insert second data in addition to the first data into at least a part of the data frame, wherein in particular the second data comprises configuration data and/or control data and/or diagnostic data. The second data can thus advantageously be transmitted likewise, wherein the transmission of the first data is not additionally delayed, interrupted or otherwise affected. In particular, jitter of the first data is thereby not caused. In one embodiment, the computing unit further comprises means for generating configuration data and/or control data and/or diagnostic data at least in part.

The second data may for example comprise so-called "commands" or any other data that should be transmitted by the computing unit to the peripheral unit. Here, the second data need not necessarily be transmitted continuously. For example, the second data is only temporarily (i.e. not in each data frame unlike the first data) and/or only partially present, and accordingly only needs to be transmitted at that time.

Furthermore, the configuration data and/or the control data and/or the diagnostic data may have any structure per se. For example, the data may exist at least partially as parallel data, e.g. as bytes. These data can likewise exist at least partially as a plurality of individual signals that are independent of one another.

In a further embodiment, a first number N1 of data bits per data frame is allocated to the first data and a second number N2 of data bits per data frame is allocated to the second data at least temporarily, wherein preferably the first number N1 is greater than the second number N2. The first data is thereby transmitted in each data frame, wherein the first data advantageously achieves an overall greater transmission capacity relative to the second data.

In one embodiment, the calculation unit is configured to determine the number N1 and/or the number N2 differently for data frames that differ in time. For example, a group of data frames (defined in time) may have a certain number N1 and N2, and an immediately following group of data frames (defined in time) may have a different number N1 and/or N2. In one embodiment, the number N1 and/or N2 may even be different for each data frame. The transmission capacity, which is characterized by the number of bits of the data frame, can thus advantageously be allocated to the first data and the second data for the respective requirements.

In a further embodiment, it is provided that the peripheral unit is arranged in the control device, wherein the peripheral unit has, in particular, at least one actuating assembly for the actuator. The calculation unit can therefore advantageously also carry out a comparison-time-critical control of the actuators via the serial bus. For example, the actuator may be an electromagnetic actuator for a fuel injector of an internal combustion engine.

In a further embodiment, the first data represent at least one real-time control signal, in particular at least one pulse width modulated control signal. For example, a pulse width modulated control signal may advantageously be used to operate an electromagnetic actuator. The computing unit may transmit the control signals via the serial bus to the respective control components of the peripheral unit with relatively small delays and relatively small jitters.

According to one embodiment, such a "real-time control signal" is characterized in that delays and/or jitter of at most approximately two time periods of a data frame can also be tolerated. This will be explained further below.

In a preferred embodiment, the second data does not comprise such a real-time signal. Thereby, the second data may advantageously be at least partially serialized, as will be explained further below. Thereby, additional first data may advantageously be transmitted together in a data frame.

In a further embodiment, the control device has at least one converter which is designed to generate a second number N2 of second data from the current configuration data and/or control data and/or diagnostic data. Thus, the configuration data and/or control data and/or diagnostic data may advantageously be processed prior to insertion into the data frame. For example, to enable insertion of frame information or other additional information for the second data.

In a further embodiment, the converter is configured as a parallel-serial converter, wherein the configuration data and/or the control data and/or the diagnostic data each have, at least temporarily, a bit width that is greater than the number N2 of second data, individually or jointly. For example, configuration data and/or control data and/or diagnostic data ("data") may exist at least partially as bytes and/or at least partially as a plurality of individual signals that are independent of one another. Thus, the data described above may advantageously be at least partially serialized. Accordingly, the number N2 of the second data may be reduced, and the number N2 of the first data may be enlarged. In one embodiment, the number N2 is 1, whereby the data described above is said to be "fully serialized" for transmission to some extent.

In a further embodiment, the converter or the parallel-serial converter is designed to insert frame information and/or control information for serial transmission into the second data. The configuration data and/or the control data and/or the diagnostic data can thus advantageously be correctly identified after transmission without additional synchronization lines or the like being required.

In a further embodiment, the converter or the parallel-serial converter comprises a UART interface (english: "Universal Asynchronous Receiver Transmitter (universal asynchronous receiver)"). Hereby, it is achieved that the second data is particularly advantageously generated from configuration data and/or control data and/or diagnostic data.

In another embodiment, the serial bus is a microsecond bus MSC (English: "Micro Second Channel (microsecond channel)"). Thus, the specific properties of the microsecond bus can also be used advantageously for controlling the device.

The invention further relates to a method for operating a control device, in particular for a motor vehicle, wherein the control device comprises a computing unit which is designed to periodically transmit data frames via a serial bus to at least one peripheral unit to be actuated by means of control signals. The computing unit inserts first data characterizing the control signal into each data frame. Similar advantages to those already described above for the control device according to the invention result.

In one embodiment of the method, second data are inserted into at least a part of the data frame by the computing unit in addition to the first data, wherein in particular the second data comprise configuration data and/or control data and/or diagnostic data.

In a further embodiment of the method, the configuration data and/or the control data and/or the diagnostic data each have, at least temporarily, a bit width that is greater than the number N2 of second data, individually or jointly, wherein the configuration data and/or the control data and/or the diagnostic data are converted into the number N2 of second data according to the type of parallel-serial converter.

The design for this method yields similar advantages to those already described above for the design of the control device.

Drawings

Exemplary embodiments of the present invention are explained below with reference to the accompanying drawings. In the drawings:

fig. 1 shows a first embodiment of a control device having a computing unit and a peripheral unit connected to each other by a serial bus;

fig. 2 shows a second embodiment of a control device having a computing unit and a peripheral unit connected to each other by a serial bus; and

fig. 3 shows a flow chart of a method for operating the control device according to fig. 1 or 2.

The same reference numerals are used for functionally equivalent elements and parameters throughout the drawings even in different embodiments.

Detailed Description

Fig. 1 shows a first embodiment of a control device 10, in particular for a motor vehicle, wherein the control device 10 comprises a computing unit 12 (left in fig. 1) which is designed to periodically transmit data frames 17 via a serial bus 16 to at least one peripheral unit 14 (right in fig. 1) to be actuated by means of control signals. The computing unit 12 is designed to insert first data 22, which characterize the control signal, into each data frame 17. In the present case, the peripheral unit 14 is arranged in the control device 10, wherein the peripheral unit 14 has, in particular, at least one actuating assembly (not shown) for an actuator (not shown).

The computing unit 12 includes a first device 18 to periodically transmit data frames 17 to the peripheral unit 14 over the serial bus 16. Briefly, the device 18 may continuously convert a total number N of periodically deliverable data bits into data frames 17 and serially transmit.

The remaining elements of the control device 10 are not shown together in fig. 1 for simplicity. The control device 10 is correspondingly depicted by means of a dashed box. In one embodiment, the serial bus 16 is a microsecond bus MSC (English: "Micro Second Channel (microsecond channel)").

The computing unit 12 is furthermore designed to insert second data 24 into at least a part of the data frame 17 in addition to the first data 22, wherein in particular the second data 24 comprise configuration data and/or control data and/or diagnostic data. The configuration data and/or control data and/or diagnostic data are currently characterized by the common reference numeral 28.

Here, a first number N1 of data bits of each data frame 17 is allocated to the first data 22, and a second number N2 of data bits of the data frame 17 is allocated at least temporarily to the second data 24, wherein the first number N1 is preferably greater than the second number N2. Illustratively, the first number N1 is equal to 12 and the second number N2 is equal to 4. In one embodiment, the second number N2 is 1. Accordingly, the number N1 can be increased by 3, for example, so that a particularly large number of first data 22 can be transmitted via the serial bus 16 each time (pro Zeit).

Currently, the first data 22 characterizes at least one real-time control signal, in particular at least one pulse width modulated control signal. For example, the pulse width modulated control signals can each be used to control the drive stage of the fuel injector of the internal combustion engine.

The control device 10 has a converter 26 which is designed to generate a second number N2 of second data 24 from the current configuration data and/or control data and/or diagnostic data (reference numeral 28).

In fig. 1, the converter 26 is configured as a parallel-serial converter 26, wherein the configuration data and/or the control data and/or the diagnostic data each have, at least temporarily, a bit width that is greater than the number N2 of the second data 24, individually or jointly. This bit width is illustratively 8 bits in fig. 1. Additionally, the converter 26 is configured for inserting frame information 30a and/or control information 30b for serial transmission into the second data 24. The frame information 30a and the control information 30b are transmitted transparently by the device 18, that is, the devices 18 and 20 do not analyze these information and do not change these information either.

A second device 20 is present in the peripheral unit 14 corresponding to the first device 18 of the computing unit 12 in order to establish again a number N of data bits in parallel by means of data frames 17 periodically transmitted via the serial bus 16. In this case, the information is transmitted by the computing unit 12 to the peripheral unit 14, so that the first and second data 22 and 24 contained in the data frame 17 can again be reproduced in the peripheral unit 14 without errors and explicitly.

For example, this information is transmitted in status bits which are additionally inserted into the data frame 17. In a preferred embodiment, this information is transmitted via additional lines, wherein the data frame 17 preferably comprises only the first and second data 22 and 24, see fig. 2 for this.

For example, the serial bus 16 may include one, two, three or more electrical lines or circuit board traces. The number of lines required or used may depend, inter alia, on the extent to which the serial data of the data frame 17 is encoded. For example, clock signal 36, data signal 42, and optionally a synchronization signal may be required. Reference is now made to fig. 2.

When the data signal 42 comprises in encoded form a clock, data of the data frame 17 and synchronization information or frame information, even a single line may be sufficient for the serial bus 16. In addition, additional bits are required if necessary, which are inserted in the data frame 17 in addition. However such additional bits are not shown together in fig. 1.

A serial-to-parallel converter 32 is arranged in the peripheral unit 14 corresponding to the parallel-to-serial converter 26 of the calculation unit 12. The serial-parallel converter 32 can determine the original configuration data and/or control data and/or diagnostic data again (reference numeral 28 ') from the recovered second data 24' without any errors and with certainty using the frame information 30a and/or the control information 30b. The first data 22' is likewise recovered error-free and unequivocally by means of the second device 20.

Fig. 2 shows a second embodiment of the control device 10. Similar to fig. 1, the computing unit 12 is shown in the left region and the peripheral unit 14 is shown in the right region. The serial bus 16 is shown in the lower middle region of fig. 2.

In the embodiment of fig. 2, the serial bus 16 is a so-called "microsecond bus" (english: MSC, micro Second Channel (microsecond channel)).

A clock generator 34 is arranged in the computing unit 12, which generates a clock signal 36 that clocks a plurality of the elements shown in fig. 2. The clock signal 36 forms, inter alia, a serial shift clock for the shift register 18a of the first device 18. The data frame 17 is periodically generated for transmission to the peripheral unit 14 in case a shift register 18a is used.

Furthermore, the clock signal 36 is divided by a first factor by means of a clock divider 38. The first factor is 16 in the present example and corresponds to the number of bits of the serial shift register 18 a. From this, a divided clock signal 40 is derived which enables, in particular, the first and second data 22 and 24 to be received in parallel into the serial shift register 18 a.

The serial bus 16 of the embodiment of fig. 2 currently includes a clock signal 36 of the clock generator 34, and a clock signal 40 divided by a clock divider 38, and a data signal 42 characterized by a data frame 17, which data signal includes the first data 22 and the second data 24 in succession bit by bit. The current data frame 17 has a number of bits of 16. The divided clock signal 40 simultaneously characterizes synchronization information by means of which the first data 22 and the second data 24 are explicitly recovered in the device 20 of the peripheral unit 14.

In addition, a total of 5 blocks 44a,44b,44c, 44d and 44e are shown in the computing unit 12, which collectively generate or characterize 6 real-time control signals. Currently, the real-time control signals of blocks 44a,44b and 44c are characterized by 3 pulse width modulated control signals, and the real-time control signals of blocks 44d and 44e are characterized by a total of 3 logic signals that should be transmitted to peripheral unit 14.

In the upper left region in fig. 2, the blocks marked with reference number 28 represent corresponding configuration data and/or control data and/or diagnostic data, which can be inserted in parallel into the shift register 26a of the parallel-to-serial converter 26 depicted thereunder. This process is symbolically represented in fig. 2 by the vertical thick arrow. The shift register 26a has, for example, 16 bit positions, wherein the bit length of the shift register 26a can be predefined independently of the bit length of the shift register 18a of the first device 18. Further, the 16 bit positions described above include the frame information 30a and/or the control information 30b already described in fig. 1.

The divided clock signal 40 is supplied as a serial shift clock to the shift register 26a. Thus, the clock frequency of the shift register 26a is currently 1/16 (wird das Schieberegister 26a vorliegend sechzehnmal langsamer getaktet als das Schieberegister 18a der ersten Einrichtung 18) of the shift register 18a of the first device 18.

In the embodiment of fig. 2, configuration data and/or control data and/or diagnostic data are converted into a 1-bit serial form using shift register 26a. The second number N2 (see fig. 1) of second data 24 is accordingly 1. Currently, with respect to the data frame 17 to be transmitted, the second data 14 is inserted into the serial shift register 18a of the first device 18 temporally before the first data 22. Alternatively, however, the second data 24 may be inserted at any bit position in the shift register 18 a.

The computing unit 12 basically transmits three signals to the peripheral unit 14: first, periodically generated data frames 17 of the data signal 42. Second, clock signal 36. Third, the divided clock signal 40.

Due to the synchronization achieved by the divided clock signal 40, the data frame 17 in the embodiment of fig. 2 only comprises data, i.e. the first and second data 22 and 24. Therefore, there is no need to transmit frame information or the like together in the data frame 17.

Similar to the first device 18, the second device of the peripheral unit 14 also comprises a shift register 20a, which also has a number of bits of 16 bits. In the case of using the shift register 20a, the first and second data 22 and 24 can be recovered from the data frame 17 without error and definitely.

Furthermore, the peripheral unit 14 comprises a serial-parallel converter 32 (upper right in fig. 2), by means of which the second data 24 'can be decomposed again into the original configuration data and/or control data and/or diagnostic data (reference numeral 28'). To this end, the second data 24' may be read out from the shift register 20a at a bit position similar to the shift register 18a and written serially into the shift register 32a of the serial-to-parallel converter 32.

The delay between the original first data 22 and the recovered first data 22' is especially small and currently corresponds illustratively at maximum to approximately the length of time of two data frames 17. This characterizes the first data 22 as a so-called "real-time control signal", which can thus also be used for a relatively time-critical control signal.

The possible first part of the delay is characterized by the parallel reception of the first data 22 into the shift register 18 a. The parallel reception takes place periodically by means of a divided clock signal 40, whereby a kind of "sampling" is obtained. Accordingly, the first possible portion of delay is at most approximately the length of time of the data frame 17.

A possible second part of the delay is characterized by the serial shift-out (to the right in fig. 2) of the data signal 42 from the shift register 18 a. After approximately the length of time of the data frame 17, all bits of the data signal 42 are shifted out of the shift register 18a to the right and correspondingly into the shift register 20a of the peripheral unit 14.

The possible third part of the delay is characterized by parallel reception into the shift register 18a and/or parallel transfer from the shift register 20 a. This portion of the delay is relatively small and is at most approximately one or two time periods of the clock signal 36 of the clock generator 34.

The frequency of the clock signal 36 is, for example, 40MHz. It will be readily appreciated that the frequency may have any other value. Also, the bit lengths shown in fig. 1 and 2 of the shift register(s) used respectively are merely exemplary and may likewise have any other value. Likewise, the arrangement (belegungmit) shown in fig. 1 and 2, which characterizes the signals or information of the first data 22 and the second data 24, respectively, is merely exemplary and can also be implemented differently at will.

The operation of the elements of the control device 10 shown in fig. 2 preferably takes place in such a way that: clock generator 34 continuously generates clock signal 36 for the serial shift clocks of shift registers 18a and 20 a. At the same time, clock signal 36 is divided by 16 in clock divider 38. The divided clock signal 40 forms a shift clock for the shift register 26a of the parallel-to-serial converter 26 and for the shift register 32a of the serial-to-parallel converter 32.

In addition, the divided clock signal 40 is used to perform parallel reception of the first and second data 22 and 24 into the shift register 18a every 16 clock steps of the clock signal 36. At the same time, the contents of shift register 26a are shifted further (to the right) by 1 bit in series. Likewise, divided clock signal 40 is used to read out the bits currently present in shift register 20a in parallel every 16 clock steps of clock signal 36 and to store them in parallel for the next 16 clock steps of clock signal 36. For this purpose, the shift register 20a has a corresponding parallel register, which is not shown together in the figures for simplicity.

An additional clock divider, not shown in the figures, again divides the divided clock signal 40 by a second factor to generate a parallel load clock (not shown) for the shift register 26a of the parallel-to-serial converter 26. Just as the first factor characterizes the size of the shift register 18a of the first device 18, the second factor characterizes the size of the shift register 26a accordingly. Currently, the second factor is thus also 16.

In this way, parallel reception of configuration data and/or control data and/or diagnostic data into the shift register 26a is performed every 256 clock steps of the clock signal 36. In the peripheral unit 14, the serial-to-parallel converter 32 accordingly operates in the opposite manner. The second data 24' is read out of the shift register 20a and written serially into the shift register 32a according to the divided clock signal 40.

The load clock (or a similar clock, which is generated in the peripheral unit 14, preferably using the frame information 30a and/or the control information 30 b) used for the shift register 26a of the parallel-to-serial converter 26 is used to currently transfer data currently respectively contained in the shift register 32a in parallel to a parallel register (not shown) arranged in the block 28' every 256 clock steps of the clock signal 36. In this way, the configuration data and/or control data and/or diagnostic data are restored and provided for possible further processing in the peripheral unit 14.

As can be seen, in particular, the first data 22 are transmitted to the peripheral unit 14 continuously in accordance with a time grid (master) of periodically formed data frames 17, wherein no frame-by-frame interruption occurs during the transmission according to the invention. Thus, in particular, the transmission of the first data 22 does not have a time gap. In a similar manner, as long as the second data 24 are present in each case, they are also transmitted without additional delays and/or interruptions, since in principle in each of the data frames 17 both the first data 22 and possibly the second data 24 are transmitted.

In one embodiment of the control device 10, the parallel-to-serial converter 26 and the serial-to-parallel converter 32 each comprise a UART interface, english: "Universal Asynchronous Receiver Transmitter (universal asynchronous receiver transmitter)".

Because the frames ("frames") of the UART interface each begin with a start bit of "0", the receiver UART interface may synchronize with it and identify the frame start. If configuration data and/or control data and/or diagnostic data should not currently be transmitted by means of a UART interface, preferably a "1" bit can be transmitted. Thus, instead of UART interface frame formats, any other frame format or bit sequence may be used, wherein the corresponding frame start is specified by a "0" bit. This is for example advantageous if the standard UART interface (8-bit serial length) is too short.

As long as the transmission capacity is too small for the second data 24 in the case of application, the number N2 is enlarged differently from the value 1 (fig. 2), for example by 2 or 4, see fig. 1. Each clock step of the divided clock signal 40 is utilized to serially shift 1, 2 or 4 bits in the shift registers 26a and 32a according to a corresponding number N2.

Fig. 3 shows a flow chart of a method for operating a control device 10, in particular for a motor vehicle, wherein the control device 10 comprises a computing unit 12 which is designed to periodically transmit data frames 17 via a serial bus 16 to at least one peripheral unit 14 to be actuated by means of control signals. The computing unit 12 inserts first data 22 characterizing the control signal into each data frame 17. The insertion of the first data 22 can thus take place strictly periodically and without interruption in this sense. This is illustrated in fig. 3 by block 100.

In the following block 110, the second data 24 are inserted by the computing unit 12 into at least a part of the data frame 17 in addition to the first data 22, wherein in particular the second data 24 comprise configuration data and/or control data and/or diagnostic data.

The configuration data and/or the control data and/or the diagnostic data have a bit width which is greater than the number N2 of second data 24, respectively, individually or jointly, at least temporarily, wherein the configuration data and/or the control data and/or the diagnostic data are converted into the number N2 of second data 24 according to the type of parallel-serial converter 26. This is illustrated by the following block 120.

In the next block 130, the data frame 17 is transmitted serially to the peripheral unit 14. In the next block 140, the first data 22' are read out from the shift register 20a of the second device 20 in parallel and stored. Meanwhile, the current bit of the second data 24' is serially written into the shift register 32a of the serial-to-parallel converter 32.

In the following block 150, configuration data and/or control data and/or diagnostic data are retrieved from the second data 24' by means of the serial-to-parallel converter 32. Thereafter, the method is continued cyclically at the beginning of block 100.

The steps described in blocks 120 and 150 should be understood symbolically within the following scope: the parallel-to-serial converter 26 and the serial-to-parallel converter 32 operate in part with the clock signal 36 divided by a factor of 256 and accordingly have a slower duty cycle, as already described above.

It will be readily appreciated that the transmission of the first and second data 22 and 24 via the serial bus 16 as described by way of example with the aid of the control device 10 shown in fig. 1 and 2 can also advantageously be performed for virtually any other application.

Claims

1. A control device (10), wherein the control device (10) comprises a computing unit (12) which is configured to periodically transmit data frames (17) via a serial bus (16) to at least one peripheral unit (14) to be manipulated by means of a control signal, characterized in that the computing unit (12) is configured to insert first data (22) characterizing the control signal into each data frame (17), wherein the first data (22) are transmitted to the peripheral unit (14) continuously in accordance with a time grid of periodically formed data frames (17).

2. The control device (10) according to claim 1, wherein the computing unit (12) is configured for inserting second data (24) into at least a portion of the data frame (17) in addition to the first data (22).

3. The control device (10) according to claim 2, wherein the second data (24) comprises configuration data and/or control data and/or diagnostic data.

4. A control device (10) according to claim 2 or 3, wherein a first number (N1) of data bits of each data frame (17) is allocated to the first data (22), and wherein a second number (N2) of data bits of the data frame (17) is allocated at least temporarily to the second data (24).

5. The control device (10) according to claim 4, wherein the first number (N1) is greater than the second number (N2).

6. A control device (10) according to one of claims 1 to 3, wherein the peripheral unit (14) is arranged in the control device (10).

7. The control device (10) according to claim 6, wherein the peripheral unit (14) has at least one actuating assembly for an actuator.

8. A control device (10) according to one of claims 1 to 3, wherein the first data (22) characterizes at least one real-time control signal.

9. The control device (10) according to claim 8, wherein the first data (22) characterizes at least one pulse width modulated control signal (44 a,44b,44 c).

10. The control device (10) according to claim 4, wherein the control device (10) has at least one converter (26) which is configured for generating the second number (N2) of second data (24) from current configuration data and/or control data and/or diagnostic data.

11. The control device (10) according to claim 10, wherein the converter (26) is configured as a parallel-to-serial converter (26), and wherein the configuration data and/or the control data and/or the diagnostic data, respectively, individually or collectively, at least temporarily, have a bit width that is larger than the number (N2) of the second data (24).

12. The control device (10) according to claim 10, wherein the converter (26) is configured for inserting frame information (30 a) and/or control information (30 b) for serial transmission into the second data (24).

13. The control device (10) according to claim 10, wherein the converter (26) comprises a UART interface.

14. A control device (10) according to one of claims 1 to 3, wherein the serial bus (16) is a microsecond bus MSC.

15. A control device (10) according to one of claims 1 to 3, wherein the control device (10) is a control device for a motor vehicle.

16. Method for operating a control device (10), wherein the control device (10) comprises a computing unit (12) which is designed to periodically transmit data frames (17) via a serial bus (16) to at least one peripheral unit (14) to be actuated by means of a control signal, characterized in that the computing unit (12) inserts first data (22) which characterize the control signal into each data frame (17), wherein the first data (22) are transmitted to the peripheral unit (14) continuously in accordance with a time grid of periodically formed data frames (17).

17. The method according to claim 16, wherein a second data (24) is inserted into at least a portion of the data frame (17) by the computing unit (12) in addition to the first data (22).

18. Method according to claim 17, wherein the second data (24) comprises configuration data and/or control data and/or diagnostic data.

19. Method according to claim 18, wherein the configuration data and/or control data and/or diagnostic data, at least temporarily, individually or collectively, respectively, have a bit width that is larger than the number (N2) of second data (24), and wherein the configuration data and/or control data and/or diagnostic data are transformed into the number (N2) of second data (24) according to the type of parallel-to-serial converter (26).

20. The method according to one of claims 16 to 19, wherein the control device (10) is a control device for a motor vehicle.