DE102016219347A1 - Control device, in particular control device for a motor vehicle - Google Patents

Abstract

The invention relates to a control unit (10), in particular for a motor vehicle, wherein the control unit (10) comprises a computing unit (12) which is adapted to periodically frame data (17) to at least one peripheral unit (14) to be controlled by means of a control signal serial bus (16) to transmit. In this case, the arithmetic unit (12) is designed to insert into each data frame (17) first data (22) characterizing the control signal.

Description

State of the art

The invention relates to a control device according to the preamble of claim 1, and a method according to the independent claim.

From the market known control devices for motor vehicles, by means of which a variety of complex control tasks are performed with high computing power. In particular, an exchange of data between different parts of the control unit is required. In the course of a progressive miniaturization or increase in performance, usable space for electrical wiring becomes scarcer and more expensive. A patent publication in this field is, for example, the DE 10 2005 042 493 A1 ,

Disclosure of the invention

The problem underlying the invention is achieved by a control device according to claim 1, and by a method according to the independent claim. Advantageous developments are specified in the subclaims. Features which are important for the invention can also be found in the following description and in the drawings, wherein the features, both alone and in different combinations, can be important for the invention, without being explicitly referred to again.

The invention relates to a control unit, in particular for a motor vehicle, wherein the control unit comprises a computing unit which is designed to periodically transmit data frames to at least one peripheral unit to be controlled by means of a control signal via a serial bus. In this case, the arithmetic unit is designed to insert first data into each data frame which characterize the control signal.

For example, the data frames are generated using an N-bit serial shift register. In this case, the N-bit serial shift register is periodically loaded after each N serial shift clocks in parallel with the first data, which are thus inserted into a respective data frame. The "arithmetic unit" is characterized in the present case by comprising all the means necessary for the formation of the data frame and for its serial transmission. In a broader understanding, the computing unit also includes means for at least partially generating the first data. Likewise, the arithmetic unit may comprise means for generating second data in a manner suitable for serial transmission and for inserting it in the data frame, as will be explained in more detail below. In one embodiment, the arithmetic unit is at least partially a part of a processor core or at least partially a part of a microcontroller.

The invention has the advantage that the first data are continuously transmitted to the peripheral unit in a temporal grid of the periodically formed data frames, wherein frame-by-frame interruptions do not occur during the transmission according to the invention. The transmission of the first data thus has no time gaps. Accordingly, a jitter (clock fluctuations or jitter) characterizing the transmission of the first data can advantageously be minimized. Because of the thus minimized jitter, the first data can thus advantageously be transmitted jointly by means of the serial bus instead of by means of respective electrical connections, whereby lines and thus wiring area can be saved on a printed circuit board. In addition, pins on semiconductor integrated circuits of the controller can be saved or used for other purposes.

In one refinement of the control unit, the arithmetic unit is designed to insert second data in at least one part of the data frames in addition to the first data, wherein in particular the second data comprise configuration data and / or control data and / or diagnostic data. As a result, advantageously, the second data can also be transmitted, wherein the transmission of the first data is in any way additionally delayed, interrupted or otherwise impaired. In particular, this does not cause jitter of the first data. In one embodiment, the arithmetic unit also comprises means for at least partially generating the configuration data and / or control data and / or diagnostic data.

The second data may include, for example, so-called "commands" or any other data which is to be transmitted from the arithmetic unit to the peripheral unit. It is not absolutely necessary that the second data be transmitted continuously. For example, the second data is only temporary (ie in contrast to the first data not in each data frame) and / or only partially present and need only be transmitted accordingly.

Furthermore, the configuration data and / or control data and / or diagnostic data may have an arbitrary structure. For example, these may at least partially be present as parallel data, for example as bytes. Likewise, these can at least partially be present as a plurality of independent individual signals.

In a further embodiment, a first number N1 of data bits of each data frame is associated with the first data, and a second number N2 of data bits of the data frame is at least temporarily associated with the second data, wherein preferably the first number N1 is greater than the second number N2. As a result, the first data in each data frame are transmitted, whereby the first data advantageously has an overall greater transmission capacity with respect to the second data.

In one embodiment, it is provided that the arithmetic unit is designed to differently dimension the number N1 and / or the number N2 in temporally different data frames. For example, a (time-defined) group of data frames may have specific numbers N1 and N2, and a subsequent (time-defined) group of data frames may have different numbers N1 and / or N2 for this purpose. In one embodiment, the numbers N1 and / or N2 may even be different with each data frame. Thereby, a transmission capacity characterized by a bit number of the data frame can advantageously be distributed to the first data and the second data for a respective demand.

In a further embodiment, it is provided that the peripheral unit is arranged in the control unit, wherein the peripheral unit has in particular at least one drive module for an actuator. Thus, the arithmetic unit can advantageously also perform a comparatively time-critical control of actuators via the serial bus. For example, the actuator may be an electromagnetic actuator for an injection valve of an internal combustion engine.

In a further refinement, the first data characterize at least one real-time control signal, in particular at least one pulse-width-modulated control signal. For example, pulse width modulated control signals can be advantageously used to control electromagnetic actuators. The arithmetic unit can transmit these control signals with a comparatively small delay and a comparatively small jitter via the serial bus to the respective control module of the peripheral unit.

According to one embodiment, such a "real-time control signal" is characterized in that a delay and / or a jitter of at most two temporal periods of the data frame can still be tolerated. This will be explained in more detail below.

In a preferred embodiment, the second data does not include such real-time signals. As a result, the second data can be advantageously at least partially serialized, as will be explained in more detail below. As a result, advantageously additional first data can be transmitted in the data frame.

In a further embodiment, the control unit has at least one converter, which is designed to generate the second number N2 of the second data from available configuration data and / or control data and / or diagnostic data. As a result, the configuration data and / or the control data and / or the diagnostic data can be advantageously processed before being inserted into the data frame. For example, it is possible to insert a frame information or other additional information for the second data.

In a further embodiment, the converter is designed as a parallel-serial converter, wherein the configuration data and / or the control data and / or the diagnostic data at least temporarily each alone or together have a larger bit width than the number N2 of the second data. For example, the configuration data and / or the control data and / or the diagnostic data ("data") may exist at least partially as bytes and / or at least partially as a plurality of independent individual signals. Then the said data can be advantageously at least partially serialized. Accordingly, the number N2 of the second data can be reduced and the number N1 of the first data can be increased. In one embodiment, the number N2 is one, thereby "serializing" the said data for transmission as it were.

In a further refinement, the converter or the parallel-to-serial converter is designed to insert frame information and / or control information for the serial transmission into the second data. As a result, the configuration data and / or the control data and / or the diagnostic data can advantageously be identified correctly after the transmission without additional synchronization lines or the like being required.

In a further embodiment, the converter or the parallel-to-serial converter comprises a UART interface, English: "Universal Asynchronous Receiver Transmitter". This allows a particularly advantageous generation of the second data from the configuration data and / or the control data and / or the diagnostic data.

In another embodiment, the serial bus is a microsecond bus, MSC, English: "Micro Second Channel". This allows the specific properties of the microsecond bus are also used for the control unit advantageous.

Furthermore, the invention relates to a method for operating a control device, in particular for a motor vehicle, wherein the control device comprises a computing unit which is adapted to periodically transmit data frames to at least one by means of a control signal to be controlled peripheral unit via a serial bus. In this case, the arithmetic unit inserts in each data frame first data characterizing the control signal. This results in comparable advantages as has already been described above for the control device according to the invention.

In one embodiment of the method, second data are inserted by the arithmetic unit into at least a part of the data frames in addition to the first data, wherein in particular the second data comprise configuration data and / or control data and / or diagnostic data.

In a further embodiment of the method, the configuration data and / or control data and / or diagnostic data at least temporarily, each alone or together on a larger bit width than the number N2 of the second data, wherein the configuration data and / or control data and / or diagnostic data in the manner of a parallel Series converter to the number N2 of the second data.

For the embodiments of the method, comparable advantages result, as has already been described above for the embodiments of the control unit.

Hereinafter, exemplary embodiments of the invention will be explained with reference to the drawings. In the drawing show:

1 a first embodiment of a control device having a computing unit and a peripheral unit, which are interconnected via a serial bus;

2 a second embodiment of the control unit with the computing unit and the peripheral unit, which are interconnected via the serial bus; and

3 a flowchart for a method for operating the controller according to the 1 or 2 ,

The same reference numerals are used for functionally equivalent elements and sizes in all figures, even in different embodiments.

The 1 shows a first embodiment of a controller 10 , in particular for a motor vehicle, wherein the control device 10 an arithmetic unit 12 includes (in 1 left), which is designed to periodically frame data 17 to at least one to be controlled by means of a control signal peripheral unit 14 (in 1 right) via a serial bus 16 transferred to. Here is the arithmetic unit 12 designed to fit into any data frame 17 first data 22 insert, which characterize the control signal. The present is the peripheral unit 14 in the control unit 10 arranged, wherein the peripheral unit 14 in particular at least one drive module (not shown) for an actuator (not shown).

The arithmetic unit 12 includes a first device 18 to periodically change the data frames 17 over the serial bus 16 to the peripheral unit 14 transferred to. Put simply, the device can 18 a total number N of periodically deliverable data bits consecutively into data frames 17 implement and transmit serially.

Other elements of the controller 10 are in for simplicity 1 not shown. The control unit is corresponding 10 drawn by a dashed frame. In one embodiment, the serial bus is 16 a microsecond bus, MSC, English: "Micro Second Channel".

The arithmetic unit 12 is further adapted to at least a part of the data frames 17 in addition to the first data 22 second data 24 in particular the second data 24 Configuration data and / or control data and / or diagnostic data include. The configuration data and / or control data and / or diagnostic data are in the present case by a common reference numeral 28 characterized.

In this case, a first number N1 of data bits of each data frame 17 the first dates 22 and a second number N2 of data bits of the data frame 17 at least temporarily the second data 24 assigned, wherein preferably the first number N1 is greater than the second number N2. By way of example, the first number N1 is twelve and the second number N2 is four. In one embodiment, the second number N2 is one. Accordingly, the number N1 can be increased by three, for example, so that a particularly large amount of first data 22 per time via the serial bus 16 can be transmitted.

In the present case, the first data characterize 22 at least one real-time control signal, in particular at least one pulse width modulated control signal. For example, the pulse width modulated control signals in each case for controlling a Driver stage can be used for an injection valve of an internal combustion engine.

The control unit 10 has a converter 26 which is adapted to the second number N2 of the second data 24 from existing configuration data and / or control data and / or diagnostic data (reference numerals 28 ) to create.

In 1 is the converter 26 as a parallel-serial converter 26 formed, wherein the configuration data and / or the control data and / or the diagnostic data, at least temporarily, each alone or together a larger bit width than the number N2 of the second data 24 exhibit. By way of example, the bit width is in 1 eight bits. In addition, the converter 26 designed to frame information 30a and / or control information 30b for the serial transmission into the second data 24 insert. The frame information 30a and the control information 30b be from the institution 18 transparent, that is, the facilities 18 and 20 do not evaluate this information and do not change it.

According to the first device 18 the arithmetic unit 12 is in the peripheral unit 14 a second device 20 present to via the serial bus 16 periodically transmitted data frames 17 restore the number N of data bits in parallel form. These are from the arithmetic unit 12 Information to the peripheral unit 14 transmitted, causing the in the data frame 17 contained first and second data 22 and 24 again error-free and unique in the peripheral unit 14 can be regenerated.

For example, this information is transmitted in overhead bits which are in the data frame 17 be inserted in addition. In a preferred embodiment, this information is transmitted over additional lines, the data frame 17 prefers only the first and second data 22 and 24 includes, compare to the 2 ,

For example, the serial bus 16 one, two, three or more electrical lines or conductor tracks of a printed circuit board. Amongst others, a number of the required lines may be of a degree of encoding the serial data of the data frame 17 be dependent. For example, a clock signal 36 , a data signal 42 and optionally a sync signal may be required. See below for details 2 ,

Even a single wire can be used for the serial bus 16 be sufficient if the data signal 42 a clock, the data of the data frame 17 , as well as a synchronous information or frame information in coded form. For this purpose, additional bits may be required, which are supplementary in the data frame 17 be inserted. Such additional bits are in the 1 but not shown.

Corresponding to the parallel-serial converter 26 the arithmetic unit 12 is in the peripheral unit 14 a serial-to-parallel converter 32 arranged. The serial-parallel converter 32 can from the recovered second data 24 ' using the frame information 30a and / or control information 30b again the original configuration data and / or control data and / or diagnostic data (reference numerals 28 ' ) error-free and clear. Likewise, the first dates 22 ' by means of the second device 20 error-free and clearly recovered.

The 2 shows a second embodiment for the controller 10 , Comparable to the 1 is the arithmetic unit in a left area 12 and in a right area, the peripheral unit 14 shown. The serial bus 16 is in a lower middle range of 2 shown.

In the embodiment of 2 is the serial bus 16 a so-called "microsecond bus" (MSC, Micro Second Channel).

In the arithmetic unit 12 is a clock generator 34 arranged, which is a clock signal 36 generated, which several of the in 2 clocked shown elements. In particular, the clock signal forms 36 a serial shift clock for a shift register 18a the first device 18 , Using the shift register 18a periodically become data frames 17 for transmission to the peripheral unit 14 generated.

Furthermore, the clock signal 36 by means of a clock divider 38 divided by a first factor. This first factor is sixteen in the present example and corresponds to a bit number of the serial shift register 18a , This results in a split clock signal 40 , which among other things, a parallel transfer of the first and the second data 22 and 24 into the serial shift register 18a allows.

The serial bus 16 the embodiment of 2 in this case comprises the clock signal 36 of the clock generator 34 as well as through the clock divider 38 divided clock signal 40 as well as through the data frame 17 characterized data signal 42 , which is the first data 22 and the second data 24 bitwise one after the other. The data frame indicates here 17 So a bit count of 16 on. The divided clock signal 40 at the same time characterizes a synchronous information, by means of which the first data 22 and the second data 24 in the facility 20 the peripheral unit 14 be recovered clearly.

Furthermore, in the arithmetic unit 12 a total of five blocks 44a . 44b . 44c . 44d and 44e which together generate or characterize six real-time control signals. In the present case are the real-time control signals of the blocks 44a . 44b and 44c characterized by three pulse width modulated control signals, and the real time control signals of the blocks 44d and 44e are characterized by a total of three logic signals which are sent to the peripheral unit 14 to be transferred.

In an in 2 the upper left area is characterized by the reference numeral 28 marked block respective configuration data and / or control data and / or diagnostic data, which in a shift register 26a the subscribed parallel-serial converter 26 can be inserted in parallel. This process is in 2 symbolized by a vertical thick arrow. The shift register 26a shows an example 16 Bit positions on, where one bit length of the shift register 26a independent of a bit length of the shift register 18a the first device 18 can be specified. In addition, the said ones include 16 Bit positions already at 1 described frame information 30a and / or control information 30b ,

The divided clock signal 40 is the shift register 26a supplied as a serial sliding clock. This will make the shift register 26a in the present case clocked sixteen times slower than the shift register 18a the first device 18 ,

In the embodiment of 2 the configuration data and / or control data and / or diagnostic data are obtained using the shift register 26a converted into a one-bit serial form. Accordingly, the second number N2 (see 1 ) of the second data 24 one. The present will be in relation to the data frame to be transmitted 17 the second data 24 time before the first dates 22 into the serial shift register 18a the first device 18 inserted. Alternatively, the second data 24 however, to any bit position in the shift register 18a be inserted.

The arithmetic unit 12 essentially transmits three signals to the peripheral unit 14 First, the periodically generated data frames 17 of the data signal 42 , Second, the clock signal 36 , Third, the split clock signal 40 ,

Thanks to a shared by the clock signal 40 enabled synchronization includes the data frame 17 in the embodiment of 2 only data, ie the first and second data 22 and 24 , Therefore, there is no need for frame information or the like in the data frame 17 to be transmitted with.

Comparable to the first device 18 also includes the second device 20 the peripheral unit 14 a shift register 20a , which also has a bit count of sixteen bits. Using the shift register 20a can the first and the second data 22 and 24 from the data frame 17 error-free and clearly recovered.

Furthermore, the peripheral unit comprises 14 a series-parallel converter 32 (in 2 top right), by means of which the second data 24 ' again in the original configuration data and / or control data and / or diagnostic data (reference numerals 28 ' ) can be disassembled. This can be the second data 24 ' from the shift register 20a at one to the shift register 18a comparable bit position read and in a shift register 32a the serial-to-parallel converter 32 be written serially.

In particular, there is a delay between the original first data 22 and the recovered first data 22 ' small and corresponds in the present example, a maximum of about the length of time of two data frames 17 , This characterizes the first data 22 as so-called "real-time control signals", which can thus also be used for relatively time-critical control signals.

A first possible part of the delay is the parallel adoption of the first data 22 in the shift register 18a characterized. The parallel acceptance takes place periodically by means of the divided clock signal 40 , which results in some sort of "sampling". Accordingly, the first possible fraction of the delay can be up to approximately one temporal length of the data frame 17 be.

A second possible fraction of the delay is due to a serial shift out (in 2 to the right) of the data signal 42 from the shift register 18a characterized. After about a temporal length of the data frame 17 are all bits of the data signal 42 to the right from the shift register 18a pushed out and corresponding to the shift register 20a the peripheral unit 14 pushed into it.

A third possible component of the delay is the parallel transfer to the shift register 18a and / or the parallel transfer from the shift register 20a characterized. This proportion of the delay is comparatively small and amounts to a maximum of approximately one or two time periods of the clock signal 36 of the clock generator 34 ,

A frequency of the clock signal 36 is for example 40 MHz. It is understood that this frequency is also any other value can have. Likewise, those in the 1 and 2 shown bit lengths of the respective shift registers used (several reference numerals) only by way of example and may also have any other value. Likewise, in the 1 and 2 shown occupancy with the first dates 22 and second data 24 respectively characterizing signals or information only as an example and can also be executed in any other way.

An operation of in 2 illustrated elements of the controller 10 is preferably as follows: The clock generator 34 continuously generates a clock signal 36 for the serial shift clocks of the shift registers 18a and 20a , At the same time the clock signal 36 in the clock divider 38 divided by sixteen. The divided clock signal 40 forms the shift clock for the shift register 26a of the parallel-to-serial converter 26 as well as for the shift register 32a the serial-to-parallel converter 32 ,

In addition, the divided clock signal becomes 40 used to every sixteen clock steps of the clock signal 36 a parallel takeover of the first and second data 22 and 24 in the shift register 18a perform. At the same time, the contents of the shift register 26a serially shifted by one bit (to the right). Likewise, the divided clock signal becomes 40 used to every sixteen clock steps of the clock signal 36 in the shift register 20a currently read bits in parallel and for the next sixteen clock steps of the clock signal 36 store in parallel. This is indicated by the shift register 20a a corresponding parallel register, which is not shown in the drawing for the sake of simplicity.

An additional clock divider, not shown in the drawing, divides the divided clock signal 40 again by a second factor, a parallel (not shown) loading clock for the shift register 26a of the parallel-to-serial converter 26 to create. Like the first factor, one size of the shift register 18a the first device 18 characterized characterizes the second factor corresponding to a size of the shift register 26a , In the present case, therefore, the second factor is sixteen.

In this way, every 256 clock steps of the clock signal takes place 36 a parallel transfer of the configuration data and / or control data and / or diagnostic data in the shift register 26a , In the peripheral unit 14 works the series-parallel converter 32 accordingly reversed. The second data 24 ' become dependent on the divided clock signal 40 from the shift register 20a read out and into the shift register 32a written serially.

The one for the shift register 26a of the parallel-to-serial converter 26 Charging clock used (or a comparable clock, which in the peripheral unit 14 preferably using the frame information 30a and / or control information 30b is generated) is used to present all 256 Clock steps of the clock signal 36 a parallel transfer of each currently in the shift register 32a contained data to one in a block 28 ' to allow arranged (not shown) parallel register. In this way, the configuration data and / or control data and / or diagnostic data are retrieved and for any further processing in the peripheral unit 14 provided.

As can be seen, in particular the transmission of the first data takes place 22 continuously in a temporal grid of the periodically formed data frames 17 to the peripheral unit 14 , wherein frame-by-frame interruptions do not occur during the transmission according to the invention. The transmission in particular of the first data 22 has no time gaps. In a similar way, the second data 24 if these are currently present, without any additional delay and / or interruption, because basically in each of the data frames 17 both first data 22 as well as possible second data 24 be transmitted.

In an embodiment of the control device 10 include the parallel-to-serial converter 26 and the serial-to-parallel converter 32 one UART interface each, English: "Universal Asynchronous Receiver Transmitter".

Because a frame of the UART interface begins with a start bit "0", the receiver UART interface can synchronize to it and recognize the beginning of the frame. If currently no configuration data and / or control data and / or diagnostic data to be transmitted by means of the UART interface, preferably "1" bits can be transmitted therein. As a result, as an alternative to a UART interface frame format, it is also possible to use any other frame formats or bit sequences in which a respective frame start is specified by a "0" bit. This is for example advantageous if a standard UART interface (8 bit serial length) should be too short.

If, in one application, a transmission capacity for the second data 24 is too small, the number N2 can deviate from the value one ( 2 ), for example, two or four, compare the 1 , Corresponding to a respective number N2, a serial shift takes place in the shift registers 26a and 32a with every clocking step of the divided clock signal 40 by one, two or four bits.

The 3 shows a flowchart for a method for operating a control device 10 , in particular for a motor vehicle, wherein the control device 10 the arithmetic unit 12 which is adapted to periodically frame data 17 to at least one to be controlled by means of a control signal peripheral unit 14 over the serial bus 16 transferred to. The arithmetic unit adds 12 in every data frame 17 first data 22 which characterize the control signal. The insertion of the first data 22 can therefore be strictly periodic and in this sense without interruption. This is in 3 through the block 100 shown.

In a following block 110 be through the arithmetic unit 12 in at least part of the data frames 17 in addition to the first data 22 second data 24 in particular the second data 24 Configuration data and / or control data and / or diagnostic data include.

In this case, the configuration data and / or control data and / or diagnostic data at least temporarily, each alone or together, a larger bit width than the number N2 of the second data 24 on, wherein the configuration data and / or control data and / or diagnostic data in the manner of the parallel-serial converter 26 to the number N2 of the second data 24 be implemented. This is through a following block 120 shown.

In a following block 130 becomes the data frame 17 serial to the peripheral unit 14 transfer. In a following block 140 become the first data 22 ' from the shift register 20a the second device 20 read in parallel and saved. At the same time, a current bit of the second data 24 ' serial into the shift register 32a the serial-to-parallel converter 32 written.

In a following block 150 the configuration data and / or control data and / or diagnostic data by means of the serial-parallel converter 32 from the second data 24 ' recovered. After that, the procedure is at the beginning of the block 100 cyclically continued.

The in the blocks 120 and 150 described steps are to be understood as symbolic, as the parallel-serial converter 26 and the serial-to-parallel converter 32 partly with the clock signal divided by a factor of 256 36 be operated and accordingly have a slower duty cycle, as already described above.

It is understood that the transmission of first and second data 22 and 24 over a serial bus 16 , as exemplified by means of in the 1 and 2 shown control unit 10 has been described, can also be advantageously carried out for almost any other applications.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102005042493 A1 [0002]

Claims (13)

Control unit ( 10 ), in particular for a motor vehicle, wherein the control device ( 10 ) a computing unit ( 12 ), which is adapted to periodically frame data ( 17 ) to at least one to be controlled by means of a control signal peripheral unit ( 14 ) via a serial bus ( 16 ), characterized in that the arithmetic unit ( 12 ) is designed to fit into each data frame ( 17 ) first data ( 22 ) which characterize the control signal. Control unit ( 10 ) according to claim 1, wherein the arithmetic unit ( 12 ) is designed to be integrated into at least part of the data frames ( 17 ) in addition to the first data ( 22 ) second data ( 24 ), in particular the second data ( 24 ) Comprise configuration data and / or control data and / or diagnostic data. Control unit ( 10 ) according to claim 2, wherein a first number (N1) of data bits of each data frame ( 17 ) the first data ( 22 ), and wherein a second number (N2) of data bits of the data frame ( 17 ) at least temporarily the second data ( 24 ), and wherein preferably the first number (N1) is greater than the second number (N2). Control unit ( 10 ) according to claim 1 to 3, wherein the peripheral unit ( 14 ) in the control unit ( 10 ), wherein the peripheral unit ( 14 ) in particular has at least one drive module for an actuator. Control unit ( 10 ) according to one of claims 1 to 4, wherein the first data ( 22 ) at least one real-time control signal, in particular at least one pulse-width-modulated control signal ( 44a . 44b . 44c ) characterize. Control unit ( 10 ) according to one of claims 2 to 5, wherein the control device ( 10 ) at least one converter ( 26 ), which is adapted to the second number (N2) of the second data ( 24 ) to generate from existing configuration data and / or control data and / or diagnostic data. Control unit ( 10 ) according to claim 6, wherein the converter ( 26 ) as a parallel-to-serial converter ( 26 ), and wherein the configuration data and / or the control data and / or the diagnostic data at least temporarily each alone or together a larger bit width than the number (N2) of the second data ( 24 ) exhibit. Control unit ( 10 ) according to claim 6 or 7, wherein the converter ( 26 ) is adapted to provide frame information ( 30a ) and / or control information ( 30b ) for the serial transmission into the second data ( 24 ). Control unit ( 10 ) according to one of claims 6 to 8, wherein the converter ( 26 ) includes a UART interface, English: "Universal Asynchronous Receiver Transmitter". Control unit ( 10 ) according to at least one of the preceding claims, wherein the serial bus ( 16 ) is a microsecond bus, MSC, English: "Micro Second Channel", is. Method for operating a control device ( 10 ), in particular for a motor vehicle, wherein the control device ( 10 ) a computing unit ( 12 ), which is adapted to periodically frame data ( 17 ) to at least one to be controlled by means of a control signal peripheral unit ( 14 ) via a serial bus ( 16 ), characterized in that the arithmetic unit ( 12 ) in each data frame ( 17 ) first data ( 22 ) which characterize the control signal. Method according to claim 11, wherein the arithmetic unit ( 12 ) in at least part of the data frames ( 17 ) in addition to the first data ( 22 ) second data ( 24 ), in particular the second data ( 24 ) Comprise configuration data and / or control data and / or diagnostic data. The method of claim 12, wherein the configuration data and / or control data and / or diagnostic data at least temporarily, each alone or together a larger bit width than the number (N2) of the second data ( 24 ), and wherein the configuration data and / or control data and / or diagnostic data in the manner of a parallel-to-serial converter ( 26 ) to the number (N2) of the second data ( 24 ) are implemented.

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