EP0232886B1 - Frame decoding - Google Patents

Abstract

A method and apparatus for frame decoding, in a system which has a series bit data flow with a frame structure including a periodically occurring item of synchronizing information which characterizes the start of each frame, uses a synchronizing bit as synchronizing information. A logic AND-link is perfomed, with data in successive search frames until only one bit, the synchronizing bit, in the search frame is set at logic "1" and this setting is retained for a plurality of search frames. A synchronizing signal, corresponding to the time position of the synchronizing bit, is generated and the bit flow and/or the synchronizing signal are delayed so that the synchronizing signal occurs in synchronism with a delayed bit flow.

Description

The invention relates to a method for frame decoding according to the preamble of patent claim 1.

A frame synchronization is known from US Pat. No. 4,002,845, in which the corresponding bits of two successive frames are compared. If these two bits have different values, an identifier bit is written to the corresponding position in a shift register. With this identification bit and the identification bit from the following comparison, an AND operation is carried out. Only an identifier bit with the value 1 in the shift register identifies the position of the synchronization bit.

Digital signal devices are being used to an increasing extent in transmission technology, in particular via microwave links. Such devices require a multiplexer-demultiplexer device with a so-called superframe structure for the additional transmission of information bits for service channel and reporting purposes.

In the publication "Multiplexer for 8.448 Mbit / s with positive-negative tamping technology" by U. Aßmus and others (see message from the research institute of the FTZ of the German Bundespost in Darmstadt, published in Telecommunications Technical Reports 42 (1972), pp. 245-256 ) the following is carried out. The combination of several basic PCM systems into a second-order system for the more economical transmission of digital signals over longer distances will make sense as a preliminary stage of a digital network and can be solved by multiplexers without transmission losses. Since a synchronous digital network cannot be expected in the near future, the asynchronous multiplexer should last for a longer transition period from Be meaningful. The multiplexer with "positive-negative" stuffing technique seems to have a special meaning among the asynchronous multiplexers. In the receiving part of the multiplexer-demultiplexer system, synchronism between the transmitter and receiver is established in a synchronization device. For this purpose, a periodically recurring synchronization word is transmitted in the bit stream in the usual way. By the Synchronization word, the bit stream is given a frame structure, the beginning of each frame being marked by the synchronization word.

As described in the description of the digital signal multiplex device DSMX8 / 34 from Siemens, a frame identifier consisting of 10 bits is used here at the beginning of the pulse frame. In the frame synchronization circuit, a shift register is shifted relative to the bit stream until the frame identification word is recognized by a logic logic at the outputs of the shift register.

The invention is based on the object of specifying a method for frame decoding in the case of a digital directional radio, which also enables rapid and reliable synchronization of the receiving device in the event of so-called tuft interference on the transmission link.

This object is achieved by the features specified in claim 1.

Cyclic pulse disturbances can cause total failures of entire power supplies. The effects of such disruptions are not that serious for postal networks, since they are resynchronized in about 1-2 ms. With encrypted transmission, however, resynchronization of the key devices takes approx. 50-100 ms.

Immunity to interference is improved by the method according to the invention, since a bit as synchronization information is falsified less often than a frame identification word.

Characterized in that the circuit arrangement according to the invention does not generate a new synchronization signal during the search process and / or the lack of the synchronization bit, but rather the new synchronization signal only after a predetermined one If the number of correctly recognized synchronization bits is output, the interference immunity against incorrect synchronization is improved. During the search process, in particular in the event of interference, the synchronization signal once generated is passed on unchanged.

The invention is described in more detail below with reference to an embodiment shown in the drawing. Show

1 is a block diagram of the circuit arrangement for frame decoding,

Fig. 2 shows the circuit arrangement for frame decoding, and

3 and 4 pulse diagrams for explaining the circuit arrangement for frame decoding.

1 shows a signal source SQ which gives a bit stream BS to a serial-parallel converter stage SPS. The signal source SQ can be the receiving part of a demultiplexer, for example. The serial-parallel converter stage SPS generates a parallel bit word BW from the serial bit stream BS, which bit consists of bits B1, B2, Bn.

Bits B1 to Bn are each present at the one input of AND logic elements, which are not described in more detail. The outputs of the AND logic elements are connected to storage locations SPL. The memory locations SPL can be part of a read-write memory, for example. The outputs of the memory locations SPL are connected to inputs of an exclusive-OR logic element, not specified, with inputs of a parallel-serial converter stage PSS, and in each case to another input of the assigned AND logic elements. The connection of a time switch stage ZS is connected via decoupling diodes to the other inputs of the AND logic elements.

At the beginning of the decoding process, the other inputs of the AND logic elements are supplied with a logic "1" by the time switching stage ZS, so that bits B1, B2, ... Bn, i.e. the bit word BW output by the serial parallel converter stage PLC is written into the memory locations SPL. During the decoding process, bits B1 to Bn of the mth bit word BW in the memory locations SPL are linked to bits B1 to Bn of the subsequent (m + 1) th bit word BW via the AND logic elements. The invention is based on the idea that the bits of the m-th bit word BW set to logic “0” in the memory locations SPL set the corresponding bits of the (m + 1) -th bit word BW to logic “0”, and these to logic "0" set bits of the (m + 1) th bit word BW are written into the memory locations SPL. Logical ones on bits of the mth bit word in the memory locations SPL are overwritten by logical zeros of the corresponding bits of the (m + 1) th bit word BW.

The result, which can be removed at the outputs of the AND logic elements, is continuously written into the memory locations SPL. During the decoding process, only that of bits B1 to Bn of bit word BW in memory locations SPL remains at logic "1", which always has a logic "1" at the output of the serial-parallel converter stage PLC. This bit is the synchronization bit S, which by definition is implemented by a periodically recurring logic "1" in the bit stream BS.

If in a bit word BW in the memory locations SPL only one of the bits B1 to Bn still has a logical "1", then the exclusive-OR logic element sends a signal to a switching input of the parallel-serial converter stage PSS, which is not specified in any more detail. This converts the bit word BW in the memory locations SPL into a serial bit sequence. This bit sequence is a synchronization signal SS. The bit stream BS is converted in a first delay stage VS1 into a delayed bit stream VBS for time adaptation to the synchronization signal SS. The delay time of the first delay stage VS1 and / or the delay time of a second delay stage VS2, which provides for a delay of the synchronization signal SS, are selected so that the synchronization bit S occurs in the delayed bit stream VBS simultaneously with the synchronization signal SS.

FIG. 2 again shows the signal source SQ known from FIG. 1, which gives the likewise known bit stream BS with the synchronization bit S to an input D0 of a serial-parallel converter SPW. A clock generator TG supplies a clock pulse sequence T0 to the clock inputs of the serial-parallel converter SPW and a clock and address processing stage TA. The clock and address preparation stage TA emits first to third clock drive pulses Q1, Q2, Q3, first to fourth clock pulse sequences T1, T2, T3, T4, and cyclically an address AD and a previous address VAD. The clock drive pulses Q1 to Q3 each have half the frequency compared to the previous clock drive pulses, the first clock drive pulses Q1 having half the frequency as the clock pulse train T0.

In the serial-parallel converter SPW, which is implemented, for example, by an eight-stage shift register, the serial bit stream PS is continuously broken down into 8-bit wide bit words BW. It is assumed here that the frame length in the bit stream BS, i.e. the number of bits between two synchronization bits S plus the synchronization bit S is a multiple of eight.

This 8-bit wide bit word BW is emitted by an output QA of the serial-parallel converter SPW and is present an input D of a first delay flip-flop VF1. The first clock pulse sequence T1 is present at the clock input of the first delay flip-flop VF1. An output Q of the first delay flip-flop VF1 outputs an (m + 1) -th bit word BW to an input E of a memory chip SP, to an input D of a second delay flip-flop VF2, and to an input, which is not described in more detail an exclusive OR logic element EOD1. The fourth clock pulse sequence T4 is applied to a control input SE of the exclusive OR logic element EOD1 via a second OR logic element OD2.

The mth bit word BW emitted by an output A of the memory chip SP is applied to a reset pulse input R of the first delay flip-flop VF1. The second clock pulse sequence T2 is present at a read / write command input SL of the memory chip SP. The memory module SP, which contains the memory locations SPL known from FIG. 1, is implemented, for example, by a so-called RAM module. The third clock pulse sequence T3 is applied to an output control input AS of the memory chip SP via a first OR gate OD1.

The address AD output by the clock and address processing stage TA is present at an address input AE of the memory chip SP, at a first input E1 of a first comparator stage V1, and at a first input E1 of a second comparator stage V2. The previous address VAD is present at an input D of a first register RG1, the clock input of which is connected to an output A of the exclusive OR logic element EOD1. An output Q outputs the content of the first register RG1 to a second input E2 of the first comparator stage V1 and to an input D of a second register RG2. One output Q gives the content of the second Register RG2 to a second input E2 of the second comparator stage V2. The comparator stages V1 and V2 each emit a pulse at their outputs if the same addresses are present at their first and second inputs E1, E2.

The output A of the first comparator stage V1 is connected to clock inputs of a counter Z, a fifth, a sixth and a seventh delay flip-flop VF5, VF6, VF7 via a divider stage TE, which has, for example, a division ratio of 2 to 1. An output A of the counter Z, which outputs a signal after a predetermined number of pulses at the clock input, is connected to clock inputs of the second register RG2 and the second delay flip-flop VF2. A reset pulse input R of the fifth delay flip-flop VF5 is connected via a second inverter I2 to the output A of the exclusive OR gate EOD1.

An output Q of the second delay flip-flop VF2 outputs the (m + 1) -th bit word BW to an input E of a parallel-serial converter PSW, to whose control inputs (not shown in more detail) the clock drive pulses Q1 to Q3 are applied. An output A of the parallel-serial converter PSW is connected to an input of an AND gate UD1, at the other input of which the output A of the second comparator stage V2 is connected.

The clock pulse sequence TO output by the clock generator TG is applied to the clock inputs of a third and a fourth delay flip-flop VF3, VF4 via a first inverter I1. The third delay flip-flop VF3 has an input D, to which an output A of the AND gate UD1 is connected, and an inverting output Q , from which the synchronization signal SS is emitted. The fourth delay flip-flop VF4 has one Input D, which can be connected to one of the inputs D1 to D7 of the serial-parallel converter SPW, and an output Q, from which the delayed bit stream VBS is emitted. The inputs D1 to D7 of the serial-parallel converter SPW are the higher seven inputs of the eight-stage shift register, or the lower seven outputs of the individual stages.

The fifth delay flip-flop VF5 has an input D, to which a logic "1" is present, and an output Q, which is connected to an input D of the sixth delay flip-flop VF6. An output Q of the sixth delay flip-flop VF6 is connected to an input of an inverting AND gate UD2, to an input of the first OR gate OD1, and to an input of the second OR gate OD2. An inverted output Q of the sixth delay flip-flop VF6 is connected to a reset pulse input R of the counter stage Z.

The third clock pulse sequence T3 is present at the other input of the first OR logic element OD1, the output of which is connected to the output control input AS of the memory chip SP. The fourth clock pulse sequence T4 is present at the other input of the second OR logic element OD2, the output of which is connected to a control input SE of the exclusive OR logic element EOD1. The third or fourth clock pulse sequence T3, T4 can be masked out by a logic "1" at the one inputs of the OR logic elements OD1 and OD2.

The output Q of the sixth delay flip-flop VF6 is also present at an input D of the seventh delay flip-flop VF 7, the output Q of which is present at the other input of the inverting AND gate UD2. The output of the inverting AND gate UD2 is connected to a reset pulse input R of the sixth delay flip-flop VF6.

All clock inputs of the blocks shown in FIG. 2 are triggered with a rising edge. The reset pulse inputs R of the delay flip-flops VF1 to VF7 and the control input SE of the exclusive OR gate EOD1 are active at a logic "0". A logical "0" at the output control input AS of the memory chip SP outputs the mth bit word BW at its output A. With a logical "1" at the output control input AS, the output A is switched to high impedance, i.e. the output of data is blocked.

The circuit parts shown with broken lines in Fig. 2 will be described later.

FIGS. 3 and 4 show impulses or states at some connections of the components shown in FIG. 2. The line or the signal on the associated line is given in each line and the associated block in brackets.

The mode of operation of the circuit arrangement for decoding shown in FIG. 2 is explained below with reference to the signals shown in FIGS. 3 and 4.

A serial bit stream BS is emitted from the signal source SQ. The bit stream BS has the synchronization bit S at one point, by which the start of a frame is identified. 3, the synchronization bit S is within an (m + 1) th search frame SR. The search frame SR contains as many bits as the frame, for example 1080 bits. The start of the search frame SR is arbitrarily determined by the switch-on time of the circuit arrangement for frame decoding.

The bit stream BS is converted by the serial-parallel converter SPW into 8-bit wide bit words BW. 3, eight consecutive bits are identified by the numbers 0 to 7. It is assumed that bit no. 1 has a logical "0" and bits no. 3 and 5, where bit no. 5 is the synchronization bit S, each have a logical "1".

The clock pulse sequence T0 is emitted by the clock generator TG. Successive clock edges of the clock pulse sequence T0 are identified with periodic times t0 to t16. The time t16 corresponds to the time t20 of the next period. Bit No. 0 is scanned at time t1 with a rising edge of the clock pulse sequence T0.

The clock pulse sequences T1 to T4 are emitted by the clock and address preparation stage TA. The first clock pulse train T1 has a logic "0" between times t0 and t1, otherwise a logic "1". The second clock pulse sequence T2 has a logic "1" between times t0 and t8 and a logic "0" between times t8 and t16. The third clock pulse sequence T3 has a logic "0" between times t4 and t8, and a logic "1" between times t8 and t24. The fourth clock pulse sequence has a logic "1" between times t0 and t12 and a logic "0" between times t12 and t16. The shape of the clock pulse sequences T1 to T4 is repeated periodically.

The address AD is given by the clock and address preparation stage TA. The address AD is changed at times t0 and t16 or t20. Between times t0 and t16 the address AD = x-1, and between times t20 and t36 the address AD = x given. In the mentioned case with 1080 bits in the frame, 135 addresses AD (1080: 8 = 135) from AD = 0 to AD = 134 are output, which are formed cyclically by the clock and address preparation stage TA.

The bit word BW output by the serial-parallel converter SPW is present at input D of the first delay flip-flop VF1. The bits of the bit stream BS with the numbers 0 to 7 are contained in the bit word BW with the number m + 1. The number of the bit word BW here refers to the number of the search frame SR, which are identical to one another. The mth bit word BW is located in the same place in the m th search frame SR as the (m + 1) th bit word BW in the (m + 1) th search frame SR. These positions are marked by the addresses AD.

From time t21, this bit word BW with the number m + 1 can be tapped at the output Q of the first delay flip-flop VF1. From the time t20, the address AD = x is present at the address input AE of the memory chip SP. Also from time t20, a logic "1" from the second clock pulse sequence T2 is present at the read / write command input SL of the memory module SP, whereby the memory module SB is prepared for reading out data. A state is considered here in which, from time t24, a logic "0" from the third clock pulse sequence T3 is present at the output control input AS of the memory chip SP, i.e. the first OR gate OD1 switches through the third clock pulse sequence T3 unchanged. This has the effect that from time t24 the bit word BW addressed by the address AD = x can be tapped at the output A of the memory chip SP. In Figure 3, this bit word BW has the number m.

The mth bit word BW is therefore present at the reset pulse input R of the first delay flip-flop VF1 from the time t24. This causes the at the output Q of the first delay flip-flop VF1 (m + 1) th bit word BW, only the bits are not set to logic "0", in their place a logical "1" is in the m th bit word BW. As already explained in the description of the basic principle of the invention with reference to FIG. 1, there is a logical AND combination (conjunction) of the m th bit word BW with the (m + 1) th.

After the logical AND operation, the result is written as (m + 1) th bit word BW into the memory location with the address AD = x. This is caused by the logic "0" of the second clock pulse sequence T2 from the time t28 on the read / write command input SL, and the address AD = x still present at the address input AE.

The logical AND combination of the mth with the (temporally) subsequent (m + 1) th bit word BW is carried out analogously for all bit words BW for the addresses AD = 0 to AD = 134. In this way, the entire search frame SR is searched for the synchronization bit S, which as the only bit always has a logical "1".

The (m + 1) th bit word BW written into the memory module SP at time t28 is also present at the inputs of the exclusive OR logic element EOD1. If, as in the numerical example chosen in FIG. 3, the (m + 1) -th bit word BW has only one bit occupied with a logic “1” (see bit number 5, the synchronization bit S in FIG. 3) , then a positive pulse is emitted from output A of the exclusive OR logic element EOD1. The rising edge of this pulse at a time t32 is determined by the fourth clock pulse sequence T4 present at the control input SE of the exclusive OR logic element EOD1, which has a logic "0" from this time t32. A state is considered in which the second OR logic element OD2 switches through the fourth clock pulse sequence T4 unchanged.

With the help of the exclusive-OR logic element EOD1, it was found that in one of the bit words BW only one bit space is occupied with a logical "1". It must now be determined whether the (m + 1) th bit word BW is the only bit word BW within a search frame SR that has a bit space occupied with a logical "1". This is determined using the first register RG1 and the first comparator stage V1 using the previous address VAD.

As shown in FIG. 4, the address AD = x or y and the previous address VAD = x-1 or y-1 are output side by side within a search frame SR by the clock and address preparation stage TA. The positive pulses emitted by the output A of the exclusive OR logic element EOD1 at times t32 and t52 have the effect that the previous address VAD = x-1 is transferred to the first register RG1 at these times t32, t52. From time t32, the previous address VAD = x-1 can therefore be tapped at the output Q of the first register RG1.

In a first case, in which the (m + 1) -th bit word BW with the address AD = x in the search frame SR with the number n is the only bit word with a bit space occupied only with a logical "1", there are from one Time t60 at the first comparator stage V1 to two identical addresses. At its first input E1 the address AD = x-1 from the clock and address preparation stage TA, and at its second input E2 the previous address VAD = x-1 from the output Q of the first register RG1. This has the effect that the first comparator stage V1 on their Output A emits a positive pulse that lasts until the next change of address. It is pointed out that any address preceding the address AD = x can be used as the previous address VAD. To adapt the synchronization signal SS to the delayed bit stream VBS, the preceding address VAD = x-1, which is directly in front of the address AD = x, is particularly well suited. It is also conceivable to use an address after the address AD = x as the previous address VAD.

In a second case, in which the (m + 1) th bit word BW with the address AD = x in the search frame with the number n is not the only bit word BW with only one bit space occupied with a logical "1", for example at an unspecified point in time, the previous address VAD = y-1 is transferred to the first register RG1. In this case, an (m + 1) -th bit word BW with only a logical "1" was found. This bit word BW belongs to the address AD = y. Since the address AD = x-1 emitted by the clock and address processing stage TA is present at the first input E1 of the first comparator stage V1, the previous address VAD = y-1 is present at the second input E2 of the first comparator stage V1. the first comparator stage V1 does not give a pulse to its output A. The same applies to the period of time during which the address AD = y-1 given by the clock and address preparation stage TA at the first input E1 of the first comparator stage V1 and the previous address VAD = x- in the second input E2 at the second input E2. 1 concern.

The pulses emitted by the output A of the first comparator stage V1 are divided down in a divider stage TE, for example in a ratio of 2 to 1, and passed to the clock input of the counter Z. After, for example, thirty pulses at output A of the first comparator stage V1, ie after fifteen pulses at the clock input of the counter Z, the counter Z outputs a pulse at its output A, by which the clock input of the second register RG2 is triggered. With this pulse, the previous VAD that can be tapped at the output Q of the first register RG1 is transferred to the second register RG2. After this pulse, the previous address VAD is thus applied from the output Q of the second register RG2 to the second input E2 of the second comparator stage V2.

The counter Z serves to increase the interference immunity of the circuit arrangement according to the invention for frame decoding. Only after repeated recognition of a single bit with a logical "1" in a bit word BW, and after recognition of a single such bit word BW in a search frame SR, is this bit identified as synchronization bit S.

From a time t80, the address AD = x-1 given by the clock and address preparation stage TA is at the first input E1 of the second comparator stage V2, and the previous address VAD = x-1 stored in the second register R2 at the second input of the second comparator stage V2 at. From time t80, the second comparator stage V2 emits a positive pulse at its output A. This impulse lasts until the next change of address.

In the following, FIG. 3 will be used again to explain the circuit arrangement shown in FIG. 2. At a time t70, a positive pulse is emitted from output A of counter Z. This pulse is also present at the clock input of the second delay flip-flop VF2, which takes over the (m + 1) th bit word BW at this time. This bit word BW is from the output Q of the second delay flip-flop VF2 given to the input E of the parallel-serial converter PSW. The parallel-to-serial converter PSW now forms from the bits with the numbers 0 to 7, with bit 5 being the synchronization bit S, a serial bit sequence of the bits with the numbers 0 to 7. This bit sequence, which is indicated by a positive, the synchronization bit S corresponding pulse is identified, is output periodically from the output A of the parallel-serial converter PSW to the AND gate UD1.

The bit sequence emitted by output A of the parallel-serial converter PSW is shown again in FIG. 4.
A time window is predefined by the pulse which is also present at the AND logic element UD1 and is output by the output A of the second comparator stage V2.

This time window selects one of the periodic pulses that can be tapped at the output A of the parallel-series converter PSW and that can be tapped at the output A of the AND logic element UD1 as a synchronization signal SS.

The delayed bit stream VBS is generated via the fourth delay flip-flop VF4. The period of time by which the delayed bit stream VBS is delayed compared to the bit stream BS is, on the one hand, by the choice of the time difference between the delivery of the address AD and the previous address VAD by the clock and address processing stage TA, and on the other hand by the optional connection of the input D of the fourth delay flip-flop VF4 adjustable to one of the inputs D1-D7 of the serial-parallel converter SPW. For this purpose, the fourth delay flip-flop VF4 is triggered by the falling edges of the clock sequence TO.

The third delay flip-flop VF3 is also triggered by the falling edges of the clock pulse sequence T0. Via the third delay flip-flop VF3 the synchronization signal SS emitted by the output A of the AND logic element UD1 is synchronized with the falling edges of the clock pulse sequence T0, and is thus synchronous with the synchronization bits S in the delayed bit stream VBS.

The beginning of the frame decoding and the behavior of the circuit arrangement according to the invention in the event of loss of the synchronization bit S, for example due to a fault, are described below.

After switching on the circuit arrangement according to the invention for frame decoding to a power supply, the first register RG1 contains a randomly adopted previous address VAD = x-1. If the address AD = x-1 is given by the clock and address processing stage TA, a pulse is given by the output A of the first comparator stage V1. After each such second pulse, due to the divider stage TE operating in a ratio of 2 to 1, the logic "1" present at the input D of the fifth delay flip-flop VF5 is switched through to its output Q. This logic "1" is now present at input D of the sixth delay flip-flop VF6. After a further two pulses at the output A of the first comparator stage V1, this logic “1” is switched through to the output Q of the sixth delay flip-flop VF6. Due to the logic "1" which can be tapped at the output Q of the sixth delay flip-flop VF6 and which is present at the one inputs of the OR logic elements OD1 and OD2, the third clock pulse sequence T3 are from the output control input AS of the memory chip SP and the fourth clock pulse sequence T4 from Control input SE of the exclusive OR logic element EOD1 separated. As already described, these two last-mentioned control inputs are active when a logic "0" is present.

As long as a logic "1" appears at the output Q of the sixth delay flip-flop VF6, it is or remains via its inverting output Q the counter level Z is reset.

The time interval at which the pulses occur at the output A of the first comparator stage V1 each correspond to a frame length of the serial bit stream BS. The logic "1" which can be tapped at the output Q of the sixth delay flip-flop VF6 is also present at the input D of the seventh delay flip-flop VF7. After two further pulses at output A of the first comparator stage V1, i.e. after two frame lengths, the logic "1" is switched through from the output D to the output Q of the seventh delay flip-flop VF7 and to the other input of the inverting AND gate UD2, at the one input of which is also the output Q of the sixth Delayed flip-flops VF6 applied logic "1" is present. This ensures that the memory chip SP is loaded over two frame lengths with bit words BW output by the serial-parallel converter SPW via the first delay flip-flop VF1.

After these two frame lengths, a logical "0" is given to the reset pulse input R of the sixth delay flip-flop VF6 via the inverting AND gate UD2, at the two inputs of which a logic "1" is now present, and thereby the output Q thereof logically set to "0". This has the effect that the third clock pulse sequence T3 controls the output control input AS of the memory chip SP, and the fourth clock pulse sequence T4 controls the control input S of the exclusive OR logic element EOD1. During the decoding process, the exclusive OR logic element EOD1 repeatedly registers bit words BW within a search frame SR, which are only one with a logical "1" bit without this bit being the synchronization bit S. As a result, a plurality of pulses are emitted from the output A of the exclusive-OR logic element EOD1 within a search frame SR, which are given via the second inverter I2 to the reset pulse input R of the fifth delay flip-flop VF5. As a result, the output Q of the fifth delay flip-flop VF5 is set to logic "0", so that switching through of the logic "1" applied to its input D is prevented.

If, as has already been described, the synchronization bit S was found in the bit stream BS, only a pulse is emitted from the output A of the exclusive OR logic element OD1 within a search frame SR. In the memory module SP, only one of the addressed memory locations is occupied with a logical "1", namely the one in which the synchronization bit S was written. If, for example, this synchronization bit S is lost due to interference on the transmission link, i.e. If the logic "1" of the synchronization bit S is set to logic "0", the associated memory location in the memory chip SP is also overwritten with logic "0". As was described in the description of the mode of operation of the circuit arrangement according to the invention for decoding, during the decoding process, logic ones in the memory module SB can be overwritten by logic zeros at its input E on bit locations of the (m + 1) th bit word BW.

Since there are now only logical zeros in the addressed memory locations in the memory module SP, no more pulses are emitted from the output A of the exclusive OR gate EOD1, and the fifth delay flip-flop VF5 is no longer reset. As already described during the switch-on process, the first comparator stage V1 is now output due to output A First the output Q of the fifth delay flip-flop VF5, and then after two further pulses the output Q of the sixth delay flip-flop VF6 is set to logic "1", and thereby the bits of the serial bit stream are written for two frame lengths BS, ie the associated bit words BW in the memory chip SP. The output A of the first comparator stage V1 still emits pulses because the first register RG1 contains a previous address VAD = x-1, which within each search frame also contains the address AD = x-1 from the clock and address preparation stage TA is delivered.

The time switching stage ZS shown in FIG. 1 is formed in the circuit arrangement shown in FIG. 2 by the fifth to seventh delay flip-flop VF5-VF7 in connection with the output A of the first comparator stage V1.

The blocks drawn in broken lines in FIG. 2 and their connections and their mode of operation are explained below. It is assumed here that the serial bit stream BS is not converted into eight-bit bit words BW, but into two four-bit bit words.

In the following example, the eight bits of the bit word BW are not output from the output QA of the serial-parallel converter SPW, as described above, but from the output QA the first four bits of the bit word BW are output as a first half-word BWA, and from an output QB of the serial-parallel converter SPW the second four bits of the bit word BW are output as the second half-word BWB. Via a multiplexer MX, the first half-word BWA is sent as bit word BW in a first switching state and the second half-word BWB is sent to input D of the first delay flip-flop VF1 in a second switching state as bit word BW given. As already explained, the bit word BW in this example is four bits wide, and the inputs D of the first and second delay flip-flops VF1, VF2, the reset pulse input R of the first delay flip-flop VF1, have a corresponding number of connections. input E and output A of the memory chip SP, input E of the parallel-serial converter PSW. The exclusive OR logic element EOD1 has four connections on the input side.

Since RAM modules for four-bit data words are currently more readily available than those for eight-bit data words, the use of the former has advantages. Two so-called 4-bit RAM modules to form an 8-bit RAM module have an increased power consumption. The conversion of the bit stream BS into four bit wide bit words BW is not possible due to the too small address area of the RAM module. As already stated, the bit stream BS has 1080 bits in one frame. The conversion into four-bit wide bit words BW results in 270 addresses. Known 4-bit RAM modules only have 256 addressable memory locations.

The frame decoding of the bit stream BS is completely analogous to the frame decoding when the first or second half-words BWA, BWB are used as bit words BW, in which eight-bit wide bit words BW are used.

The synchronization bit S contained in the bit stream BS is either in one of the first half-words BWA or in one of the second half-words BWB. In frame decoding, the first and second half-words BWA, BWB are searched for, and then, if the synchronization bit S was not found, the second and first half-words BWB, BWA are searched for the synchronization bit S.

The circuit parts additionally required in the half-word version are described below.

This is the already described multiplexer MX, which has an input selection input EW, via which one of the inputs of the multiplexer MX, which are not specified in more detail, is switched through to the output, which is also not specified in detail. The output Q of the sixth delay flip-flop VF6 is connected via a further divider stage TE2, which has a division ratio of 2 to 1, to a further input D4 of the second delay flip-flop VF2, and to the input selection input EW of the multiplexer MX. In the half-word version, the input labeled D of the second delay flip-flop VF2 contains the connections D0 to D3. The same applies to the output Q of the second delay flip-flop VF2. Another output Q4 of the second delay flip-flop VF2 is connected to an input of a further exclusive OR gate EOD2, at whose other input the third clock drive pulses Q3 are present. The signal emitted by the second exclusive OR gate EOD2 is present at a further input of the AND gate UD1.

It is assumed that after switching on the circuit arrangement for decoding the frame to a power supply, a logic "1" is output from the further output Q4 of the second delay flip-flop VF2. The multiplexer MX, for example, switches the first half-word BWA through this logical "1".

In a first case, the synchronization bit S is located at a point in the bit stream BS that is converted into a second half-word BWB. As a result of the decoding process, that is to say when searching for the synchronization bit S in the first half-words BWA, the synchronization bit S is not found.

Here, the same process takes place as has already been described if the synchronization bit S is lost. Since no synchronization bit S is found in the first half-words BWA, there are finally only logical zeros in the memory chip SP. This causes a logic "1" at the output Q of the sixth delay flip-flop VF6, since the exclusive OR gate EOD1 no longer resets the fifth delay flip-flop. It is assumed that this logical "1", that is, the change to logical "1", causes a logical "0" at the input selection input EW of the multiplexer MX via the further divider stage TE2.

Due to the logical "0" at the input selection input EW of the multiplexer MX, the second half-word BWB is switched through. Then a search process takes place, which ends with the finding of the synchronization bit S in the second half-words BWB. As has already been described above for the eight-bit bit words BW, the counter Z runs up and causes the pending (m + 1) th second half-word BWB and the logical "0" output by the further divider stage TE2 to be transferred into the second delay -Flip-flop VF2. Due to the appearance of the logic "0" at the further output Q4 of the second delay flip-flop VF2, the third clock control pulses Q3 are not inverted via the further exclusive OR gate EOD2 to the AND gate UD1.

In the further description, reference is made again to FIG. 4. In the half-word version, two pulses are emitted from output A of the parallel-serial converter PSW within an address AD = x-1. Compared to an eight-bit bit word BW at input E of the parallel-serial converter PSW, the conversion of a four-bit bit word BW only needs half the time. Of these two pulses, the one must now be taken as the synchronization signal SS, which in this case belongs to the second half-word BWB.

Via the output signal of the further exclusive-OR logic element EOD2, the second of the two pulses emitted by output A of the parallel-serial converter PSW is selected within an address AD and output by output A of the AND logic element UD1 as a synchronization signal SS.

In a second case, the synchronization bit S is located at a point in the bit stream BS which is converted into a first half-word BWA. Through the decoding process, that is to say when searching for the synchronization bit S in the first half-words BWA, the synchronization bit S is found, as explained above with reference to the eight-bit wide bit word BW.

Due to the logic "1" which can be tapped at the further output Q4 of the second delay flip-flop VF2 in this case, the third clock control pulses Q3 are inverted via the further exclusive-OR logic element EOD2 to the AND logic element UD1. As a result, the first of the two pulses output by the output A of the parallel-serial converter PSW is selected within an address AD, and output by the output A of the AND logic element UD1 as a synchronization signal SS. This case is not shown in FIG. 4.

Analog processes take place when, due to other logic states at the further input D4 or further output Q4 of the second delay flip-flop VF2, the order of the half-words BWA or BWB in which the search is carried out for the synchronizing bit S is reversed.

Claims (9)

1. Method of frame decoding, preferably in a multiplexer-demultiplexer system for digital signal transmission, in which method a serial bit stream (BS) has a frame structure with a periodically occurring item of synchronising information which characterises the start of each frame, characterised in that, using a synchronising bit (S) as item of synchronising information, a logical AND operation is continuously carried out, commencing with an m-th search frame (SR) and with the subsequent (m+1)-th search frame (SR), each search frame (SR) having the same number of bits as the frame and the result forming the (m+1)-th search frame (SR) for the next logic operation, in that it is determined when only one bit, the synchronising bit (S), in the search frame (SR) is occupied by a logic "1", and this setting is maintained over a plurality of search frames (SR), in that a synchronising signal (SS) is generated in accordance with the timing position of the synchronising bit (S), in that the bit stream (BS) and/or the synchronising signal (SS) are delayed in such a way that the synchronising signal (SS) and the synchronising bit (S) occur synchronously in a delayed bit stream (VBS), and in that the search frame (SR) is divided into sections, the AND logic operation being carried out with the sections which assume the same position in the consecutive search frames (SR).
2. Method according to Claim 1, characterised in that the AND logic operations are carried out in each case with the r-th sections of the consecutive search frames (SR), the AND logic operations being carried on with the (r+1)-th sections of the consecutive search frames (SR) in the event that the result of the last logic operation of the r-th sections has bits occupied exclusively with logic zeros.
3. Circuit arrangement for frame decoding, preferably in a multiplexer-demultiplexer system for digital signal transmission, to which a serial bit stream (BS) and an associated clock pulse sequence (TO) are applied, characterised in that a series-parallel converter stage (SPS) is provided in which the bit stream (BS) is converted into parallel bit words (BW), the bits of a search frame (SR) being represented in at least one bit word (BW), in that AND logic operation elements are provided to which the bit words (BW) associated with one another are fed bit by bit, in that memory locations (SPL) are connected downstream of the AND logic operation elements for storing the result of this logic operation, in that furthermore an exclusive-OR logic operation element is connected to the memory locations (SPL) and emits a signal if the at least one bit word (BW) of a search frame (SR) has only one bit set to logic "1", in that this signal is applied to the circuit input of a parallel-series converter stage (PSS) which subsequently converts this at least one bit word (BW) into a serial synchronising signal (SS), and in that delay stages (VS1, VS2) are provided in the signal path of the bit stream (BS) and/or of the synchronising signal (SS).
4. Circuit arrangement according to Claim 3, characterised in that the series-parallel converter stage (SPS) has a series-parallel converter (SPW) in which the bit stream (BS) is converted into n-bit wide bit words (BW), the number of bits in one frame being an integral multiple of the number n, in that the memory locations (SPL) are located in a RAM memory module (SP) having an output control input (AS), in that the clock pulse sequence (TO) is applied to a clock and address processing stage (TA) which forms addresses (AD) in cycles, the number of addresses corresponding to the number of bit words (BW) in a search frame (SR), and the AND logic operations being carried out with bit words (BW) which are written under the same address (AD) in the memory module (SP), and in that the AND logic operation elements are realised by means of a first delay flip-flop (VF1) via which the bit words (BW) are transmitted to one input (E) of the memory module (SP) and which has a resetting pulse input (R) to which an output (A) of the memory module (SP) is connected, the AND logic operation being carried out with the (m+1)-th bit word (BW), which can be tapped off at the output (Q) of the first delay flip-flop (VE1), with the address (AD) = x by applying the m-th bit word (BW) with the address (AD) = x to the resetting pulse input (R) of the said delay flip-flop (VF1).
5. Circuit arrangement according to Claim 4 characterised in that the bit word (BW) applied to the input (E) of the memory module (SP) is applied to an exclusive -OR logic operation element (EOD1), in that a pulse is emitted from an output (A) of the exclusive-OR logic operation element (EOD1) if a bit word (BW) having only one bit set to logic "1" is registered by the said exclusive-OR logic operation element (EOD1), by means of which bit a preceding address (VAD) emitted by the clock and address processing stage (TA) is transferred into a first register (RG1), and in that a first comparative stage (V1) is provided having a first input (E1) to which the address (AD) is applied and having a second input (E2) to which an output (Q) of the first register (RG1) is connected, the first comparative stage (V1) emitting a signal at an output (A) if identical addresses are applied to its inputs (E1, E2), that is to say if, within a search frame (SR), only one bit word (BW) with only one bit (synchronising bit (S)) set to logic "1" is found.
6. Circuit arrangement according to Claim 5, characterised in that a counter (Z) is provided which emits a signal at an output (A) after a predetermined number of signals emitted from the output (A) of the first comparative stage (V1), in that a second register (RG2) is provided into which the preceding address (VAD) is transferred in the event of such a signal, and in that a second comparative stage (V2) is provided having a first input (E1) to which the address (AD) is applied and having a second input (E2) to which an output (Q) of the second register (RG2) is connected, the second comparative stage (V2) emitting a signal at an output (A) if the same addresses are applied to its inputs (E1, E2), that is to say if the single bit (synchronising bit(S)) set to logic "1" has been found in as many search frames (SR) as is determined by the predetermined number.
7. Circuit arrangement according to Claim 6, characterised in that the parallel-series converter stage (PSS) has a parallel-series converter (PSW) and a second delay flip-flop (VF2) via which the bit word (BW) applied to the input (E) of the memory module (SP) is transmitted to the parallel-series converter (PSW), the switching input to which the signal emitted by the output (A) of the counter (Z) is applied being realised by means of a clock input of the second delay flip-flop (VF2), and in that an AND logical operation element (UD1) is provided to which a serial bit sequence emitted by the parallel-series converter (PSW) and the signal emitted by the output (A) of the second comparative stage (V2) are applied, the synchronising signal (SS) being emitted by an output (A) of the AND logic operation element (UD1).
8. Circuit arrangement according to one of Claims 4 to 7, characterised in that the n bits of the n bit wide bit word (BW) are transmitted via two outputs (QA, QB), of the series-parallel converter in the form of two sets of n/2 bits to inputs of a multiplexer (MX) which emits a first half word (BWA) in a first switching state, and in a second switching state a second half word (BWB), the subsequent modules being designed for processing the n/2 bit wide half words (BWA, BWB) instead of the n bit wide bit words (BW), and in that after an unsuccessful search for the synchronising bit (S) in one of the half words (BWA or BWB) the search is continued in the respective other half word (BWB or BWA).
9. Circuit arrangement according to one of Claims 4 to 8, characterised in that the number n corresponds to the number 8.

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