CN115202943A - Data accelerator card, chip test system, method and electronic equipment - Google Patents
Data accelerator card, chip test system, method and electronic equipment Download PDFInfo
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- CN115202943A CN115202943A CN202210529646.3A CN202210529646A CN115202943A CN 115202943 A CN115202943 A CN 115202943A CN 202210529646 A CN202210529646 A CN 202210529646A CN 115202943 A CN115202943 A CN 115202943A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The invention provides a data accelerator card, a chip test system, a chip test method and electronic equipment, comprising the following steps: the device comprises a main controller, a plurality of sub-controllers and a plurality of test chips; the main controller is connected with the sub-controllers, and each sub-controller is connected with one test chip respectively; the main controller is used for reading the state information of each test chip in sequence and in a circulating manner according to a preset sequence and controlling the sub-controller and the test chips to carry out data transmission operation according to the state information; the test chip is used for calculating the received test data sent by the sub-controllers to obtain test results and returning the test results to the sub-controllers. The invention can automatically test a plurality of test chips and has simple operation.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a data accelerator card, a chip testing system, a chip testing method and electronic equipment.
Background
With the development of the chip industry, the control of the chip quality is more and more concerned. Ensuring the quality of chips, both for the manufacturer and the consumer, has become an increasingly important issue. Therefore, testing of the chip becomes an essential step. Most of the existing testing methods are used for testing a single chip, and when a large number of chips need to be tested, a large amount of labor and time are required, and the operation is complex.
Disclosure of Invention
In view of the above, the present invention provides a data accelerator card, a chip testing system, a chip testing method and an electronic device, which can automatically test a plurality of test chips and are simple in operation.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a data accelerator card, including: the device comprises a main controller, a plurality of sub-controllers and a plurality of test chips; the system comprises a main controller, a plurality of sub-controllers, a plurality of test chips and a plurality of test modules, wherein the main controller is connected with the sub-controllers, and each sub-controller is respectively connected with one test chip; the main controller is used for reading the state information of each test chip in sequence and in a circulating manner according to a preset sequence and controlling the sub-controller and the test chips to carry out data transmission operation according to the state information; the test chip is used for calculating the received test data sent by the sub-controllers to obtain test results and returning the test results to the sub-controllers.
In one embodiment, the data accelerator card further comprises: the device comprises a read memory and a write memory, wherein each sub-controller is connected with one read memory; the read memory is used for storing the test result of the test chip, and the write memory is used for storing the test data issued by the upper computer.
In one embodiment, when the main controller determines that the state information of the test chip satisfies a first preset condition, the sub-controller is controlled to read the test data from the write memory and transmit the test data to the test chip connected to the sub-controller.
In one embodiment, when the main controller determines that the state information of the test chip meets the second preset condition, the control sub-controller reads the test result of the test chip connected with the sub-controller and stores the test result in the corresponding read memory.
In one embodiment, the data accelerator card further comprises: and the PCIE interface is used for connecting an upper computer.
In one embodiment, the data accelerator card further comprises: heat dissipation assembly and power supply unit.
In a second aspect, an embodiment of the present invention provides a chip testing system, including: the data accelerator card of any one of the first aspect and the upper computer connected with the data accelerator card; and a PCIE driving program is configured in the upper computer and used for sending control signals and test data to the data accelerator card and reading the test result of each test chip.
In one embodiment, the upper computer is further configured to obtain status information of each test chip and temperature information of the data accelerator card.
In a third aspect, an embodiment of the present invention provides a chip testing method, where the method is applied to any one of the data accelerator cards provided in the first aspect, and the method includes: sequentially and circularly reading the state information of each test chip according to a preset sequence; and controlling the sub-controller and the test chip to perform data transmission operation according to the state information.
In one embodiment, the step of controlling the sub-controller and the test chip to perform the data transmission operation according to the status information includes: when the test chip of the sub-controller meets a first preset condition, controlling the sub-controller to read test data from the write memory and send the test data to the test chip connected with the sub-controller; the test chip calculates the test data to obtain a test result, and returns the test result to the sub-controller.
In one embodiment, the step of controlling the sub-controller and the test chip to perform the data transmission operation according to the status information further comprises: and when the state information of the test chip meets a second preset condition, controlling the sub-controllers to read the test results of the test chip connected with the sub-controllers and storing the test results in the corresponding read memories.
In one embodiment, the method further comprises: and receiving a starting signal sent by the upper computer, and initializing the data accelerator card based on the starting signal.
In a fourth aspect, an embodiment of the present invention provides an electronic device, which includes a processor and a memory, where the memory stores computer-executable instructions capable of being executed by the processor, and the processor executes the computer-executable instructions to implement the steps of any one of the methods provided in the third aspect.
In a fifth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of any one of the methods provided in the third aspect.
The embodiment of the invention has the following beneficial effects:
the data accelerator card, the chip test system, the method and the electronic equipment provided by the embodiment of the invention comprise the following steps: the device comprises a main controller, a plurality of sub-controllers and a plurality of test chips; the system comprises a main controller, a plurality of sub-controllers, a plurality of test chips and a plurality of test modules, wherein the main controller is connected with the sub-controllers, and each sub-controller is respectively connected with one test chip; the main controller is used for sequentially reading the state information of each test chip in a circulating manner according to a preset sequence and controlling the sub-controller and the test chips to carry out data transmission operation according to the state information; the test chip is used for calculating the received test data sent by the sub-controllers to obtain test results and returning the test results to the sub-controllers. Above-mentioned data acceleration card, every sub-controller and test chip form a control assembly line, control a plurality of control assembly lines simultaneously through main control unit, according to predetermineeing the order, circulate in proper order and judge the status information of test chip to carry out corresponding data transmission operation according to the status information of test chip, thereby can realize testing a plurality of test chip automaticly simultaneously, easy operation.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a data accelerator card according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another data accelerator card according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a chip testing system according to an embodiment of the present invention;
FIG. 4 is a flowchart of a chip testing method according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating write data according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating read data according to an embodiment of the present invention;
FIG. 7 is a flow chart of a single chip test according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Icon:
10-a main controller; 20-a sub-controller; 30-testing the chip; 40-read memory; 50-write memory; a 60-PCIE interface; 70-a heat dissipation assembly; 80-a power supply unit; 301-data accelerator card; 302-upper computer.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, most of the existing chip testing methods are used for testing a single chip, and when a large number of chips need to be tested, a large amount of manpower and time are required to be consumed, so that the operation is complex. Based on this, the data accelerator card, the chip test system, the chip test method and the electronic device provided by the embodiment of the invention can automatically test a plurality of test chips, and are simple to operate.
To facilitate understanding of the present embodiment, first, a data accelerator card disclosed in the embodiment of the present invention is described in detail, referring to a schematic structural diagram of a data accelerator card shown in fig. 1, which illustrates that the data accelerator card mainly includes: a main controller 10, a plurality of sub-controllers 20, and a plurality of test chips 30; the main controller 10 is connected with the sub-controllers 20, and each sub-controller 20 is connected with one test chip 30; the main controller 10 is configured to sequentially and cyclically read the state information of each test chip 30 according to a preset sequence, and control the sub-controller 20 and the test chips 30 to perform data transmission operation according to the state information; the test chip 30 is configured to calculate the received test data sent by the sub-controller 20 to obtain a test result, and return the test result to the sub-controller 20.
In an implementation manner, the data accelerator card provided in the embodiment of the present invention is developed by using a PCIE (peripheral component interconnect express) FPGA (Field Programmable Gate Array) as a development platform, and can transmit data to a multi-channel test chip at a high speed and in parallel. In a specific application, each test chip 30 is connected to one sub-controller 20, and the main controller 10 can automatically and sequentially read the status information of each test chip 30, and control the sub-controllers 20 to perform corresponding data transmission operations, such as writing test data, reading test results, and the like, according to the read status information. When the sub-controllers 20 send the test data to the test chip 30, and the test chip 30 calculates the test data, the main controller 10 will continue to read the status information of the next sub-controller 20 in sequence until the test on all the test chips 30 is realized.
According to the data accelerator card provided by the embodiment of the invention, each sub-controller and the test chip form a control assembly line, the main controller is used for simultaneously controlling the plurality of control assembly lines, the state information of the test chip is sequentially and circularly judged according to the preset sequence, and corresponding data transmission operation is carried out according to the state information of the test chip, so that the plurality of test chips can be automatically tested simultaneously, and the operation is simple.
Further, referring to fig. 2, on the basis of fig. 1, the data accelerator card provided in the embodiment of the present invention further includes: the memory comprises a read memory 40, a write memory 50, a PCIE interface 60, a heat dissipation assembly 70 and a power supply unit 80, wherein the power supply unit 80 is a 400A high-current power supply. Specifically, the sub-controllers and the test chip can communicate with each other through a QSPI bus, each sub-controller is connected to a read memory 40, the read memory 40 is used for storing a test result of the test chip 30, and the write memory 50 is used for storing test data issued by the upper computer. The read memory 40 may specifically adopt a read FIFO (First Input First Output, first in First out queue), and the write memory 50 may adopt a write FIFO.
In one embodiment, when the main controller determines that the state information of the test chip satisfies a first preset condition, the sub-controller is controlled to read the test data from the write memory and transmit the test data to the test chip connected to the sub-controller. Specifically, the first preset condition may be that the storage space for storing the test data inside the test chip 30 is not full and there is no test result in the storage space for storing the test result inside the test chip 30, that is, if the main controller 10 determines, according to the read status information of the test chip 30, that the storage space for storing the test data inside the test chip 30 is not full and there is no test result in the storage space for storing the test result inside the test chip 30, the sub-controller 20 may read the test data from the write memory 50 and send the test data to the test chip 30 connected thereto, and the test chip 30 calculates the received test data to obtain the test result and stores the test result in the storage space for storing the test result inside the test chip 30.
In one embodiment, when the main controller determines that the state information of the test chip satisfies the second preset condition, the sub-controller is controlled to read the test result of the test chip connected with the sub-controller and store the test result in the corresponding read memory. Specifically, the second preset condition may be that there is a test result in the storage space for storing the test result inside the test chip 30, that is, if the main controller 10 determines that there is a test result in the storage space for storing the test result inside the test chip 30 according to the read status information of the test chip 30, the sub-controller 20 may read the test result from the storage space for storing the test result inside the test chip 30, and store the read test result in the corresponding read memory 40.
In an implementation manner, the data accelerator card provided in the embodiment of the present invention is connected to an external upper computer through a PCIE interface 60, a PCIE high-speed channel is used for transmitting data, and a transmission rate can reach 800MB/s, so that the performance of the data accelerator card is improved.
In an implementation manner, the data accelerator card provided in the embodiment of the present invention is configured with the integrated heat dissipation assembly 70, so that heat can be dissipated timely and quickly, thereby ensuring that the data accelerator card operates at a proper temperature, reducing loss, and further improving the performance of the data accelerator card.
According to the data accelerator card provided by the embodiment of the invention, firstly, a multi-channel chip control pipeline is configured in the data accelerator card, so that data can be received and transmitted automatically, an upper computer only needs to transmit test data into a buffer area in the data accelerator card, the data accelerator card can automatically test the multi-channel test chip, and the operation is simple and convenient; secondly, a large-capacity memory is configured in the data accelerator card and used as a data buffer area, so that a test result can be stored, and the data accelerator card is convenient to use in subsequent tests; finally, the data accelerator card transmits data by using a PCIE high-speed channel, the transmission rate can reach 800MB/s, 400A high-current power supply is supported, and an integrated heat dissipation device is configured, so that the performance of the data accelerator card is further improved.
For the data accelerator card provided in the foregoing embodiment, an embodiment of the present invention further provides a chip testing system, referring to a schematic structural diagram of the chip testing system shown in fig. 3, where the system may include the following components: a data acceleration card 301 and an upper computer 302 connected with the data acceleration card; a PCIE driver is configured inside the upper computer 302, and is configured to issue a control signal and test data to the data accelerator card 301, and read a test result of each test chip; and is also used to obtain status information of each test chip and temperature information of data accelerator card 301.
In an embodiment, the upper computer 302 may be configured with related upper computer software, dynamic Link Library (DLL), and PCIE drivers (such as drivers in Linux and Win10 systems), and the upper computer 302 and the data accelerator card 301 are connected through a PCIE interface to implement data transmission. When the chip is tested, the upper computer 302 only needs to send a starting signal to the data acceleration card 301, and send test data to the data acceleration card 301 for storage, the data acceleration card 301 can automatically read the state information of each test chip under the condition that the upper computer 302 does not need to participate, and transmit data to the test chip through the QSPI bus, after the main controller reads the test chip and has a test result, the sub-controller can read the test result from the test chip and transmit the test result to the read memory of the data acceleration card 301 for caching, so that the upper computer 302 can read the test result.
Further, the PCIE driver of the upper computer 302 may also initialize the state of the data accelerator card 301, send various control commands, and query the state information of the test chip and the temperature information of the data accelerator card 301.
The chip testing system provided by the embodiment of the invention can automatically read the state information of each testing chip without the participation of an upper computer, and carry out corresponding data transmission operation according to the state information of the testing chip, thereby realizing the automatic testing of a plurality of testing chips at the same time and having simple operation.
It should be noted that, the chip testing system provided by the embodiment of the present invention has the same implementation principle and the same technical effect as the foregoing embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing embodiment for the part of the embodiment of the chip testing system that is not mentioned.
For the data accelerator card provided in the foregoing embodiment, an embodiment of the present invention further provides a chip testing method, where the method is applied to the data accelerator card provided in the foregoing embodiment, and referring to a flowchart of a chip testing method shown in fig. 4, it is shown that the method mainly includes the following steps S401 to S402:
step S401: and sequentially and circularly reading the state information of each test chip according to a preset sequence.
Step S402: and controlling the sub-controller and the test chip to perform data transmission operation according to the state information.
In one embodiment, taking 16 test chips as an example, the test chips may be numbered in advance, i.e. from test chip No. 1 to test chip No. 16, and the numbers of the sub-controllers connected to the test chips correspond to the numbers of the sub-controllers. And in the test process, the upper computer issues the test data to the data accelerator card and stores the test data in the write memory. The main controller sequentially reads the state information of each test chip according to a preset sequence (1-16), and controls the sub-controllers to perform corresponding data transmission operations according to the read state information, such as writing test data, reading test results and the like.
The chip testing method provided by the embodiment of the invention can automatically read the state information of each testing chip without the participation of an upper computer, and perform corresponding data transmission operation according to the state information of the testing chip, thereby realizing the automatic testing of a plurality of testing chips at the same time and having simple operation.
The method provided by the embodiment of the present invention further includes, before step S401: and receiving a starting signal sent by the upper computer, and initializing the data accelerator card based on the starting signal so as to ensure that the data accelerator card can stably work.
Further, as for the aforementioned step S402, that is, the step of controlling the sub-controller and the test chip to perform the data transmission operation according to the status information, the following two cases are mainly included:
(1) When the state information of the test chip meets a first preset condition, controlling the sub-controller to read the test data from the write memory and sending the test data to the test chip connected with the sub-controller; the test chip calculates the test data to obtain a test result, and returns the test result to the sub-controller.
Specifically, the first preset condition may be that a storage space for storing the test data inside the test chip is not full and a storage space for storing the test result inside the test chip does not have the test result. Referring to fig. 5, a schematic diagram of writing data is shown, in which an XDMA is shown as a driver of a data accelerator card for data transmission with an upper computer. If the main controller determines that the storage space for storing the test data in the test chip is not full and no test result exists in the storage space for storing the test result in the test chip according to the read state information of the test chip No. 1, the sub-controller No. 1 can read one test data from the write memory and send the test data to the test chip No. 1 connected with the sub-controller, and the test chip No. 1 can calculate the received test data to obtain the test result and store the test result into the storage space for storing the test result in the test chip No. 1. While the sub-controller 1 performs writing operation, the flow of the main controller is still continued, the states of the No. 2-16 test chips are sequentially judged (namely state information is read), the No. 1 test chip is returned again after the judgment is finished, the No. 1-16 test chips are judged, and if the test result is not calculated yet at the moment, the test data are continuously written; if the calculation is completed, the test result data is stored in a read FIFO inside the data accelerator card.
(2) And when the state information of the test chip meets a second preset condition, controlling the sub-controllers to read the test results of the test chip connected with the sub-controllers and storing the test results in the corresponding read memories.
Specifically, the second preset condition may be that a test result exists in a storage space for storing the test result inside the test chip. Referring to a schematic diagram of reading data shown in fig. 6, if the main controller determines that the storage space for storing the test result inside the test chip has the test result according to the read status information of the test chip, the sub-controller may read the test result from the storage space for storing the test result inside the test chip, and store the read test result in the corresponding read memory for the upper computer to read.
Furthermore, for the test chip, writing of test data to the test chip and reading of test results from the test chip cannot be performed simultaneously. After the test data is written, the inside of the chip can be calculated to return a test result, and the returned test result can be stored in a chip memory area.
The method provided by the embodiment of the invention can carry out full-automatic test operation on a plurality of chips, the plurality of chips simultaneously work, the state of each test chip is judged, data writing or result reading and other operations are carried out according to the state of the chip, and multi-channel tests are sequentially executed without conflict, so that an operator only needs to start the test, and the operation burden is reduced.
For convenience of understanding, the embodiment of the present invention further provides a single chip test flowchart, which is shown in fig. 7 and mainly includes the following steps S701 to step 705:
step S701: the main controller judges the state information of the test chip; if the state information of the test chip meets the first preset condition, executing step S702; if the state information of the test chip satisfies the second predetermined condition, step S704 is executed.
In one embodiment, the first preset condition may be that a storage space for storing the test data inside the test chip is not full and a storage space for storing the test result inside the test chip does not have the test result, and the second preset condition may be that the storage space for storing the test result inside the test chip has the test result.
Step S702: and the sub-controller reads the test data from the write memory and sends the test data to the test chip.
Step S703: the test chip calculates the received test data to obtain a test result, and returns to step S701.
Step S704: and reading the test result from the storage space for storing the test result in the test chip by the sub-controller.
Step S705: the sub-controller stores the read test result in the corresponding read memory, and returns to step S701.
It should be noted that, the method provided by the embodiment of the present invention, the implementation principle and the resulting technical effect are the same as those of the foregoing embodiment, and for the sake of brief description, the corresponding contents in the foregoing embodiment may be referred to where no portion of the embodiment of the method is mentioned.
The embodiment of the invention also provides electronic equipment, which specifically comprises a processor and a storage device; the storage means has stored thereon a computer program which, when executed by the processor, performs the method of any of the above embodiments.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 100 includes: the device comprises a processor 81, a memory 82, a bus 83 and a communication interface 84, wherein the processor 81, the communication interface 84 and the memory 82 are connected through the bus 83; the processor 81 is arranged to execute executable modules, such as computer programs, stored in the memory 82.
The Memory 82 may include a high-speed Random Access Memory (RAM) and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 84 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used.
The bus 83 may be an ISA bus, PCI bus, EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 8, but this does not indicate only one bus or one type of bus.
The memory 82 is used for storing a program, the processor 81 executes the program after receiving an execution instruction, and the method executed by the apparatus defined by the flow process disclosed in any of the foregoing embodiments of the present invention may be applied to the processor 81, or implemented by the processor 81.
The processor 81 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 81. The Processor 81 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 82, and the processor 81 reads the information in the memory 82 and performs the steps of the above method in combination with the hardware thereof.
The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the method described in the foregoing method embodiment, and specific implementation may refer to the foregoing method embodiment, which is not described herein again.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: those skilled in the art can still make modifications or changes to the embodiments described in the foregoing embodiments, or make equivalent substitutions for some features, within the scope of the disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (14)
1. A data accelerator card, comprising: the device comprises a main controller, a plurality of sub-controllers and a plurality of test chips; the main controller is connected with the sub-controllers, and each sub-controller is connected with one test chip respectively;
the main controller is used for sequentially reading the state information of each test chip in a circulating manner according to a preset sequence and controlling the sub-controller and the test chips to carry out data transmission operation according to the state information;
the test chip is used for calculating the received test data sent by the sub-controllers to obtain test results and returning the test results to the sub-controllers.
2. The data accelerator card of claim 1, further comprising: the reading memory and the writing memory are connected, wherein each sub-controller is connected with one reading memory;
the read memory is used for storing the test result of the test chip, and the write memory is used for storing the test data issued by the upper computer.
3. The data accelerator card of claim 2, wherein when the main controller determines that the status information of the test chip satisfies a first preset condition, the main controller controls the sub-controller to read the test data from the write memory and send the test data to the test chip connected to the sub-controller.
4. The data accelerator card of claim 2, wherein when the main controller determines that the status information of the test chip satisfies a second preset condition, the main controller controls the sub-controller to read the test result of the test chip connected to the sub-controller and store the test result in a corresponding read memory.
5. The data accelerator card of claim 1, further comprising: and the PCIE interface is used for connecting an upper computer.
6. The data accelerator card of claim 1, further comprising: heat dissipation assembly and power supply unit.
7. A chip test system, comprising: the data accelerator card of any one of claims 1 to 6, and an upper computer connected to the data accelerator card;
and a PCIE driving program is configured in the upper computer and used for sending control signals and test data to the data accelerator card and reading the test result of each test chip.
8. The chip testing system according to claim 7, wherein the upper computer is further configured to obtain status information of each of the test chips and temperature information of the data accelerator card.
9. A chip testing method applied to the data accelerator card of any one of claims 1 to 6, the method comprising:
sequentially and circularly reading the state information of each test chip according to a preset sequence;
and controlling the sub-controller and the test chip to perform data transmission operation according to the state information.
10. The method of claim 9, wherein the step of controlling the sub-controller and the test chip to perform a data transfer operation according to the status information comprises:
when the state information of the test chip meets a first preset condition, controlling the sub-controller to read test data from a write memory and sending the test data to the test chip connected with the sub-controller;
and the test chip calculates the test data to obtain a test result and returns the test result to the sub-controller.
11. The method of claim 9, wherein the step of controlling the sub-controller and the test chip to perform a data transfer operation according to the status information further comprises:
and when the state information of the test chip meets a second preset condition, controlling the sub-controllers to read the test results of the test chip connected with the sub-controllers, and storing the test results in corresponding read memories.
12. The method of claim 9, further comprising:
and receiving a starting signal sent by an upper computer, and initializing the data accelerator card based on the starting signal.
13. An electronic device comprising a processor and a memory, the memory storing computer-executable instructions executable by the processor to perform the steps of the method of any of claims 9 to 12.
14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of the preceding claims 9 to 12.
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| CN116106725A (en) * | 2023-03-24 | 2023-05-12 | 大唐恩智浦半导体（徐州）有限公司 | Multi-chip power-on test system, method and device and electronic equipment |
| CN116132186A (en) * | 2023-02-22 | 2023-05-16 | 广州万协通信息技术有限公司 | Verification method and verification device of security algorithm module and electronic equipment |
| CN116884470A (en) * | 2023-06-27 | 2023-10-13 | 珠海妙存科技有限公司 | Storage product testing method and system, electronic equipment and storage medium |
| CN117409851A (en) * | 2023-12-15 | 2024-01-16 | 合肥康芯威存储技术有限公司 | Test system and test method for memory chip |
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| CN116132186A (en) * | 2023-02-22 | 2023-05-16 | 广州万协通信息技术有限公司 | Verification method and verification device of security algorithm module and electronic equipment |
| CN116132186B (en) * | 2023-02-22 | 2024-02-27 | 广州万协通信息技术有限公司 | Verification method and device of security algorithm module, electronic equipment and storage medium |
| CN116106725A (en) * | 2023-03-24 | 2023-05-12 | 大唐恩智浦半导体（徐州）有限公司 | Multi-chip power-on test system, method and device and electronic equipment |
| CN116884470A (en) * | 2023-06-27 | 2023-10-13 | 珠海妙存科技有限公司 | Storage product testing method and system, electronic equipment and storage medium |
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