CN109190276A - FPGA prototype verification system - Google Patents
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- CN109190276A CN109190276A CN201811072493.4A CN201811072493A CN109190276A CN 109190276 A CN109190276 A CN 109190276A CN 201811072493 A CN201811072493 A CN 201811072493A CN 109190276 A CN109190276 A CN 109190276A
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- 238000004891 communication Methods 0.000 claims description 19
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- 238000002474 experimental method Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000012360 testing method Methods 0.000 description 2
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- 238000004590 computer program Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The present invention provides a kind of FPGA prototype verification system, the FPGA prototype verification system includes: at least two cascade FPGA prototype verification plates；The port I/O of the high speed connector of previous stage FPGA prototype verification plate is connect with the port I/O of the high speed connector of rear stage FPGA prototype verification plate；The port I/O of the optical interface module of previous stage FPGA prototype verification plate is connect with the port I/O of the optical interface module of rear stage FPGA prototype verification plate.Reach through high speed connector and optical interface module, the cascade of plate grade can flexibly be carried out, consequently facilitating carrying out some large-scale modules or the experiment of full chip prototype verification, the technical effect for solving the few disadvantage of existing scheme interconnection interface can be greatly improved with interconnection interface.
Description
Technical field
The present invention relates to FPGA prototype verification technical fields, more particularly, to a kind of FPGA prototype verification system.
Background technique
FPGA prototype is a kind of technology of maturation, for by the way that RTL is transplanted to field programmable gate array
(FPGA) integrated circuit (ASIC) of specialized application, the function of Application Specific Standard Product (ASSP) and system on chip (SoC) are verified
And performance.
Since hardware complexity is continuously increased, the related software quantity for needing to verify is continuously increased, therefore its today makes
It is more extensive with range.
Since the software usually accounts for more than half of design efforts would, so the FPGA realization of SoC RTL is also used as
The basis-of software development, hardware/software co-verification and software verification is all these all complete before final silicon chip is available
At.
All of these factors taken together both contributes to reduce design cost and shortens Time To Market, reduces the risk of readjustment.Example
Such as, the software verified extensively in FPGA prototype should be easier the chip after flow and combine.One available
FPGA prototype can be used for product demonstration and field test.
However, current FPGA verifies system, the small number of the interconnecting interface communicated between every two panels FPGA piece is insufficient
To support large-scale data to exchange.
Summary of the invention
In view of this, being deposited in the prior art the purpose of the present invention is to provide a kind of FPGA prototype verification system with alleviating
Every two panels FPGA piece between the small number of interface that communicates, be not enough to the technical issues of supporting large-scale data to exchange.
In a first aspect, the embodiment of the invention provides a kind of FPGA prototype verification systems, comprising: at least two is cascade
FPGA prototype verification plate；
The port I/O of the high speed connector of previous stage FPGA prototype verification plate and the high speed of rear stage FPGA prototype verification plate
The port I/O of connector connects；
The port I/O of the optical interface module of previous stage FPGA prototype verification plate and the light of rear stage FPGA prototype verification plate connect
The port I/O of mouth mold block connects.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein institute
Stating FPGA prototype verification plate includes: FPGA module, optical interface module and high speed connector；
The GTH high-speed interface of the FPGA module and the optical interface of the optical interface module are correspondingly connected with；
The high-performance I/O interface of the FPGA module is correspondingly connected with the port I/O of the high speed connector.
With reference to first aspect, the embodiment of the invention provides second of possible embodiments of first aspect, wherein more
It is a length of arrangement wire between the port I/O of the high speed connector is interfaced to by the high-performance I/O of the FPGA module to pass through respectively
Isometric constraint processing is crossed, so that the length difference between length of arrangement wire described in any two is less than default constraint threshold value.
With reference to first aspect, the embodiment of the invention provides the third possible embodiments of first aspect, wherein high
The port I/O of fast connector uses LVDS level.
With reference to first aspect, the embodiment of the invention provides the 4th kind of possible embodiments of first aspect, wherein institute
State FPGA prototype verification plate further include: processor；
It is connected between the processor and the FPGA module by communication bus.
With reference to first aspect, the embodiment of the invention provides the 5th kind of possible embodiments of first aspect, wherein institute
Stating communication bus includes: I2C communication bus, RapidIO communication bus, PCIe communication bus and 10GBase-KR communication bus.
With reference to first aspect, the embodiment of the invention provides the 6th kind of possible embodiments of first aspect, wherein institute
State FPGA prototype verification plate further include: CPLD module；
It is connected between the CPLD module and the FPGA module by parallel bus.
With reference to first aspect, the embodiment of the invention provides the 7th kind of possible embodiments of first aspect, wherein institute
State FPGA prototype verification plate further include: power module；
The power module is FPGA prototype verification plate power supply.
With reference to first aspect, the embodiment of the invention provides the 8th kind of possible embodiments of first aspect, wherein institute
State FPGA prototype verification plate further include: clock module；
The clock module provides clock signal for the FPGA prototype verification plate.
The embodiment of the present invention brings following the utility model has the advantages that the embodiment of the present invention is by by previous stage FPGA prototype verification plate
The port I/O of high speed connector connect with the port I/O of the high speed connector of rear stage FPGA prototype verification plate, by previous stage
The end I/O of the optical interface module of the port I/O and rear stage FPGA prototype verification plate of the optical interface module of FPGA prototype verification plate
Mouth connection, by high speed connector and optical interface module, can flexibly carry out the cascade of plate grade, consequently facilitating carrying out some big
The module of scale or the experiment of full chip prototype verification can greatly improve that solve existing scheme interconnection interface few with interconnection interface
The shortcomings that.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention are in specification, claims
And specifically noted structure is achieved and obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structure chart of FPGA prototype verification system provided in an embodiment of the present invention；
Fig. 2 is a kind of structure chart of FPGA prototype verification system provided in an embodiment of the present invention；
Fig. 3 is the structure chart of another FPGA prototype verification plate provided in an embodiment of the present invention；
Fig. 4 is the structure chart of another FPGA prototype verification plate provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
Current FPGA verifies system, and the small number of the interconnecting interface communicated between every two panels FPGA piece is not enough to prop up
Large-scale data exchange is held, such as: VU440 cascade witness plate needs to meet the base of resource and interface under single exchange verifying scene
This demand, simultaneously because full chip logic resource occupation is larger, and even if the current Xilinx maximum FPGA of logical resource, 1
Also it is unable to satisfy requirement, is based on this, a kind of FPGA prototype verification system provided in an embodiment of the present invention can be by by previous stage
The end I/O of the high speed connector of the port I/O and rear stage FPGA prototype verification plate of the high speed connector of FPGA prototype verification plate
Mouth connection, by the light of the port I/O of the optical interface module of previous stage FPGA prototype verification plate and rear stage FPGA prototype verification plate
The port I/O of interface module connects, and by high speed connector and optical interface module, can flexibly carry out the cascade of plate grade, from
And it is convenient for some large-scale modules or the experiment of full chip prototype verification, it can be solved now with greatly improving for interconnection interface
Have the shortcomings that scheme interconnection interface is few.
For convenient for understanding the present embodiment, first to a kind of FPGA prototype verification system disclosed in the embodiment of the present invention
System system describes in detail, and the FPGA prototype verification system includes: at least two cascade FPGA prototype verification plates；Example
Property, it include two blocks of cascade FPGA prototype verification plates in Fig. 1, in practical applications, to meet actual demand, FPGA prototype is tested
In card system can also include 3 pieces ... 10 pieces ... 100 pieces etc. of FPGA prototype verification plate；
Referring to Fig. 1, the port I/O of the high speed connector of previous stage FPGA prototype verification plate and rear stage FPGA prototype verification
The port I/O of the high speed connector of plate connects；
The port I/O of the optical interface module of previous stage FPGA prototype verification plate and the light of rear stage FPGA prototype verification plate connect
The port I/O of mouth mold block connects.
The embodiment of the present invention is by by the port I/O of the high speed connector of previous stage FPGA prototype verification plate and rear stage
The port I/O of the high speed connector of FPGA prototype verification plate connects, by the optical interface module of previous stage FPGA prototype verification plate
The port I/O is connect with the port I/O of the optical interface module of rear stage FPGA prototype verification plate, passes through high speed connector and optical interface
Module can flexibly carry out the cascade of plate grade, consequently facilitating carrying out some large-scale modules or full chip prototype verification reality
It tests, can solve the few disadvantage of existing scheme interconnection interface with greatly improving for interconnection interface.
As shown in Fig. 2, the FPGA prototype verification plate includes: FPGA module 11, light in another embodiment of the present invention
Interface module 12 and high speed connector 13；
The GTH high-speed interface of the FPGA module 11 and the optical interface of the optical interface module 12 are correspondingly connected with；It is exemplary
, optical interface module 12 can refer to QSFP+ optical interface module 12, in the embodiment of the present invention 40 high-speed channel interfaces of FPGA with
4 × form, by QSFP+ optical interface module 12 draw, can be with the optical interface pair of other QSFP+ forms without any switching
It connects, it is only necessary to can be docked with the optical interface of SFP+ form using point fine optical fiber, be tested carrying out all kinds of high speed protocol prototypes
It is very convenient when card.
The high-performance I/O interface of the FPGA module 11 and the port I/O of the high speed connector 13 are correspondingly connected with.
In embodiments of the present invention, FPGA module 11 be prototype verification with FPGA (such as: VU440FPGA also can be used
Other model same type devices) and its peripheral system circuit；VU440FPGA shares 48 GTH high-speed interfaces, wherein 40 pass through
QSFP+ optical module is drawn, i.e. QSFP+ optical interface module 12；VU440FPGA shares 1404 HP I/O (High
Performance I/O, high-performance input/output) interface, it is drawn by the SEAF high speed connector 13 of Samtec therein
600 pairs of difference I/O interfaces, i.e. SEAF interface module, 600 pairs of differential lines be it is two-way, both can receive or send out.
Multiple high-performance I/O by the FPGA module 11 are interfaced between the port I/O of the high speed connector 13
Length of arrangement wire is handled by isometric constraint respectively, so that the length difference between length of arrangement wire described in any two is less than default constraint
Threshold value guarantees the requirements of timing constraints of bus data transfer.Stringent isometric constraint processing is all done in practical printed board, that
Length difference emulates within 10mil, and to the signal integrity and time delay of cabling between this, guarantees its quality.Illustratively,
Based on aforementioned VU440FPGA, 600 couples of difference I/O can all be done with stringent isometric constraint processing in practical printed board, that
Length difference is within 10mil between this, causes to require timing which solves length of arrangement wire in existing scheme is inconsistent
Not the shortcomings that multi-disc cascade verifying is not available.
The port I/O of high speed connector 13 uses LVDS level, using LVDS level standard, improves transmission speed, simultaneously
Support multiplexing.
As shown in figure 3, in another embodiment of the present invention, the FPGA prototype verification plate further include: processor 14；Place
The T2080 processor 14 that device 14 is NXP is managed, in the embodiment of the present invention, is added the T2080 processor 14 of NXP, processor 14 can be with
Operating system is run, the cooperation verifying of processor 14 is being needed, as configured, being accessed, data interaction to the RTL module verified
Etc. it is very convenient under scenes.The addition of processor 14 is also more nearly the true hardware environment of most chips, can be in prototype
It verifies the same period and carries out software development, greatly shorten the hardware and software development period.
It is connected between the processor 14 and the FPGA module 11 by communication bus.The communication bus includes: I2C
Communication bus, RapidIO communication bus, PCIe communication bus and 10GBase-KR communication bus.In embodiments of the present invention, lead to
Believe that bus can also include other communication bus, various configurations access mode can be provided for confirmatory experiment, it is in addition also closer
The use environment of actual chips.
As shown in figure 4, in another embodiment of the present invention, the FPGA prototype verification plate further include: 15 mould of CPLD
Block；It is connected between 15 module of CPLD and the FPGA module 11 by parallel bus.
In another embodiment of the present invention, the FPGA prototype verification plate further include: power module (not shown)；
The power module is the electronics of each needs power supply in the FPGA prototype verification plate.
The FPGA prototype verification plate further include: clock module (not shown)；The clock module is the FPGA
Each electronic device for needing clock signal in prototype verification plate provides clock signal.
The computer program product of FPGA prototype verification system provided by the embodiment of the present invention, including store program generation
The computer readable storage medium of code, the instruction that said program code includes can be used for executing previous methods as described in the examples
Method, specific implementation can be found in embodiment of the method, and details are not described herein.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
It with the specific work process of device, can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
In addition, in the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. a kind of FPGA prototype verification system characterized by comprising at least two cascade FPGA prototype verification plates；
The port I/O of the high speed connector of previous stage FPGA prototype verification plate is connect with the high speed of rear stage FPGA prototype verification plate
The port I/O of device connects；
The port I/O of the optical interface module of previous stage FPGA prototype verification plate and the optical interface mould of rear stage FPGA prototype verification plate
The port I/O of block connects.
2. FPGA prototype verification system according to claim 1, which is characterized in that the FPGA prototype verification plate includes:
FPGA module, optical interface module and high speed connector；
The GTH high-speed interface of the FPGA module and the optical interface of the optical interface module are correspondingly connected with；
The high-performance I/O interface of the FPGA module is correspondingly connected with the port I/O of the high speed connector.
3. FPGA prototype verification system according to claim 2, which is characterized in that multiple high property by the FPGA module
Energy I/O is interfaced to the length of arrangement wire between the port I/O of the high speed connector and handles respectively by isometric constraint, so that arbitrarily
Length difference between two length of arrangement wire is less than default constraint threshold value, guarantees the requirements of timing constraints of bus data transfer.
4. FPGA prototype verification system according to claim 2, which is characterized in that the port I/O of high speed connector uses
LVDS level.
5. FPGA prototype verification system according to claim 2, which is characterized in that the FPGA prototype verification plate also wraps
It includes: processor；
It is connected between the processor and the FPGA module by communication bus.
6. FPGA prototype verification system according to claim 5, which is characterized in that the communication bus includes: I2C communication
Bus, RapidIO communication bus, PCIe communication bus and 10GBase-KR communication bus.
7. FPGA prototype verification system according to claim 2, which is characterized in that the FPGA prototype verification plate also wraps
It includes: CPLD module；
It is connected between the CPLD module and the FPGA module by parallel bus.
8. FPGA prototype verification system according to claim 2, which is characterized in that the FPGA prototype verification plate also wraps
It includes: power module；
The power module is FPGA prototype verification plate power supply.
9. FPGA prototype verification system according to claim 2, which is characterized in that the FPGA prototype verification plate also wraps
It includes: clock module；
The clock module provides clock signal for the FPGA prototype verification plate.
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| CN201811072493.4A CN109190276A (en) | 2018-09-14 | 2018-09-14 | FPGA prototype verification system |
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| CN201811072493.4A CN109190276A (en) | 2018-09-14 | 2018-09-14 | FPGA prototype verification system |
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| CN112989757A (en) * | 2021-05-10 | 2021-06-18 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
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| CN113326227A (en) * | 2021-08-03 | 2021-08-31 | 上海国微思尔芯技术股份有限公司 | Link multiplexing method, system and prototype verification method |
| CN114301854A (en) * | 2021-02-05 | 2022-04-08 | 井芯微电子技术(天津)有限公司 | PCIe switching equipment |
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| CN116155372A (en) * | 2023-04-17 | 2023-05-23 | 湖南泛联新安信息科技有限公司 | Multi-FPGA prototype verification system based on optical switching |
| BE1029108B1 (en) * | 2022-05-07 | 2023-08-10 | Chao Chang | SYSTEM AND METHOD FOR PROTOTYPE VERIFICATION FOR INTEGRATED CIRCUIT BASED ON FPGA |
| CN116737624A (en) * | 2023-06-06 | 2023-09-12 | 成都立思方信息技术有限公司 | High-performance data access device |
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Cited By (14)
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| CN114301854A (en) * | 2021-02-05 | 2022-04-08 | 井芯微电子技术(天津)有限公司 | PCIe switching equipment |
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| CN112989757A (en) * | 2021-05-10 | 2021-06-18 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
| CN113326227A (en) * | 2021-08-03 | 2021-08-31 | 上海国微思尔芯技术股份有限公司 | Link multiplexing method, system and prototype verification method |
| CN114626326A (en) * | 2022-03-19 | 2022-06-14 | 北京汤谷软件技术有限公司 | FPGA prototype verification device and verification system |
| BE1029108B1 (en) * | 2022-05-07 | 2023-08-10 | Chao Chang | SYSTEM AND METHOD FOR PROTOTYPE VERIFICATION FOR INTEGRATED CIRCUIT BASED ON FPGA |
| CN115454905A (en) * | 2022-08-22 | 2022-12-09 | 杭州未名信科科技有限公司 | PCIE interface card for chip FPGA prototype verification stage |
| CN115454905B (en) * | 2022-08-22 | 2024-02-20 | 杭州未名信科科技有限公司 | PCIE interface card for chip FPGA prototype verification stage |
| CN116155372A (en) * | 2023-04-17 | 2023-05-23 | 湖南泛联新安信息科技有限公司 | Multi-FPGA prototype verification system based on optical switching |
| CN116155372B (en) * | 2023-04-17 | 2023-07-11 | 湖南泛联新安信息科技有限公司 | Multi-FPGA prototype verification system based on optical switching |
| CN116737624A (en) * | 2023-06-06 | 2023-09-12 | 成都立思方信息技术有限公司 | High-performance data access device |
| CN116737624B (en) * | 2023-06-06 | 2024-03-12 | 成都立思方信息技术有限公司 | High-performance data access device |
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