CN112989757A - Method and storage medium for numbering a plurality of prototype verification boards - Google Patents
Method and storage medium for numbering a plurality of prototype verification boards Download PDFInfo
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Abstract
The present disclosure provides a method and storage medium for numbering a plurality of prototype verification boards. The plurality of prototype verification boards include a first verification board, a second verification board connected with the first verification board, and a third verification board connected with the second verification board, the method comprising: receiving a first numbering instruction at a first verification board; in response to receiving the first numbering instruction at the first verification board, setting, by the first verification board, the first verification board to the first number and sending a second numbering instruction to the second verification board; in response to receiving the second numbering instruction at the second verification board, setting, by the second verification board, the second verification board to the second number and sending a third numbering instruction to a third verification board; in response to receiving the third numbering instruction at the third verification board, setting the third verification board to be the third number by the third verification board; and sending the first number, the second number, and the third number to the host.
Description
Technical Field
The present disclosure relates to the field of computer software technologies, and in particular, to a method and a storage medium for numbering a plurality of prototype verification boards.
Background
As chip designs grow in size, the need for prototyping of chip designs cannot be met with only one prototype verification board. Typically, a chip design needs to be divided into multiple parts and loaded into multiple prototype boards for prototype verification, respectively, and a certain prototype board may be operated separately. Furthermore, the number of prototype verification boards that need to be used often varies from verification project to verification project. Although each prototype verification board has its unique identification code (e.g., MAC address), it is relatively difficult for a user (even a host computer connected to the verification board) to determine the prototype verification board that he or she is operating with a complex identification code, increasing the management difficulty of the prototype verification board.
Disclosure of Invention
In view of the above, the present disclosure proposes a method and a storage medium for numbering a plurality of prototype verification boards.
In a first aspect of the present disclosure, a method for numbering a plurality of prototype verification boards is provided, wherein the plurality of prototype verification boards comprises a first verification board, a second verification board connected with the first verification board, and a third verification board connected with the second verification board, the method comprising: receiving a first numbering instruction at the first verification board; in response to receiving the first numbering instruction at the first verification board, setting, by the first verification board, the first verification board to a first number and sending a second numbering instruction to the second verification board, wherein the second numbering instruction further comprises information about the first number; in response to receiving the second numbering instruction at the second verification board, setting, by the second verification board, the second verification board to a second number and sending a third numbering instruction to the third verification board, wherein the third numbering instruction further comprises information about the second number; setting, by the third verification board, the third verification board to a third number in response to receiving the third numbering instruction at the third verification board; and sending the first number, the second number, and the third number to a host.
In a second aspect of the disclosure, a non-transitory computer-readable storage medium is provided, which stores a set of instructions of an electronic device for causing the electronic device to perform the method of the first aspect.
According to the method and the storage medium for numbering the plurality of prototype verification plates, after the first verification plate receives the first numbering instruction, the first verification plate sets the first verification plate to be a first number, and sends the second numbering instruction to the second verification plate; after the second numbering instruction receives the second numbering instruction, the second verification board sets the second numbering instruction as the second numbering, and sends a third numbering instruction to a third verification board; after the third verification board receives the third serial number instruction, the third verification board sets the third verification board to be the third serial number, and therefore the plurality of prototype verification boards are numbered, and the first serial number, the second serial number and the third serial number are sent to the host to be stored. Like this, when prototype verification is carried out to chip design, can pinpoint this prototype verification board according to the serial number of the prototype verification board of being operated to can reduce prototype verification's the degree of difficulty, improve prototype verification's efficiency, and reduced the management degree of difficulty to prototype verification board.
Drawings
In order to more clearly illustrate one or more embodiments or prior art solutions of the present specification, the drawings that are needed in the description of the embodiments or prior art will be briefly described below, and it is obvious that the drawings in the following description are only one or more embodiments of the present specification, and that other drawings may be obtained by those skilled in the art without inventive effort from these drawings.
Fig. 1 shows a schematic structural diagram of an exemplary verification system according to an embodiment of the present disclosure.
FIG. 2A illustrates a schematic diagram of the connection of an exemplary plurality of prototype verification boards, according to an embodiment of the present disclosure.
FIG. 2B illustrates a schematic diagram of the connection of yet another exemplary plurality of prototype verification boards, according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of an exemplary numbered topology according to an embodiment of the present disclosure.
Fig. 4 illustrates a flow diagram of an exemplary method for numbering a plurality of prototype verification boards provided by embodiments of the present disclosure.
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
It is to be noted that unless otherwise defined, technical or scientific terms used in one or more embodiments of the present specification should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in one or more embodiments of the specification is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
As described above, it is difficult to manage a variable number of prototype verification boards in a conventional manner.
In view of the above, the disclosed embodiments provide a method for numbering a plurality of prototype verification boards, wherein the plurality of prototype verification boards includes a first verification board, a second verification board connected to the first verification board, and a third verification board connected to the second verification board, the method comprising: receiving a first numbering instruction at the first verification board; in response to receiving the first numbering instruction at the first verification board, setting, by the first verification board, the first verification board to a first number and sending a second numbering instruction to the second verification board, wherein the second numbering instruction further comprises information about the first number; in response to receiving the second numbering instruction at the second verification board, setting, by the second verification board, the second verification board to a second number and sending a third numbering instruction to the third verification board, wherein the third numbering instruction further comprises information about the second number; setting, by the third verification board, the third verification board to a third number in response to receiving the third numbering instruction at the third verification board; and sending the first number, the second number, and the third number to a host.
According to the method for numbering the plurality of prototype verification plates, after the first verification plate receives the first numbering instruction, the first verification plate sets the first verification plate to be a first number, and sends the second numbering instruction to the second verification plate; after the second numbering instruction receives the second numbering instruction, the second verification board sets the second numbering instruction as the second numbering, and sends a third numbering instruction to a third verification board; after the third verification board receives the third serial number instruction, the third verification board sets the third verification board to be the third serial number, and therefore the plurality of prototype verification boards are numbered, and the first serial number, the second serial number and the third serial number are sent to the host to be stored. Like this, when prototype verification is carried out to chip design, can pinpoint this prototype verification board according to the serial number of the prototype verification board of being operated to can reduce prototype verification's the degree of difficulty, improve prototype verification's efficiency, and reduced the management degree of difficulty to prototype verification board.
FIG. 1 illustrates a schematic diagram of an exemplary verification system 100, in accordance with embodiments of the present disclosure.
As shown in FIG. 1, the verification system 100 may include a host computer 102 and a plurality of prototype verification boards 112 and 118.
The host 102 may be a computing device (e.g., a desktop computer, a notebook computer, etc.) having a processor and memory. The host 102 may send instructions (e.g., prototype verification instructions, numbering instructions, etc.) to the plurality of prototype verification boards 112-118, and the plurality of prototype verification boards 112-118 perform corresponding operations according to the received instructions. For example, the host 102 sends a prototype verification execution instruction to the plurality of prototype verification boards 112-118, and after the plurality of prototype verification boards 112-118 receive the prototype verification execution instruction, the plurality of prototype verification boards can execute a method for designing a prototype by building a System On Chip (SOC) and an Application Specific Integrated Circuit (ASIC) on a Field Programmable Gate Array (FPGA), so that hardware verification and early software development can be conveniently performed, development of designs such as ASICs is accelerated, a development cycle is shortened, development cost of an ASIC Application System is reduced, and a success rate of stream files is improved.
The host computer 102 may be connected to a plurality of prototype verification boards 112-118, and the plurality of prototype verification boards 112-118 may be connected in series via a serial bus. Wherein the plurality of prototype verification boards 112-118 includes a verification board 112, a verification board 114 connected to the verification board 112, and a verification board 116 connected to the verification board 114. It is understood that in an actual verification system, since the plurality of prototype verification boards respectively simulate a plurality of modules of the chip design, and a large amount of data communication exists among the plurality of modules of the chip design, a parallel bus connection may also exist among the plurality of prototype verification boards 112 and 118 for data communication among each other. In the actual operation of a plurality of prototype verification boards, it is difficult for a user (even a host computer connected to the verification boards) to determine on which prototype verification board the current operation is specific, and it is necessary to distinguish and manage each prototype verification board by a special identification in order to accurately locate the operated prototype verification board.
Wherein the special identifier may be a different number. The numbers may be letters, numbers, etc.
FIG. 2A shows a schematic diagram of an exemplary multiple prototype verification board connection 210, according to an embodiment of the present disclosure.
As shown in fig. 2A, a plurality of prototype verification boards 112-116 may be connected in series via a serial bus. Different numbers are used as special identifications for distinguishing and managing the prototype verification plates, and a numbering instruction can be sent to the prototype verification plate needing numbering through the host machine, so that the prototype verification plate needing numbering completes numbering for the prototype verification plate according to the numbering instruction. Since the plurality of prototype verification boards 112-116 may forward the numbering instruction over the serial bus, the verification board that first received the numbering instruction (e.g., the verification board 112) among the plurality of prototype verification boards 112-116 may be determined as the initial verification board. For example, when verification board 112 receives a numbering command from host 102, verification board 112 may determine that the numbering command does not include any numbering information and thus confirm that verification board 112 is itself the initial verification board. Where the initial verification board has no upper level verification board, only the lower level verification board (i.e., verification board 114) connected to its downstream interface 1124. For example, the upstream interface 1122 of the prototype verification board 112 is connected to and communicates with the host 102.
It will be appreciated that other ways of determining the initial authentication plate may be used. For example, an instruction may be sent by the host 102 to traverse the plurality of prototype verification boards 112-116 to determine that the verification board 112 is an initial verification board.
In some embodiments, the numbering instruction 202 may be sent by the host 102 to the verification board 112, and upon receipt of the numbering instruction 202 at the verification board 112, the verification board 112 may set itself with a unique number. For example, the verification board 112 may set itself with the number "000". And verification board 112 may call its downstream interface 1124 to send numbering instructions 204 to the verification board 114 to which it is connected, where numbering instructions 204 may include information about the number of verification board 112. For example, the number instruction 204 may include a verification board 112 number "000".
When the serial number instruction 204 is received by the upstream interface 1142 of the verification board 114, the verification board 114 may set itself another serial number different from the rest of the prototype verification board serial numbers. For example, verification board 114 may set itself with a number "001" in order based on the number "000" of verification board 112. And the verification board 114 may call its downstream interface 1144 to send a numbering instruction 206 to the verification board 116 to which it is connected, where the numbering instruction 206 may include information about the number of the verification board 114. For example, the number instruction 206 may include a verification board 114 number "001".
Similarly, when the numbering instruction 206 is received by the upstream interface 1162 of the verification board 116, the verification board 116 may set itself another number that is different from the rest of the prototype verification board numbers. For example, verification board 116 may sequentially set itself to number "002" based on verification board 114 number "001". The verification board 116 may be a termination verification board, and after the verification board 116 numbers itself, the downlink interface of the verification board 116 is no longer called to continue sending the numbering instruction. Where the termination verification board has only the superior verification board (i.e., verification board 114) connected to its upstream interface 1162 and no inferior verification board. At this point, the verification board 112 number, verification board 114 number, and verification board 116 number may be sent to host 102 for storage.
It should be noted that the plurality of prototype verification panels 112-116 may determine whether they themselves have been numbered. For a prototype verification board with a number already set, the prototype verification board receiving the number instruction will not set a new number for itself again.
Since the plurality of prototype verification boards do not include only serial connections therebetween, FIG. 2B shows a schematic diagram of a connection pattern 230 for yet another exemplary plurality of prototype verification boards according to an embodiment of the present disclosure.
As shown in fig. 2B, a plurality of prototype verification boards 112a-118c are configured with a plurality of series lines therebetween. Since some or some of the prototype verification boards may be unavailable in actual operation, if a plurality of prototype verification boards 112a to 118c are numbered only by a single serial line, and an unavailable prototype verification board appears on the serial line, the numbering instruction cannot be forwarded continuously, so that the numbering of the plurality of prototype verification boards 112a to 118c cannot be completed.
Thus, the authentication board 112a may connect a plurality of lower authentication boards (e.g., 112b, 114a, 114b, and 114 c). It is understood that when the verification capabilities of multiple prototype verification boards are provided in the form of a cloud service, it is uncertain whether each prototype verification board has not been used by a customer at the current time.
In some embodiments, host 102 may send a numbering instruction to verification board 112 a. The verification board 112a may then determine whether the verification board 112a itself is usable. When the verification board 112a is available, then the verification board 112a may number itself upon receiving the numbering instruction 212 sent by the host 102; when verification board 112a is not available, then verification board 112a may forward numbering instructions 212 to a target verification board of the plurality of lower verification boards. For example, when verification board 112a is not available, verification board 112a may forward number instructions 212 to target verification board 112 b.
In some embodiments, it may further be determined whether the selected target verification board is available. When the target verification board is available, the target verification board sends confirmation information to the verification board 112a and numbers itself according to the received numbering instruction 212; when the target verification board is not available, then the numbering instruction 212 is forwarded by verification board 112a to another target verification board of the plurality of lower verification boards that is different from the target verification board. For example, when target verification board 112b is not available, verification board 112a may forward number instructions 212 to target verification board 114 a. Therefore, when the prototype verification board which needs numbering and forwards the numbering instruction downwards is unavailable, the numbering instruction can be forwarded to other available prototype verification boards, the available prototype verification boards execute the numbering instruction, and the numbering instruction is continuously forwarded to other prototype verification boards to complete the numbering of the plurality of prototype verification boards.
In some embodiments, any authentication board, after being used by a user, will send a message to host 102 informing host 102 that the authentication board is already occupied. Thus, when host 102 receives a new authentication request, host 102 may select a number of available authentication boards for providing authentication capabilities to the user by determining a scheme (i.e., a path for the numbered instructions) for connecting the authentication boards based on the current availability status of the authentication boards. The host 102 may accordingly send a serial number command to an initial verification board (or a higher level verification board) in the transfer path, and the initial verification board transfers downward step by step according to the transfer path. Accordingly, the numbering instructions may include verifying this connection scheme of the board. In some embodiments, multiple prototype verification boards may be selected for numbering based on the user's requirements for the number of prototype verification boards. For example, if the user wants 5 prototype verification boards satisfying his needs, the verification board 112a may set a number "000" for itself according to the received number command 212 sent by the host 102, and then forward the number command 214 to the verification board 114 b; after the number "001" is set for the verification board 114b according to the received number instruction 214, the number instruction 216 is forwarded to the verification board 116 b; after the number "002" is set for the verification board 116b according to the received number instruction 216, the number instruction 218 is forwarded to the verification board 116 a; after the number "003" is set for itself by the verification board 116a according to the received number instruction 218, the number instruction 220 is forwarded to the verification board 118 a; the verification board 118a sets a serial number "004" for itself according to the received serial number command 220, and finally sends the serial numbers of the 5 prototype verification boards (namely, the verification boards 112a, 114b, 116a and 118 a) to the host computer, so that the user can know the serial number of the prototype verification board selected by the user.
Fig. 3 shows a schematic diagram of an exemplary numbered topology 300 in accordance with an embodiment of the present disclosure.
As shown in fig. 3, after the numbering operation is completed on the plurality of prototype verification boards, the host 102 may obtain the connection relationships of the plurality of prototype verification boards (e.g., 112a is connected to 112b, 114a, 114b, and 114c, respectively), and establish a numbering topology 300 with the connection relationships corresponding to the numbers (e.g., 000, 001, 002). For the user, only one numbered topological graph 300 can be seen, which is very simple and clear, thereby facilitating the operation of the user. In addition, because every verification board all knows the serial number of self after the operation of numbering, consequently every verification board can also carry out some corresponding operations according to self serial number.
In some embodiments, host 102 may analyze occupancy information for multiple prototype verification boards, providing a number of prototype verification boards that meets requirements based on numbering plan 300 and numbering inquiry requests. The prototype verification board meeting the requirements can be a prototype verification board with occupation information not higher than preset occupation amount. For example, the occupation information may be a resource occupation ratio, the host 102 determines the resource occupation ratios of a plurality of prototype verification boards through analysis, and if a user wants to know the number of the prototype verification board of which the current remaining resources satisfy the prototype verification requirement, a number query request is sent to the host 102, and the host 102 determines, according to the number query request, a number corresponding to the prototype verification board of which the resource occupation ratio is not higher than a preset occupation amount (for example, the resource occupation ratio is 30%) in the number topological graph 300, and provides the number to the user, so that the user can select the prototype verification board required to be operated according to the number.
In the verification system 100, the number of prototype verification boards may be increased or decreased, and the added prototype verification boards may be added to any one of the series lines. After the number of the prototype verification boards changes, the numbers of the plurality of prototype verification boards after the number change can be determined again, and the corresponding relationship between the connection relationship and the numbers in the numbering topological graph 300 is modified correspondingly.
Fig. 4 illustrates a flow diagram of an exemplary method 400 for numbering a plurality of prototype verification boards provided by embodiments of the present disclosure. The method 400 may be performed by the plurality of prototype verification boards.
A method 400 for numbering a plurality of prototype verification boards, wherein the plurality of prototype verification boards (e.g., verification board 112 of fig. 1 and 118) comprises a first verification board (e.g., verification board 112 of fig. 2A), a second verification board connected to the first verification board (e.g., verification board 114 of fig. 2A), and a third verification board connected to the second verification board (e.g., verification board 116 of fig. 2A) provided by embodiments of the present disclosure, the method 400 may comprise the following steps.
At step 402, a first numbering instruction (e.g., numbering instruction 202 in fig. 2A) may be received at the first verification board.
In some embodiments, it may occur that some or a portion of the prototype verification board is not available for use in actual operation. Thus, multiple prototype boards may be connected in a manner that not only does there be a single line of serial connection, there may also be multiple prototype boards (e.g., prototype boards 112a-118c in FIG. 2B) connected by multiple serial lines. A first verification board (e.g., verification board 112a in fig. 2B) may connect multiple lower level verification boards (e.g., verification boards 112B, 114a, 114B, or 114c in fig. 2B). In some embodiments, receiving the first numbering instruction at the first verification board further comprises: determining whether the first verification board is available; and in response to the first verification board being unavailable, forwarding, by the first verification board, the first numbering instruction to a first target verification board (e.g., verification board 112B in fig. 2B) of the plurality of lower verification boards. In still other embodiments, the first numbering instruction may include a scheme of interfacing a verification board for selecting a target verification board among the plurality of lower verification boards to forward the first numbering instruction thereto.
In some embodiments, it may be further determined whether the selected first target verification board is available, since a problem may arise that the first target verification board is still unavailable. Responsive to the first verification board being unavailable, forwarding, by the first verification board, the first numbering instruction to a first target verification board of the plurality of lower verification boards further comprises: determining whether the first target verification board is available; and in response to the first target verification board being available, sending a confirmation message to the first verification board; or in response to the first target verification board being unavailable, forwarding, by the first verification board, the first numbering instruction to a second target verification board of the plurality of lower verification boards (e.g., verification board 114a in fig. 2B).
At step 404, in response to receiving the first numbering instruction at the first verification board, the first verification board may be set to a first number (e.g., number "000" in fig. 2A) by the first verification board and a second numbering instruction (e.g., numbering instruction 204 in fig. 2A) is sent to the second verification board, wherein the second numbering instruction further includes information about the first number. It will be appreciated that in some embodiments, the first numbering instruction forwarded by the first verification board may be considered the second numbering instruction.
In some embodiments, the first verification board may be an initial verification board, the method further may include: traversing the plurality of prototype verification boards to determine that the first verification board is the initial verification board; and invoking a downstream interface (e.g., downstream interface 1124 in fig. 2A) of the verification board to send the second numbering instruction to the second verification board.
At step 406, in response to receiving the second numbering instruction at the second verification board, the second verification board may be set to a second number (e.g., number "001" in fig. 2A) by the second verification board and a third numbering instruction (e.g., numbering instruction 206 in fig. 2A) may be sent to the third verification board, wherein the third numbering instruction further includes information about the second number. It will be appreciated that in some embodiments, the second numbered instruction forwarded by the second verification board may be considered the third numbered instruction.
At step 408, in response to receiving the third numbering instruction at the third verification board, the third verification board may be set to a third number (e.g., number "002" in FIG. 2A) by the third verification board.
In some embodiments, the third verification board may be a termination verification board, and the method may further comprise: receiving the third numbering instruction via an upstream interface (e.g., upstream interface 1162 in fig. 2A) of the third verification board.
At step 410, the first number, the second number, and the third number may be sent to a host (e.g., host 102 in fig. 1).
As described above, after determining the numbers of the plurality of prototype verification boards, the user can further know the number and the specific position of the operated prototype verification board, thereby more precisely positioning the operated prototype verification board. Thus, in some embodiments, the method may further comprise: obtaining connection relationships of the plurality of prototype verification boards (e.g., verification board 112a is connected with verification boards 112B, 114a, 114B, and 114c, respectively, in fig. 2B); establishing a numbering topological graph (for example, the numbering topological graph 300 in the figure 3) of the connection relation corresponding to the number; and responding to the received number inquiry request, and providing the number of the prototype verification board according to the number topological graph.
In some embodiments, if the user wants to select a part of the prototype verification boards among the prototype verification boards satisfying the user's needs to perform corresponding operations, providing the number of the prototype verification board according to the number topology map in response to receiving the number inquiry request may further include: analyzing the occupancy information of the plurality of prototype verification boards; and providing the serial number of the prototype verification board with the occupation information not higher than the preset occupation amount according to the serial number topological graph and the serial number inquiry request.
As described above, any number of prototype verification boards may be added or subtracted in any one serial line in a verification system (e.g., verification system 100 in FIG. 1). After the number of prototype verification boards changes, the method 400 may be executed again to re-determine the numbers of the plurality of prototype verification boards after the number changes, and accordingly modify the correspondence between the connection relationships and the numbers in the numbering topology 300.
According to the method and the storage medium for numbering the plurality of prototype verification plates, after the first verification plate receives the first numbering instruction, the first verification plate sets the first verification plate to be a first number, and sends the second numbering instruction to the second verification plate; after the second numbering instruction receives the second numbering instruction, the second verification board sets the second numbering instruction as the second numbering, and sends a third numbering instruction to a third verification board; after the third verification board receives the third serial number instruction, the third verification board sets the third verification board to be the third serial number, and therefore the plurality of prototype verification boards are numbered, and the first serial number, the second serial number and the third serial number are sent to the host to be stored. Like this, when prototype verification is carried out to chip design, can pinpoint this prototype verification board according to the serial number of the prototype verification board of being operated to can reduce prototype verification's the degree of difficulty, improve prototype verification's efficiency, and reduced the management degree of difficulty to prototype verification board.
It should be noted that the method of the present disclosure may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In the case of such a distributed scenario, one of the plurality of devices may only perform one or more steps of the method of the present disclosure, and the plurality of devices may interact with each other to complete the method.
Embodiments of the present disclosure also provide computer-readable storage media storing instructions. The instructions, when executed by the electronic device, are for performing the above-described method. The computer readable storage media, including both permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
The foregoing description of specific embodiments of the present disclosure has been described. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.
In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.
The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.
Claims (10)
1. A method for numbering a plurality of prototype verification boards, wherein the plurality of prototype verification boards comprises a first verification board, a second verification board connected to the first verification board, and a third verification board connected to the second verification board, the method comprising:
receiving a first numbering instruction at the first verification board;
in response to receiving the first numbering instruction at the first verification board, setting, by the first verification board, the first verification board to a first number and sending a second numbering instruction to the second verification board, wherein the second numbering instruction further comprises information about the first number;
in response to receiving the second numbering instruction at the second verification board, setting, by the second verification board, the second verification board to a second number and sending a third numbering instruction to the third verification board, wherein the third numbering instruction further comprises information about the second number;
setting, by the third verification board, the third verification board to a third number in response to receiving the third numbering instruction at the third verification board; and
sending the first number, the second number, and the third number to a host.
2. The method of claim 1, wherein the first authentication board connects a plurality of lower authentication boards.
3. The method of claim 2, wherein receiving the first numbering instruction at the first verification board further comprises:
determining whether the first verification board is available; and
forwarding, by the first verification board, the first numbering instruction to a first target verification board of the plurality of subordinate verification boards in response to the first verification board being unavailable.
4. The method of claim 3, wherein said forwarding, by said first verification board, said first numbering instruction to a first target verification board of said plurality of lower verification boards in response to said first verification board being unavailable further comprises:
determining whether the first target verification board is available; and
sending a confirmation message to the first verification board in response to the first target verification board being available; or
Forwarding, by the first verification board, the first numbering instruction to a second target verification board of the plurality of subordinate verification boards in response to the first target verification board being unavailable.
5. The method of claim 1, wherein the first authentication plate is an initial authentication plate, the method further comprising:
traversing the plurality of prototype verification boards to determine that the first verification board is the initial verification board; and
and calling a downlink interface of the verification board to send the second serial number instruction to the second verification board.
6. The method of claim 1, wherein the third verification board is a termination verification board, the method further comprising:
receiving the third numbering instruction via an upstream interface of the third verification board.
7. The method of claim 1, further comprising:
acquiring the connection relation of the plurality of prototype verification boards;
establishing a number topological graph corresponding to the connection relation and the number; and
and responding to the received number inquiry request, and providing the number of the prototype verification board according to the number topological graph.
8. The method of claim 7, wherein said providing the number of the prototype verification board from the numbering topology in response to receiving a numbering inquiry request further comprises:
analyzing the occupancy information of the plurality of prototype verification boards; and
and providing the serial number of the prototype verification board with the occupation information not higher than the preset occupation amount according to the serial number topological graph and the serial number query request.
9. The method of claim 2, wherein said first numbering instruction comprises a scheme of interfacing a verification board for selecting a target verification board among said plurality of lower level verification boards to forward said first numbering instruction thereto.
10. A non-transitory computer readable storage medium storing a set of instructions of an electronic device for causing the electronic device to perform the method of any one of claims 1 to 9.
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