CN203025709U - Clock synchronization device for field programmable gate array (FPGA) prototype verification board stack - Google Patents
Clock synchronization device for field programmable gate array (FPGA) prototype verification board stack Download PDFInfo
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- CN203025709U CN203025709U CN2013200318316U CN201320031831U CN203025709U CN 203025709 U CN203025709 U CN 203025709U CN 2013200318316 U CN2013200318316 U CN 2013200318316U CN 201320031831 U CN201320031831 U CN 201320031831U CN 203025709 U CN203025709 U CN 203025709U
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Abstract
The embodiment of the utility model discloses a clock synchronization device for field programmable gate array (FPGA) prototype verification board stack. The device comprises a master FPGA verification board and at least one slave FPGA prototype verification board, wherein the master FPGA verification board and the slave FPGA prototype verification board respectively comprise a clock chip, a master control chip, at least one slave FPGA chip and a high-speed interface; and the master control chip comprises a local clock input pin, a stack clock input pin, a selection signal input pin, a feedback clock input pin, a slave FPGA clock synchronization clock signal output pin, a feedback clock synchronization clock signal output pin and a high-speed interface synchronization clock signal output pin. The device is used for the high-speed interface stack and phase-locked loop feedback in the master control chips, so that clocks output by the multi-layer FPGA prototype verification board to all the slave FPGA chips can be synchronous.
Description
Technical field
The utility model belongs to FPGA prototype verification technical field, relates to especially a kind of clock synchronization apparatus of FPGA prototype verification stack of plates.
Background technology
field programmable gate array (Field Program Gate Array, FPGA) prototype verification is a kind of SOC (system on a chip) (System on Chip that builds on FPGA, SOC) and special IC (ApplicationSpecific Integrated Circuit, ASIC) methodology of prototype, can carry out easily hardware verification and early stage software development, the method is also referred to as ASIC prototype verification or SOC prototype verification, can accelerate the exploitation of the designs such as ASIC, shorten the R﹠D cycle, reduce the cost of development of ASIC application system, improved the success ratio of flow.
In FPGA prototype verification field, when the capacity of the fpga logic door of veneer does not also reach user's logic demand, tend to adopt stacking method.FPGA can realize by the connection of interconnection IO the mutual transmission of signal.When designing the stacking scheme of FPGA prototype verification plate, it is very important that the design of clock synchronous seems.Consider complicated SOC/ASIC design, need multiple-plate FPGA to work in coordination with and complete, will inevitably produce the demand of synchronous clock source.The quality of the synchronizing quality of FPGA prototype verification plate clock source has often directly determined the complexity that verifiable SOC/ASIC designs.
In prior art, in FPGA prototype verification field, the realization of clock synchronous by sharing single crystal oscillator, perhaps shares single programmable clock often, unanimously realizes multiple FPGA clock synchronous in lamina by clock source to the PCB cabling of each sheet FPGA.Also need to realize clock synchronous by means of the equal connecting line of time-delay for multilayer board.This method both had been subject to the restriction of single crystal oscillator or the shared pin of single programmable clock, also was subject to the impact of connecting line quality, and the quantity of synchronous clock is difficult to flexible change, and quality also can not be guaranteed.
The utility model content
For addressing the above problem, the purpose of this utility model is to provide a kind of clock synchronization apparatus of FPGA prototype verification stack of plates, be used for phaselocked loop feedback in and main control chip stacking by high-speed interface, make multilayer PFGA prototype verification plate export to respectively and realize synchronous from the clock of fpga chip.
For achieving the above object, the technical solution of the utility model is:
a kind of clock synchronization apparatus of FPGA prototype verification stack of plates, comprise that main FPGA prototype verification plate and at least one are from FPGA prototype verification plate, described main FPGA prototype verification plate and comprise clock chip from FPGA prototype verification plate, main control chip, at least one is from fpga chip and high-speed interface, described main control chip comprises the local clock input pin, stacking clock input pin, select the signal input pin, the feedback clock input pin, from FPGA clock synchronous clock signal output pin, feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin,
wherein select the signal input pin to connect input high-low level signal, feedback clock synchronizing clock signals output pin exports the feedback clock input pin to, input to corresponding to fpga chip from FPGA clock synchronous clock signal output pin, high-speed interface synchronizing clock signals output pin on main FPGA prototype verification plate exports the high-speed interface on it to, high-speed interface on main FPGA prototype verification plate is connected with high-speed interface from FPGA prototype verification plate, high-speed interface from the FPGA prototype verification plate exports the stacking clock input pin from the FPGA prototype verification plate to.
Preferably, wherein main control chip further comprises the first data selector, the second data selector, and Clock Managing Unit and global clock impact damper,
Two input ports of described the first data selector by the stacking clock input signal of stacking clock input pin input, connect high-low level signal by selecting the signal input pin respectively by the local crystal oscillator clock signal of local clock input pin input;
Two input ports of described the second data selector connect the high-low level signal by feedback clock input pin input feedback clock input signal by selecting the signal input pin;
The output signal of the output port of described the first data selector inputs to the input end of clock mouth of Clock Managing Unit, and the output signal of the output port of the second data selector inputs to the feedback clock input port of Clock Managing Unit;
the output signal of the output port of described Clock Managing Unit inputs to the global clock impact damper, again by global clock impact damper output multi-channel synchronizing clock signals, by exporting FPGA clock synchronous clock signal from FPGA clock synchronous clock signal output pin extremely from fpga chip, by high-speed interface synchronizing clock signals output pin output high-speed interface synchronizing clock signals, export the feedback clock synchronizing clock signals to the feedback clock input pin by feedback clock synchronizing clock signals output pin, the phaselocked loop of Clock Managing Unit is adjusted input end of clock mouth and the same homophase frequently of feedback clock input port of Clock Managing Unit.
Preferably, the phaselocked loop of described Clock Managing Unit is digital phase-locked loop or analog phase-locked look.
Compared with prior art, the utlity model has following technique effect:
(1) the interior phaselocked loop feedback of and main control chip stacking by high-speed interface makes multilayer PFGA prototype verification plate export to respectively synchronous from the clock realization of fpga chip, has increased the extended capability of clock synchronous;
(2) by adopting clock signal that clock chip produces as source signal on main FPGA prototype verification plate, the clock signal of exporting from the employing of FPGA prototype verification plate from main FPGA prototype verification plate is as clock signal, realized more effective clock synchronous, the clock synchronous error of avoiding.
Description of drawings
Fig. 1 is the structure principle chart of clock synchronization apparatus of the FPGA prototype verification stack of plates of the utility model embodiment;
Fig. 2 is the structure principle chart of main control chip of clock synchronization apparatus of the FPGA prototype verification stack of plates of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
On the contrary, the utility model contain any by claim definition make on marrow of the present utility model and scope substitute, modification, equivalent method and scheme.Further, in order to make the public, the utility model is had a better understanding, in hereinafter details of the present utility model being described, detailed some specific detail sections of having described.Do not have for a person skilled in the art the description of these detail sections can understand the utility model fully yet.
The structure principle chart of clock synchronization apparatus with reference to the FPGA prototype verification stack of plates that Figure 1 shows that the utility model embodiment, for simplied system structure, the technical solution of the utility model is described from the FPGA witness plate as example to comprise a main FPGA prototype verification plate and one in diagram.Those skilled in the art it should be understood that, it does not limit the number of the FPGA prototype verification plate that can comprise in the utility model embodiment.it comprises that a main FPGA prototype verification plate and one are from FPGA prototype verification plate, main FPGA prototype verification plate and comprise clock chip from FPGA prototype verification plate, main control chip, at least one is from fpga chip and high-speed interface, main control chip comprises the local clock input pin, stacking clock input pin, select the signal input pin, the feedback clock input pin, from FPGA clock synchronous clock signal output pin, feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin, wherein select the signal input pin to connect input high-low level signal, feedback clock synchronizing clock signals output pin exports the feedback clock input pin to, input to corresponding to fpga chip from FPGA clock synchronous clock signal output pin, high-speed interface synchronizing clock signals output pin on main FPGA prototype verification plate exports the high-speed interface on it to, high-speed interface on main FPGA prototype verification plate is connected with high-speed interface from FPGA prototype verification plate, high-speed interface from the FPGA prototype verification plate exports the stacking clock input pin from the FPGA prototype verification plate to.
with reference to figure 2, be depicted as the structure principle chart of main control chip 10 wherein, it further comprises the first data selector 101, the second data selector 102, Clock Managing Unit 103 and global clock impact damper 104, the local crystal oscillator clock signal that two input ports of the first data selector produce by local clock input pin 105 input clock chips respectively, by the stacking clock input pin 106 stacking clock input signals of input, connect the high-low level signal by selecting signal input pin 107, two input ports of the second data selector 102 connect the high-low level signal by feedback clock input pin 108 input feedback clock input signals by selecting signal input pin 107, the output signal of the output port of the first data selector 101 inputs to the input end of clock mouth CLKIN of Clock Managing Unit 103, and the output signal of the output port of the second data selector 102 inputs to the feedback clock input port CLKFB of Clock Managing Unit 103, the output signal of the output port of Clock Managing Unit inputs to global clock impact damper 104, again by global clock impact damper output multi-channel synchronizing clock signals, as shown in FIG., export FPGA clock synchronous clock signals to the first from fpga chip by first from FPGA clock synchronous clock signal output pin 112, export FPGA clock synchronous clock signals to the second from fpga chip by second from FPGA clock synchronous clock signal output pin 111, by high-speed interface synchronizing clock signals output pin 110 output high-speed interface synchronizing clock signals, export the feedback clock synchronizing clock signals to the feedback clock input pin by feedback clock synchronizing clock signals output pin 109, the phaselocked loop of Clock Managing Unit is adjusted input end of clock mouth and the same homophase frequently of feedback clock input port of Clock Managing Unit.In concrete application example, the phaselocked loop of Clock Managing Unit is digital phase-locked loop or analog phase-locked look.
The above is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (3)
1. the clock synchronization apparatus of a FPGA prototype verification stack of plates, comprise that main FPGA prototype verification plate and at least one are from FPGA prototype verification plate, it is characterized in that, described main FPGA prototype verification plate and comprise clock chip from FPGA prototype verification plate, main control chip, at least one is from fpga chip and high-speed interface, described main control chip comprises the local clock input pin, stacking clock input pin, select the signal input pin, the feedback clock input pin, from FPGA clock synchronous clock signal output pin, feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin,
wherein select the signal input pin to connect input high-low level signal, feedback clock synchronizing clock signals output pin exports the feedback clock input pin to, input to corresponding to fpga chip from FPGA clock synchronous clock signal output pin, high-speed interface synchronizing clock signals output pin on main FPGA prototype verification plate exports the high-speed interface on it to, high-speed interface on main FPGA prototype verification plate is connected with high-speed interface from FPGA prototype verification plate, high-speed interface from the FPGA prototype verification plate exports the stacking clock input pin from the FPGA prototype verification plate to.
2. the clock synchronization apparatus of FPGA prototype verification stack of plates according to claim 1, is characterized in that,
Wherein main control chip further comprises the first data selector, the second data selector, and Clock Managing Unit and global clock impact damper,
Two input ports of described the first data selector by the stacking clock input signal of stacking clock input pin input, connect high-low level signal by selecting the signal input pin respectively by the local crystal oscillator clock signal of local clock input pin input;
Two input ports of described the second data selector connect the high-low level signal by feedback clock input pin input feedback clock input signal by selecting the signal input pin;
The output signal of the output port of described the first data selector inputs to the input end of clock mouth of Clock Managing Unit, and the output signal of the output port of the second data selector inputs to the feedback clock input port of Clock Managing Unit;
the output signal of the output port of described Clock Managing Unit inputs to the global clock impact damper, again by global clock impact damper output multi-channel synchronizing clock signals, by exporting FPGA clock synchronous clock signal from FPGA clock synchronous clock signal output pin extremely from fpga chip, by high-speed interface synchronizing clock signals output pin output high-speed interface synchronizing clock signals, export the feedback clock synchronizing clock signals to the feedback clock input pin by feedback clock synchronizing clock signals output pin, the phaselocked loop of Clock Managing Unit is adjusted input end of clock mouth and the same homophase frequently of feedback clock input port of Clock Managing Unit.
3. the clock synchronization apparatus of FPGA prototype verification stack of plates according to claim 2, is characterized in that, the phaselocked loop of described Clock Managing Unit is digital phase-locked loop or analog phase-locked look.
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| CN2013200318316U CN203025709U (en) | 2013-01-21 | 2013-01-21 | Clock synchronization device for field programmable gate array (FPGA) prototype verification board stack |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103105889B (en) * | 2013-01-21 | 2015-07-29 | 杭州乔微电子科技有限公司 | The clock synchronization apparatus that a kind of FPGA prototype verification sheetpile is folded and system |
| CN107168458A (en) * | 2017-06-07 | 2017-09-15 | 苏州瑞迈斯医疗科技有限公司 | A kind of clock distributing equipment for being used to digitize pet detector |
| CN107766599A (en) * | 2016-08-22 | 2018-03-06 | 深圳市中兴微电子技术有限公司 | The prototype verification device of IC chip |
| CN112260684A (en) * | 2020-12-21 | 2021-01-22 | 上海国微思尔芯技术股份有限公司 | Clock alignment system and method for prototype verification system |
| CN112906328A (en) * | 2021-02-05 | 2021-06-04 | 博流智能科技（南京）有限公司 | FPGA prototype verification system generation method and system and FPGA prototype verification method and system |
| CN112989757A (en) * | 2021-05-10 | 2021-06-18 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
| CN113419598A (en) * | 2021-05-18 | 2021-09-21 | 武汉中海庭数据技术有限公司 | Clock synchronization system and method for multi-SOC (system on chip) |
| CN114115438A (en) * | 2020-08-31 | 2022-03-01 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
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2013
- 2013-01-21 CN CN2013200318316U patent/CN203025709U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103105889B (en) * | 2013-01-21 | 2015-07-29 | 杭州乔微电子科技有限公司 | The clock synchronization apparatus that a kind of FPGA prototype verification sheetpile is folded and system |
| CN107766599A (en) * | 2016-08-22 | 2018-03-06 | 深圳市中兴微电子技术有限公司 | The prototype verification device of IC chip |
| CN107168458A (en) * | 2017-06-07 | 2017-09-15 | 苏州瑞迈斯医疗科技有限公司 | A kind of clock distributing equipment for being used to digitize pet detector |
| CN114115438A (en) * | 2020-08-31 | 2022-03-01 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN114115438B (en) * | 2020-08-31 | 2023-07-04 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN112260684A (en) * | 2020-12-21 | 2021-01-22 | 上海国微思尔芯技术股份有限公司 | Clock alignment system and method for prototype verification system |
| CN112906328A (en) * | 2021-02-05 | 2021-06-04 | 博流智能科技（南京）有限公司 | FPGA prototype verification system generation method and system and FPGA prototype verification method and system |
| CN112906328B (en) * | 2021-02-05 | 2024-03-08 | 博流智能科技（南京）有限公司 | FPGA prototype verification system generation method and system, and FPGA prototype verification method and system |
| CN112989757A (en) * | 2021-05-10 | 2021-06-18 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
| CN112989757B (en) * | 2021-05-10 | 2021-09-28 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
| CN113419598A (en) * | 2021-05-18 | 2021-09-21 | 武汉中海庭数据技术有限公司 | Clock synchronization system and method for multi-SOC (system on chip) |
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