CN101872331A - High-speed annular bus protocol adopting node mode - Google Patents
High-speed annular bus protocol adopting node mode Download PDFInfo
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- CN101872331A CN101872331A CN200910049686A CN200910049686A CN101872331A CN 101872331 A CN101872331 A CN 101872331A CN 200910049686 A CN200910049686 A CN 200910049686A CN 200910049686 A CN200910049686 A CN 200910049686A CN 101872331 A CN101872331 A CN 101872331A
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Abstract
The invention relates to a high-speed annular bus protocol adopting a node mode. The protocol comprises a bus main controller, a bus node adapter, a variable bus node number and an annular structure bus, as well as an expandable bus command. The invention can be used for the control of all modules inside an integrated circuit chip, the realization of a data bus and the control and the data exchange of all circuit board-level chips.
Description
Technical field
The present invention relates to be fit in a kind of extensive ASIC design the interior communication of chip of rear end placement-and-routing and the chip chamber communications protocol that is adapted at the circuit board level wiring.By adopting the loop configuration of daisy chain pattern, and the communications protocol that adopts data stream format, make the line number signal that is used for communication reduce, the input/output port pipe leg fixed number of master controller, do not need between node and master controller to have point-to-point physical connection, solved the wiring bottleneck that main control organ pipe leg too much causes in the traditional die design and driven shortcoming such as load height.In extensive ASIC design, the bus of the loop configuration that adopts can not produce the problem that too much becomes system bottleneck owing to the pipe leg number of certain piece FPGA when doing chip checking with many FPGA prototype system, test is simple, meets the Design-For-Test theory.
Background technology
In the monster chip design, all exist data bus and register bus usually, along with integrated number of modules is more and more, the module that need carry out data access and register access also rises thereupon.The radial pattern bus structure of traditional one-to-many, write data and address bus are shared by a plurality of modules, but module of every increase just need increase corresponding address interface decoding and retaking of a year or grade data line on the master controller of bus, when number of modules rises to some, the pipe leg density of master controller is too high, and there is the line bottleneck in total system on master controller; And owing to need to drive a plurality of modules, its bus load is too high as the write data of sharing and address bus, need be with special processing, generation chip area and power wastage when realizing the high-frequency design.The project organization of such one-to-many, its shortcoming is completely exposed in carrying out the FPGA prototype verification, the too high problem of main control organ pipe leg is for the wiring and the sequential of the fpga chip internal logic at its place, and after dividing many FPGA, the pipe leg number that the fpga chip at master controller place needs is too high all to have a negative impact.
Adopt the ring bus mode of chrysanthemum chain, main control and each node pipe leg fixed number, the variation with number of modules does not exert an influence, and design repeats available.There is not bottleneck in system in sequential and interconnection resource (comprising chip internal and chip chamber), by adopting line number signal still less, significantly reduces the power consumption of chip simultaneously.
Summary of the invention
The objective of the invention is at the DCB line number signal in the chip design too much, what produce in the placement-and-routing of chip blocks up and the sequential control difficulty, and in the circuit board level design, the difficult problem that the PCB cabling is too much, a kind of high-speed annular bus protocol that adopts node mode that proposes, by adopting stream format communication and daisy chain structure connected in series, when effectively reducing the linking number of signal wire, there is the bottleneck problem of central point in the line that has solved one-to-many bus existence in the system.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is a node adaptor interface synoptic diagram of the present invention.
Fig. 2 is a ring bus connection diagram of the present invention.
Fig. 3 is a write order sequential synoptic diagram of the present invention.
Fig. 4 is a read command sequential synoptic diagram of the present invention.
Fig. 5 is a transferring command sequential synoptic diagram of the present invention.
Fig. 6 is a querying node command timing synoptic diagram of the present invention.
Fig. 7 has obtained the sequential synoptic diagram for node of the present invention.
Embodiment
The present invention needs to design two standard modules in realization, main controller module, with the node adaptor module, in realizing, system has a master controller and a plurality of node adapter, and master controller and a plurality of node adapter are by series connection looping bus on connecting.Fig. 2 is the formation signal of ring bus.Adopting with 8 bits in the following enforcement sample is the ring bus of bit wide, and the interface of conversion back and local intermodule is 32 bits.In the application of reality, ring bus and and local intermodule interface width can do variation, but do not break away from method for designing of the present invention.
Fig. 1 is node adapter (Net-Interface-Unit is called for short NIU) the interface synoptic diagram that the present invention adopts.Adapter adopts single channel clock (clk) to do driving, is done by single reset signal (rst) to reset.Each NIU has own unique node serial number (ID#).The interface signal of NIU comprises: by traffic spike line (i_in_data) and the expression effective Warning Marks of data (i_in_valid) that prime node or master controller transmit, the data stream (o_out_data) of level node or master controller transmission backward and effectively Warning Mark signal wire (o_out_valid) simultaneously.NIU numbers with different according to what order by matched node, data stream on the ring bus converted to and local module (Block) between unidirectional write data and read data bus, and will order and after clock period that the data stream time-delay is fixing backward level transmit.NIU itself does not need to know whom its prime and back level be, the node serial number of each NIU need be according to permanent order, and still numbering must be unique, otherwise be in displaced condition forever away from the duplicate node of master controller (according to the data stream positive dirction).
Be to implement in the sample NIU to the processing procedure of various command below:
Fig. 3 is the signal of of the present invention writing (WR) command process sequential.In the data stream that passes over by prime (i_in_data and i_in_valid), first clock period is that second clock period of node serial number (ID) is write order (WR), the 3rd clock period transmits is follow-up data length (LENGTH) indication (this time indication is 4 byte unit) of transmitting of needing, the 4th cycle and follow-up clock are used for Data transmission, up to the data length of finishing indication.If the destination node in the nodal value of current NIU and the data stream does not match, then the present node adapter is not done any operation to data stream, after time-delay clock period with data stream backward level transmit; If the coupling of the destination node in the nodal value of current NIU and the data stream, order in the data stream of level transmission at first backward replaces to transmission (PASS) order by writing (WR) order, simultaneously the write data stream (WDATA) of 8 bits is put in order according to 32 bit units, submitted to local module (Block) by the method that produces the data write signal pulse.And by producing the data reading signal pulse, reading of data from local module replaces to read data (RDATA) according to 8 bit-wise with the write data in the data stream (WDATA) then.This mode of carrying out read operation when writing can significantly be accelerated the exchange rate of data.It is pointed out that by simple variation and can add the order of only writing--when writing, do not carry out read operation.
Fig. 4 is the signal of of the present invention reading (RD) command process sequential.Carry out the read operation (RD) except by above-mentioned write order (WR) time, independently read command operation can also be arranged.The data stream that passes over by prime, first clock period is that second clock period of node serial number (ID) is read command (RD), what the 3rd clock period transmitted is the data length (LENGTH) that follow-up needs read, the 4th cycle and follow-up clock are used for Data transmission, up to the data length of finishing indication.If the destination node in the nodal value of current NIU and the data stream does not match, then current NIU node adapter is not done any operation to data stream, after time-delay clock period with data stream backward level transmit (data value of this moment itself is meaningless, can be arbitrary value); If the coupling of the destination node in the nodal value of current NIU and the data stream, order in the data stream of level transmission at first backward replaces to transmission (PASS) order by reading (RD) order, simultaneously by producing the data reading signal pulse, reading of data from local module (Block) is placed into read data backward in the data stream of level according to 8 bit-wise then.
Fig. 5 is the signal of transmission of the present invention (PASS) command process sequential.The data stream that passes over by prime, first clock period is that second clock period of node serial number (ID) is transferring command (PASS), what the 3rd clock period transmitted is the data length (LENGTH) that follow-up needs read, the 4th cycle and follow-up clock are used for Data transmission, up to the data length of finishing indication.In transferring command was handled, the destination node matching result in present node adapter and the data stream was meaningless, and data stream is not done any operation, and unique operation is with data stream level transmission backward after the clock period of delaying time.Transmit (PASS) order and place by the adapter NIU of first matching section point value in the loop usually, be used to tell back level NIU adapter data not to be carried out any processing, guarantee to arrive at master controller at last after data are through time-delay.Also can produce transferring command (PASS) by master controller,, can get back to master controller at last by after the time-delay of each adapter.If through the maximum interstitial content clock period of supporting on the ring bus time-delay after, master controller does not receive echo, then can judge the loop fracture, the method can be used for judging whether whole loop closed.
Fig. 6 is the signal of querying node of the present invention (IDPOLL) command process sequential.The data stream that is passed over by prime only comprises two cycles, and first clock period is node serial number (ID), and second clock period is querying node order (IDPOLL).In command process, if the node serial number in the nodal value of current adapter and the data stream (ID) coupling, after then querying node (IDPOLL) order of second period being replaced to node and having obtained order (IDGOT), level transmits backward.If present node does not match, then order is left intact, and directly submits enough backs level.
Fig. 7 is that node of the present invention obtains the signal of (IDGOT) command process sequential.The same with above-mentioned querying node (IDPOLL) order, the data stream that is passed over by prime only comprises two cycles, and first clock period is node serial number (ID), and second clock period is that node has obtained order (IDGOT).In command process, the destination node in present node adapter and the data stream is not done matching judgment, and data stream is not done any operation, after time-delay clock period with data stream backward level transmit.Node obtains (IDGOT) order and is placed by the adapter of first matching section point value in the loop usually, is used to tell back level adapter oneself to be queried to, and follow-up NIU does not carry out any processing to the result, guarantees that the result arrives at master controller at last.Node has obtained order (IDGOT) and can not produced by master controller usually, if but master controller need produce such order in some occasion, final this order is arrived at master controller after the clock period through the node corresponding number, this order is the same with above-mentioned transferring command (PASS), can judge also whether whole loop is closed.
Whether the major function of the main controller module of bus (Net-Interface-Controller is called for short NIC) is to produce Target id, order, data placement and reception, and overtime judgement is arranged among the NIC, rupture in order to judge the loop.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, difference according to practical application, can do the variation of stream format, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should be appreciated that and can make amendment or be equal to replacement technical scheme of the present invention, and do not break away from the spirit and scope of technical solution of the present invention.
Claims (5)
1. adopt the high-speed annular bus protocol of node mode, hardware comprises two general modules,
Bus master controller: in the full annular bus, have only a master controller, all communications are all started by it.Master controller is with the visit of chip main control module (as central processor CPU etc.) to node location, convert corresponding flow data communications protocol to, comprise automatic generation nodal value, order, data are sent to node, and submit to the chip main control module after the data preparation that will return by node.
The bus node adapter: in the full annular bus, according to actual needs, interstitial content can change.The node adapter adopts in whole bus with a kind of implementation method, by monitor and the matching bus communication data stream in the destination node value, with the bus content preservation of node to one's name or with the delivery of content of own node on bus.
In application, each node has a bus node adapter, each node adapter connects with the serial mode of chrysanthemum chain in the system, the input of first node adapter comes autonomous controller, master controller is sent in the output of last node adapter, the output of previous node adapter is the input of next node adapter, constitutes a loop configuration at last.Master controller and node adapter adopt same clock and reset signal, and synchronous mode is adopted in whole bus design.
2. the high-speed annular bus protocol of employing node mode as claimed in claim 1 is characterized in that, total system has only a master controller, and with the variation of interstitial content any modification is not arranged.
3. the high-speed annular bus protocol of employing node mode as claimed in claim 1 is characterized in that, the node module number could varyization of total system, and each node has independently static node address.
4. as claim 1,2, the high-speed annular bus protocol of 3 described employing node modes, it is characterized in that the loop configuration that adopts, make the input/output port of master controller not increase or reduce with the variation of interstitial content, the daisy chain serial mode of employing makes in high-speed chip design or board design, wiring reduces, and sequential control is simple; The increase of chip system or circuit board module or delete does not simply produce any influence of structure to total system.
5. as claim 1,2,3, the high-speed annular bus protocol of 4 described employing node modes, the communication command that it is characterized in that hardware layer can be expanded, and each node can be done the secondary command analysis to the data flow data behind the matching section point value as required simultaneously, to do the function expansion.
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| CN200910049686A CN101872331A (en) | 2009-04-21 | 2009-04-21 | High-speed annular bus protocol adopting node mode |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346726A (en) * | 2011-09-20 | 2012-02-08 | 四川卫士通信息安全平台技术有限公司 | High-speed annular interconnection method of plurality of chips on board |
| CN104268121A (en) * | 2014-09-23 | 2015-01-07 | 浪潮(北京)电子信息产业有限公司 | Super-large scale chip and layout method thereof as well as method and system for accessing register |
| CN107633145A (en) * | 2017-09-26 | 2018-01-26 | 郑州云海信息技术有限公司 | A kind of data acquisition ring circuit design implementation method and structure |
| CN112989757A (en) * | 2021-05-10 | 2021-06-18 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
-
2009
- 2009-04-21 CN CN200910049686A patent/CN101872331A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346726A (en) * | 2011-09-20 | 2012-02-08 | 四川卫士通信息安全平台技术有限公司 | High-speed annular interconnection method of plurality of chips on board |
| CN104268121A (en) * | 2014-09-23 | 2015-01-07 | 浪潮(北京)电子信息产业有限公司 | Super-large scale chip and layout method thereof as well as method and system for accessing register |
| CN104268121B (en) * | 2014-09-23 | 2017-08-11 | 浪潮(北京)电子信息产业有限公司 | The method and system of register are accessed in ultra-large chip |
| CN107633145A (en) * | 2017-09-26 | 2018-01-26 | 郑州云海信息技术有限公司 | A kind of data acquisition ring circuit design implementation method and structure |
| CN112989757A (en) * | 2021-05-10 | 2021-06-18 | 芯华章科技股份有限公司 | Method and storage medium for numbering a plurality of prototype verification boards |
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Application publication date: 20101027 |