CN116155372A - Multi-FPGA prototype verification system based on optical switching - Google Patents
Multi-FPGA prototype verification system based on optical switching Download PDFInfo
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- CN116155372A CN116155372A CN202310403280.XA CN202310403280A CN116155372A CN 116155372 A CN116155372 A CN 116155372A CN 202310403280 A CN202310403280 A CN 202310403280A CN 116155372 A CN116155372 A CN 116155372A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/073—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an out-of-service signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/27—Arrangements for networking
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a multi-FPGA prototype verification system based on optical exchange, which comprises an optical switch, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board through cables or wiring in the circuit board card through LVDS interfaces, the FPGAs between different circuit board cards are connected with the plurality of high-speed serial transceivers through the optical switch, and the FPGAs in the same circuit board card are non-directly connected in a board through the optical switch and the high-speed serial transceivers. The method has stronger flexibility, and can complete reconfiguration of circuit communication without manually plugging and unplugging optical fibers; compared with the traditional message switching equipment, the optical switching delay is lower, can process signals which need to arrive in a single period in the simulation process, improves the simulation performance, and can save the pin resources of the FPGA.
Description
Technical Field
The invention belongs to the technical field of FPGA hardware systems, and particularly relates to a multi-FPGA prototype verification system based on optical switching.
Background
FPGA prototype verification is an important link in the overall process of IC design verification. When prototype verification is performed on a large-scale chip, the resource of one FPGA does not meet the requirement of the whole design, and a plurality of FPGAs are required to be cascaded. With the annual improvement of chip manufacturing process, the functions and performances of chips are higher and higher, the scale is larger and the requirements on a multi-FPGA prototype verification system are urgent.
In order to ensure that the time delay of a communication link between FPGAs is as low as possible, a mainstream commercial multi-FPGA prototype verification system basically adopts a direct connection mode for communication, such as coaxial cable or optical fiber. Although the link mode can ensure large bandwidth and low time delay of the communication link between the ports, the flexibility is poor, if the connection relation of the FPGA needs to be adjusted, the interface needs to be plugged and unplugged again, and the phenomenon of unstable interface signals is easily caused, so that the user experience is influenced.
An Optical switch (Optical switch) is a device capable of performing data exchange of Optical signals, and directly performing data exchange of Optical signals without electro-Optical-to-photoelectric conversion. Therefore, there is a need for a multi-FPGA prototype verification system based on optical switching.
Disclosure of Invention
Aiming at the technical problems, the invention provides a multi-FPGA prototype verification system based on optical switching.
The technical scheme adopted for solving the technical problems is as follows:
a multi-FPGA prototype verification system based on optical exchange comprises an optical switch, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board through cables or wiring in the circuit board card through LVDS interfaces, the FPGAs between different circuit board cards are connected with the plurality of high-speed serial transceivers through the optical switch, and the FPGAs in the same circuit board card are not directly connected in a board through the optical switch and the high-speed serial transceivers.
Preferably, the FPGAs between different circuit board cards are connected through an optical switch and a plurality of high-speed serial transceivers, comprising:
the FPGA of one circuit board card is connected to the optical switch through different paths of high-speed serial transceivers respectively, and then is connected to the FPGA of the other circuit board card through different paths of high-speed serial transceivers.
Preferably, a plurality of FPGAs in the same circuit board card are not directly connected in the board through an optical switch and a high-speed serial transceiver, including:
any FPGA of the same circuit board card is connected to the optical switch through the corresponding high-speed serial transceiver, and then is connected to other FPGAs of the same circuit board card through other high-speed serial transceivers of different paths.
Preferably, the high-speed serial transceiver includes at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port, and a GTM port.
Preferably, the FPGAs between different circuit board cards can also be directly connected by cables through reserved ports based on LVDS.
Preferably, the optical switch adopts a line switch of an all-optical switch, and the implementation method of the optical switch comprises single-channel interconnection and multi-channel binding interconnection.
Preferably, the peripheral interface may be accessed into the hardware architecture through the optical switch, where the peripheral interface includes at least one of an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, a GPIO interface, an HDMI interface, an SRIO interface, an Ethernet interface, a PCIE interface, and a DDR interface.
Preferably, parameter setting is performed on a management interface of the optical switch, connection relation among ports is controlled, and reconfiguration of circuit communication is completed.
The multi-FPGA prototype verification system based on optical switching has the following advantages compared with the prior art,
(1) The high-speed interconnection between the FPGAs is realized by adopting an optical switching mode, so that the high-speed interconnection has stronger flexibility than a mode of direct connection through optical fibers, and the reconfiguration of circuit communication can be completed without manually plugging the optical fibers;
(2) The optical switching delay is lower than that of the traditional message switching equipment, and can process signals which need to arrive in a single period in the simulation process;
(3) Compared with the LVDS port based on the TDM mode, the signal transmission bandwidth of the optical switching mode is increased by hundreds of thousands of times, and the simulation performance is improved;
(4) Meanwhile, due to limited bandwidth, when the TDM-based LVDS ports transmit the same number of signals, more FPGA pins are needed, and the adoption of the method and the device can save the pin resources of the FPGA.
Drawings
FIG. 1 is a schematic diagram of an exemplary architecture of a multi-FPGA prototype verification system based on optical switching according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an exemplary architecture of a multi-FPGA prototype verification system based on optical switching according to another embodiment of the present invention;
FIG. 3 is an expanded schematic diagram of a multi-FPGA prototype verification system based on optical switching according to an embodiment of the present invention;
fig. 4 is an expanded schematic diagram of a multi-FPGA prototype verification system based on optical switching according to another embodiment of the present invention.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings.
In one embodiment, as shown in fig. 1 and fig. 2, an optical-exchange-based multi-FPGA prototype verification system includes an optical switch, a plurality of circuit board cards and a multi-channel high-speed serial transceiver, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board through cables or wiring in the circuit board card through LVDS interfaces, the FPGAs between different circuit board cards are connected with the multi-channel high-speed serial transceiver through the optical switch, and the FPGAs in the same circuit board card are indirectly connected in a board through the optical switch and the high-speed serial transceiver.
Specifically, the whole system is composed of a plurality of FPGAs (Field Programmable Gate Array, field programmable gate arrays), the FPGAs are firstly grouped according to resource conditions, as shown in fig. 1, 4 FPGAs can be used as a group, and the FPGAs in the group are directly connected by adopting cables or wiring in a circuit board card. The full system FPGA can be connected with the optical switch through the high-speed serial transceiver for full system interconnection. Wherein the number of channels interconnected between FPGAs can be adjusted as desired. The number of channels between the FPGA and the optical switch can also be adjusted as desired.
In one embodiment, the FPGA between different circuit board cards is connected to the multi-way high-speed serial transceiver through an optical switch, comprising:
the FPGA of one circuit board card is connected to the optical switch through different paths of high-speed serial transceivers respectively, and then is connected to the FPGA of the other circuit board card through different paths of high-speed serial transceivers.
In one embodiment, the multiple FPGAs in the same circuit board card are not directly connected in-board through the optical switch and the high-speed serial transceiver, including:
any FPGA of the same circuit board card is connected to the optical switch through the corresponding high-speed serial transceiver, and then is connected to other FPGAs of the same circuit board card through other high-speed serial transceivers of different paths.
In one embodiment, the high speed serial transceiver includes at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port, and a GTM port.
Specifically, GTH, GTX, GTY, GTP, GTZ, GTM port: GT, gigabyte Transceiver, G-bit transceivers, commonly referred to as Serdes, high speed transceivers, GT, etc. GTH, GTX, GTY, GTP, GTZ, GTM is different high-speed serial transceivers developed according to different processes and requirements in each series of FPGA of Xilinx, and the supported highest linear speed is ordered as GTP < GTX < GTH < GTZ < GTY < GTM.
In one embodiment, the FPGAs between different circuit board cards may also be directly connected by cables through reserved LVDS-based ports.
In particular, LVDS (Low-Voltage Differential Signaling, low voltage differential signaling) is a differential signaling technology with Low power consumption, low bit error rate, low crosstalk, and Low radiation.
In one embodiment, the optical switch adopts a line switch of an all-optical switch, and the implementation method of the optical switch comprises single-channel interconnection and multi-channel binding interconnection.
In particular, the optical switch in the invention adopts the line switch of the all-optical switch instead of the packet switch, and is characterized in that the point-to-point direct connection is realized after the interconnection relation of all endpoints is determined, and the specific implementation mode comprises single-channel interconnection and multi-channel binding interconnection.
The system can be expanded through an optical switch to realize a larger-scale FPGA prototype verification system. As shown in fig. 2 and 3 below, wherein the number of channels between switches can be configured as desired.
In one embodiment, the peripheral interface may be accessed to the hardware system through the optical switch, where the peripheral interface includes at least one of an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, a GPIO interface, an HDMI interface, an SRIO interface, an Ethernet interface, a PCIE interface, and a DDR interface.
Specifically, based on the optical switch, abundant peripheral interfaces can be accessed into a hardware system, a peripheral resource pool is realized, the dispatching management of the hard cloud-like platform is facilitated, and the hardware system comprises low-speed peripherals such as an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, a GPIO interface and the like, and high-speed peripherals such as HDMI, SRIO, ethernet, PCIE, DDR and the like. A typical manner is shown in fig. 4 below.
Further, the I2C, also referred to as IIC, I2C bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips corporation. It requires only two wires to transfer information between devices connected to the bus. UART (Universal Asynchronous Receiver/Transmitter ) is a universal serial data bus for asynchronous communications that communicates bi-directionally, enabling full duplex transmission and reception. SPI (Serial Peripheral Interface ), is a high-speed, full duplex, synchronous communications bus. QSPI: the queue SPI is an extension of an SPI interface which is proposed by a Motorola company, the Motorola company enhances the functions of the SPI interface on the basis of an SPI protocol, a queue transmission mechanism is increased, and a queue serial peripheral interface protocol (namely QSPI protocol) is proposed, and is generally used for connecting single, double or four (data lines) SPI Flash storage media. JTAG (Joint Test Action Group ), is an International Standard test protocol (IEEE 1149.1 compliant) and is used primarily for on-chip testing. Most advanced devices now support the JTAG protocol, such as DSP, FPGA devices, etc. The standard JTAG interface is 4 lines: TMS, TCK, TDI, TDO, respectively, mode select, clock, data input and data output lines. GPIO (General purpose input/output), P0-P3 with a function similar to 8051, can be used by a user freely by program control, and the PIN can be used as General Purpose Input (GPI) or General Purpose Output (GPO) or General Purpose Input and Output (GPIO) according to practical considerations, such as clk generator, chip select, etc.
HDMI (High Definition Multimedia Interface ) is a fully digital video and audio transmission interface that can transmit uncompressed audio and video signals. RapidIO: rapidIO interconnect architecture, compatible with the most popular integrated communication processors, host processors, and network digital signal processors at present, is a high-performance, packet-switched interconnect technology. SRIO (Serial RapidIO), which is a RapidIO standard in which a physical layer adopts Serial differential analog signal transmission, can meet the requirements of high-performance embedded industry for reliability, increased bandwidth, and faster bus speed in the internal interconnection of a system. Ethernet: ethernet is a computer local area network technology, and the IEEE 802.3 standard of the IEEE organization sets up the technical standard of ethernet, which specifies the contents including the connection of the physical layer, the electronic signal and the medium access control. PCIE: peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard originally named "3GIO", was proposed by Intel in 2001, and was intended to replace the old PCI, PCI-X and AGP bus standards. DDR: double Data Rate SDRAM the Chinese name "double data stream SDRAM" is a memory name, meaning that double rate synchronous dynamic random access memory is one of the memories.
In one embodiment, parameter setting is performed at a management interface of the optical switch, connection relation between ports is controlled, and reconfiguration of circuit communication is completed.
The multi-FPGA prototype verification system based on optical switching has the following advantages compared with the prior art,
(1) The high-speed interconnection between the FPGAs is realized by adopting an optical switching mode, so that the high-speed interconnection has stronger flexibility than a mode of direct connection through optical fibers, and the reconfiguration of circuit communication can be completed without manually plugging the optical fibers;
(2) The optical switching delay is lower than that of the traditional message switching equipment, and can process signals which need to arrive in a single period in the simulation process;
(3) Compared with the LVDS port based on the TDM mode, the signal transmission bandwidth of the optical switching mode is increased by hundreds of thousands of times, and the simulation performance is improved;
(4) Meanwhile, due to limited bandwidth, when the TDM-based LVDS ports transmit the same number of signals, more FPGA pins are needed, and the adoption of the method and the device can save the pin resources of the FPGA.
The multi-FPGA prototype verification system based on optical switching provided by the invention is described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the core concepts of the invention. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (8)
1. A multi-FPGA prototype verification system based on optical exchange is characterized by comprising an optical switch, a plurality of circuit board cards and a plurality of high-speed serial transceivers, wherein a plurality of FPGAs are placed in each circuit board card, the FPGAs in the same circuit board card are directly connected in a board through cables or wires in the circuit board card through LVDS interfaces, the FPGAs between different circuit board cards are connected with the plurality of high-speed serial transceivers through the optical switch, and the FPGAs in the same circuit board card are non-directly connected in a board through the optical switch and the high-speed serial transceivers.
2. The system of claim 1, wherein the FPGA between the different circuit board cards is connected to the multi-way high-speed serial transceiver through the optical switch, comprising:
the FPGA of one circuit board card is connected to the optical switch through different paths of high-speed serial transceivers respectively, and then is connected to the FPGA of the other circuit board card through different paths of high-speed serial transceivers.
3. The system of claim 2, wherein the plurality of FPGAs in the same circuit board card are not directly connected in-board through the optical switch and the high-speed serial transceiver, comprising:
any FPGA of the same circuit board card is connected to the optical switch through the corresponding high-speed serial transceiver, and then is connected to other FPGAs of the same circuit board card through other high-speed serial transceivers of different paths.
4. The system of claim 3, wherein the high-speed serial transceiver comprises at least one of a GTH port, a GTX port, a GTY port, a GTP port, a GTZ port, and a GTM port.
5. The system of claim 4, wherein FPGAs between different circuit board cards are further directly connectable by cables through reserved LVDS-based ports.
6. The system of claim 5, wherein the optical switch is a line switch of an all-optical switch, and wherein the optical switching is implemented by a single channel interconnect and a multi-channel bonded interconnect.
7. The system of claim 6, wherein a peripheral interface is accessible into the hardware architecture through the optical switch, wherein the peripheral interface comprises at least one of an I2C interface, a UART interface, an SPI interface, a QSPI interface, a JTAG interface, a GPIO interface, an HDMI interface, an SRIO interface, an Ethernet interface, a PCIE interface, and a DDR interface.
8. The system of claim 7, wherein parameter setting is performed at a management interface of the optical switch to control connection relationships between ports to complete reconfiguration of circuit communications.
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