CN204597988U - The AFDX terminal test equipment of Based PC PCI interface - Google Patents
The AFDX terminal test equipment of Based PC PCI interface Download PDFInfo
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- CN204597988U CN204597988U CN201420865717.8U CN201420865717U CN204597988U CN 204597988 U CN204597988 U CN 204597988U CN 201420865717 U CN201420865717 U CN 201420865717U CN 204597988 U CN204597988 U CN 204597988U
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Abstract
The utility model discloses a kind of AFDX terminal test equipment of Based PC PCI interface, comprising: PCI communication module, for realizing the exchanges data between host computer and programmable chip; Programmable chip, data for being passed down by host computer carry out AFDX protocol code to be given to tested AFDX aviation ethernet standard equipment, and the data that tested AFDX aviation ethernet standard equipment is uploaded are carried out verify, traffic shaping and Redundancy Management to be to be given to host computer; AFDX terminal test equipment interface module, for realizing the exchanges data between programmable chip and tested AFDX aviation ethernet standard equipment; Power module, powers for giving whole testing equipment.The utility model achieves sampling, the function such as queue and error injection/detection of AFDX aviation ethernet standard equipment.
Description
Technical field
The utility model relates to testing equipment technical field, is specifically related to a kind of AFDX terminal test equipment of Based PC PCI interface.
Background technology
AFDX full name is avionic full-duplex switched-type Ethernet (Avionics Full DuplexSwitched Ethernet, AFDX), it is for carrying out exchanges data and a kind of agreement (IEEE802.3 and the ARINC664Part7) standard defined between aviation subsystem, be based on ARINC429 and 1553B basis on a kind of bus communication protocol specification (ARINC664).AFDX is one of current avionics network data transmission technology more advanced in the world, it is based on the ICP/IP protocol of the high bandwidth ethernet technology of maturation and extensive use, therefore its research and development, deployment can be more prone to compared with traditional avionics system with enforcement, and cost is lower.But compared with conventional Ethernet, it has again, and real-time is good, reliability high.At present, AFDX aviation Ethernet shows very strong adaptability in the avionics network application such as big-and-middle-sized transporter and passenger plane, under cover has huge applications potentiality.Therefore, such avionic device (AFDX aviation ethernet standard equipment) test and safeguard and just seem and become more and more important.In addition, because pci bus transmission speed is fast, and support the function such as hot plug, power management, not only can meet the high speed data transfer of multi-channel A FDX aviation Ethernet, and volume is little, price is low, easy to use, applied range, and pci bus is the avionics industrial computer bus being in main flow, therefore, PCI technology and TCP/IP technology are applied in AFDX aviation Ethernet, design a kind of AFDX aviation ethernet terminal testing equipment of Based PC PCI interface, many more conveniences will be brought.
Utility model content
The utility model object is the AFDX terminal test equipment providing a kind of Based PC PCI interface.
Above-mentioned purpose is achieved through the following technical solutions:
An AFDX terminal test equipment for Based PC PCI interface, is characterized in that, comprising: PCI communication module, for realizing the exchanges data between host computer and following programmable chip; Programmable chip, realize the distinctive repertoire of AFDX protocol stack, data for being passed down by described host computer carry out AFDX protocol code to be given to tested AFDX aviation ethernet standard equipment, and the data that described tested AFDX aviation ethernet standard equipment is uploaded are carried out verify, traffic shaping and Redundancy Management to be to be given to described host computer; AFDX terminal test equipment interface module, for realizing the exchanges data between described programmable chip and described tested AFDX aviation ethernet standard equipment; Power module, powers for giving whole testing equipment.
As concrete technical scheme, described PCI communication module comprises interconnective pci interface and PCI bridging chip, and described PCI bridging chip is connected with programmable chip, and described pci interface is connected with described host computer.
As concrete technical scheme, described PCI communication module adopts PCI9056 interface chip.
As concrete technical scheme, comprise in described programmable chip: processor unit, for controlling the inner each module of described programmable chip and each component working of chip exterior; Data that are encoded or also injection mistake are sent to described AFDX terminal test equipment interface module for setting logic by sendaisle; Receive path, for setting logic to receive the data of described AFDX terminal test equipment interface module with to be decoded and verification; Pci interface module, for realizing the exchanges data between described programmable chip and PCI communication module.
As concrete technical scheme, described sendaisle comprises and connecting successively: traffic shaping module, the message flow sent for controlling the inner AFDX port of described programmable chip standardizes, the data flow making it export be regular, there is no a delay variation and meet the message flow of the BAG parameter of following virtual link scheduler module; Virtual link scheduler module, for dispatching from the message in different virtual circuits, determines the order sending message, to meet the requirement of real-time; Sending Redundancy Management System, for when sending message, sent message copy being sent to 2 independently in redundant network; Described receive path comprises and connecting successively: integrity checking module, for the data received by the MAC layer receiving terminal of AFDX are carried out integrity checking, namely checks the SN sequence number whether received frame has virtual link and expect; Receive Redundancy Management System, when receipt message, the message after integrity checking is carried out identical inspection, with filtering redundancy message.
As concrete technical scheme, described programmable chip model is EP3C55F484I type FPGA.
As concrete technical scheme, described AFDX terminal test equipment interface module is the two Redundant Ethernet PHY physical layer interfaces be connected with described programmable chip.
As concrete technical scheme, the described pair of Redundant Ethernet PHY physical layer interface comprises 2 separate ethernet PHY physical layer interfaces.
As concrete technical scheme, described AFDX terminal test equipment interface module adopts 88E1111 interface chip.
The beneficial effect of the AFDX terminal test equipment of the Based PC PCI interface that the utility model provides is: because pci interface supports hot plug, by making full use of, conventional Ethernet data transmission bandwidth is high and pci bus transmission speed is fast and the feature of support hot plug, make the utility model can meet the high speed data transfer of two redundancy AFDX aviation Ethernet, achieve the sampling (sampling) of AFDX aviation ethernet standard equipment, the functions such as queue (queuing) and error injection/detection, the function such as error checking and protocal analysis can be carried out between simulation and AFDX aviation ethernet standard equipment, meanwhile, the utility model volume is relatively little, is convenient for carrying and uses.
Accompanying drawing explanation
The structured flowchart of the AFDX terminal test equipment of the Based PC PCI interface that Fig. 1 provides for the utility model embodiment.
The internal structure block diagram of the AFDX terminal test equipment of the Based PC PCI interface that Fig. 2 provides for the utility model embodiment.
Embodiment
As shown in Figure 1, the AFDX terminal test equipment of the Based PC PCI interface that the present embodiment provides is test board, comprises PCI communication module, programmable chip, AFDX terminal test equipment interface module and power module.Wherein programmable chip is connected with PCI communication module and AFDX terminal test equipment interface module, and power module powers to whole testing equipment.
As shown in Figure 2, PCI communication module is connected between host computer and programmable chip, for realizing the exchanges data between host computer and programmable chip.PCI communication module comprises interconnective pci interface and PCI bridging chip, and pci interface is connected with host computer (not shown), the pci interface model calling of PCI bridging chip and programmable chip.
Continue referring to Fig. 2, programmable chip comprises processor unit, sendaisle, receive path and pci interface module.Processor unit and sendaisle, receive path and pci interface model calling, for controlling the inner each module of programmable chip and each component working of chip exterior.
Data that are encoded or also injection mistake are sent to described AFDX terminal test equipment interface module for setting logic by sendaisle.Sendaisle comprises the transmission cache module, traffic shaping module, virtual link scheduler module, transmission Redundancy Management System and the MAC1 that connect successively.Wherein, traffic shaping module, the message flow sent for controlling the inner AFDX port of programmable chip standardizes, the data flow making it export be regular, there is no a delay variation and meet the message flow of the BAG parameter of following virtual link scheduler module; Virtual link scheduler module, for dispatching from the message in different virtual circuits, determines the order sending message, to meet the requirement of real-time; Sending Redundancy Management System, for when sending message, sent message copy being sent to 2 independently in redundant network.
Receive path, for setting logic to receive the data of described AFDX terminal test equipment interface module with to be decoded and verification.Receive path comprises the MAC2, reception cache module, integrity checking module and the reception Redundancy Management System that connect successively.Wherein, integrity checking module, for the data received by the MAC layer receiving terminal of AFDX are carried out integrity checking, namely whether inspection received frame has the SN sequence number that virtual link is expected; Receive Redundancy Management System, when receipt message, the message after integrity checking is carried out identical inspection, with filtering redundancy message.
Pci interface module, for realizing the exchanges data between programmable chip and PCI communication module.
Continue to be connected between programmable chip and tested AFDX aviation ethernet standard equipment referring to Fig. 2, AFDX terminal test equipment interface module, for realizing the exchanges data between programmable chip and tested AFDX aviation ethernet standard equipment.AFDX terminal test equipment interface module is two Redundant Ethernet PHY physical layer interfaces, comprise 2 separate ethernet PHY physical layer interfaces, 2 separate ethernet PHY physical layer interfaces are connected with the sendaisle of programmable chip and receive path respectively, and the other end is respectively by RJ45 interface and tested AFDX aviation ethernet standard equipment connection (not shown).
Power module, it is input as+12V/-12V/+5V/+3.3V direct current, exports and has+2.5V ,-5V and 1.2V.
In the present embodiment, the concrete model of PCI bridging chip is PCI9056, multiple local bus can be made to be quickly transferred in pci bus by this chip.Programmable chip is fpga chip, and model is EP3C55F484I, can realize all functions of AFDX protocol stack and MAC link layer.Two redundant physical layer PHY chip of AFDX adopt 88E1111, can realize data link and the transmission of 10M/100M ethernet physical layer.
During the work of the AFDX terminal test equipment of the Based PC PCI interface that the utility model embodiment provides, its pci interface is connected with PC, the RJ45 cable interface of its pair of Redundant Ethernet PHY physical layer interface and tested AFDX aviation ethernet standard equipment connection, realize the exchanges data between tested AFDX aviation ethernet standard equipment and the PC running inspection software, its workflow specifically comprises transmission data workflow and receives data workflow.
Send data workflow:
First on PC, upper strata testing software is run, the relevant parameter of sendaisle is set by it, this information is sent to programmable chip by pci interface, processor unit in programmable chip arranges the related register parameter of sendaisle according to the parameter that PC passes down, this message is through traffic shaping module simultaneously, carry out planningization process, the Frame making it export be regular, there is no delay variation.After adding sequence number (SN) from the Frame of traffic shaping module by virtual scheduling module, mail to transmission Redundancy Management System.Needs are sent message copy and are sent to 2 independently in redundancy MAC link layer by Redundancy Management System.MAC module adds frame sequence verification to Frame, mails to AFDX terminal test equipment interface module.Be sent in tested AFDX aviation ethernet standard equipment after the Frame of the MAC layer in programmable chip is carried out level conversion by the ethernet PHY physical layer interface of AFDX terminal test equipment interface module.
Receive data workflow:
First on PC, upper strata testing software is run, the relevant parameter of receive path is set by it, this information is sent to programmable chip by pci interface, and processor unit arranges the relevant parameter of receive path according to the parameter that host computer passes down, completes the initialization operation of receive path.Then, after AFDX terminal test equipment interface module detects and physical link has Frame, taken out by Frame, deliver to MAC module in programmable chip, MAC module carries out CRC check to Frame.Deliver to receiver module afterwards.The data that MAC module transmits by receiver module are stored in own cache, until after data frame receipt, end-to-end and Redundancy Management are carried out to Frame, during integrity checking, whether inspection received frame has the SN sequence number that virtual link is expected, Redundancy Management is used for the message after integrity checking being carried out identical inspection, with filtering redundancy message.Processor unit in programmable chip controls the correct message received to be uploaded to host computer by pci interface, and host computer testing software will carry out data verification and analysis to these message.
The utility model is not limited to above-described embodiment, based on above-described embodiment, the simple replacement of not making creative work, the scope that the utility model discloses should be belonged to.
Claims (9)
1. an AFDX terminal test equipment for Based PC PCI interface, is characterized in that, comprising:
PCI communication module, for realizing the exchanges data between host computer and following programmable chip;
Programmable chip, realize the distinctive repertoire of AFDX protocol stack, data for being passed down by described host computer carry out AFDX protocol code to be given to tested AFDX aviation ethernet standard equipment, and the data that described tested AFDX aviation ethernet standard equipment is uploaded are carried out verify, traffic shaping and Redundancy Management to be to be given to described host computer;
AFDX terminal test equipment interface module, for realizing the exchanges data between described programmable chip and described tested AFDX aviation ethernet standard equipment;
Power module, powers for giving whole testing equipment.
2. the AFDX terminal test equipment of Based PC PCI interface as claimed in claim 1, it is characterized in that: described PCI communication module comprises interconnective pci interface and PCI bridging chip, described PCI bridging chip is connected with programmable chip, and described pci interface is connected with described host computer.
3. the AFDX terminal test equipment of Based PC PCI interface as claimed in claim 1 or 2, is characterized in that: described PCI communication module adopts PCI9056 interface chip.
4. the AFDX terminal test equipment of Based PC PCI interface as claimed in claim 1, is characterized in that: comprise in described programmable chip:
Processor unit, for controlling the inner each module of described programmable chip and each component working of chip exterior;
Data that are encoded or also injection mistake are sent to described AFDX terminal test equipment interface module for setting logic by sendaisle;
Receive path, for setting logic to receive the data of described AFDX terminal test equipment interface module with to be decoded and verification;
Pci interface module, for realizing the exchanges data between described programmable chip and PCI communication module.
5. the AFDX terminal test equipment of Based PC PCI interface as claimed in claim 4, is characterized in that, described sendaisle comprises and connecting successively:
Traffic shaping module, the message flow sent for controlling the inner AFDX port of described programmable chip standardizes, the data flow making it export be regular, there is no a delay variation and meet the message flow of the BAG parameter of following virtual link scheduler module;
Virtual link scheduler module, for dispatching from the message in different virtual circuits, determines the order sending message, to meet the requirement of real-time;
Sending Redundancy Management System, for when sending message, sent message copy being sent to 2 independently in redundant network;
Described receive path comprises and connecting successively:
Integrity checking module, for the data received by the MAC layer receiving terminal of AFDX are carried out integrity checking, namely whether inspection received frame has the SN sequence number that virtual link is expected;
Receive Redundancy Management System, when receipt message, the message after integrity checking is carried out identical inspection, with filtering redundancy message.
6. the AFDX terminal test equipment of the Based PC PCI interface as described in claim 1 or 4 or 5, is characterized in that: described programmable chip model is EP3C55F484I type FPGA.
7. the AFDX terminal test equipment of Based PC PCI interface as claimed in claim 1, is characterized in that: described AFDX terminal test equipment interface module is the two Redundant Ethernet PHY physical layer interfaces be connected with described programmable chip.
8. the AFDX terminal test equipment of Based PC PCI interface as claimed in claim 7, is characterized in that: the described pair of Redundant Ethernet PHY physical layer interface comprises 2 separate ethernet PHY physical layer interfaces.
9. the AFDX terminal test equipment of the Based PC PCI interface as described in claim 1 or 7 or 8, is characterized in that: described AFDX terminal test equipment interface module adopts 88E1111 interface chip.
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| CN201420865717.8U CN204597988U (en) | 2014-12-30 | 2014-12-30 | The AFDX terminal test equipment of Based PC PCI interface |
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| CN201420865717.8U CN204597988U (en) | 2014-12-30 | 2014-12-30 | The AFDX terminal test equipment of Based PC PCI interface |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809863A (en) * | 2017-05-05 | 2018-11-13 | 中国航空无线电电子研究所 | A kind of on-board data storage resource Distributed sharing network system based on AFDX |
| CN117459276A (en) * | 2023-10-26 | 2024-01-26 | 齐鲁中科新动能创新研究院 | Debugging device applied to master-slave communication system |
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2014
- 2014-12-30 CN CN201420865717.8U patent/CN204597988U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809863A (en) * | 2017-05-05 | 2018-11-13 | 中国航空无线电电子研究所 | A kind of on-board data storage resource Distributed sharing network system based on AFDX |
| CN117459276A (en) * | 2023-10-26 | 2024-01-26 | 齐鲁中科新动能创新研究院 | Debugging device applied to master-slave communication system |
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