CN203399134U

CN203399134U - FC network dual-port simulation card

Info

Publication number: CN203399134U
Application number: CN201320510981.5U
Authority: CN
Inventors: 胡钢; 邱昆
Original assignee: CHENGDU CHENGDIAN GUANGXIN TECHNOLOGY Co Ltd
Current assignee: Chengdu Uestc Optical Communication Co ltd
Priority date: 2013-08-21
Filing date: 2013-08-21
Publication date: 2014-01-15
Anticipated expiration: 2023-08-21

Abstract

The utility model discloses an FC network dual-port simulation card, comprising a central processor, an interface test adapter, a first reference clock chip, a second reference clock chip and a field programmable gate array (FPGA); the interface test adapter, the first reference clock chip, the second reference clock chip and the FPGA are all in connection with the central processor; the interface test adapter is in connection with a plurality of test terminals. According to the above principle, the FC network dual-port simulation card can identify and determine test terminal port information through the interface adapter and sends the processed information to the central processor to raise transmission efficiency.

Description

FC network dual-port artificial card

Technical field

The utility model relates to network port field, is specifically related to FC network dual-port artificial card.

Background technology

FC network dual-port artificial card, for according to the definition of FC agreement, is realized data communication.Specifically comprise the data encapsulation from user software is become to FC frame, according to sending protocol requirement, send in FC network; The FC frame that receives the port from FC network, parses user data, is submitted to user software.In dual-port communication, two of system requirements are dual-port independently, can independently carry out data communication, can distinguish a network equipment.Due to the data of two ports of a PCIE interface transmission of FC artificial card employing, need to carry out the data separation of two ports.During single port communication, bi-directional data bandwidth transmission rate 160MB/s, receives 180M/s; Each port bi-directional data bandwidth transmission rate 120MB/s during dual-port communication, receiving velocity 160MB/s.In the face of above bandwidth requirement, the efficiency of transmission that how to improve PCIE is the key that guarantees bandwidth.In prior art, also cannot realize identification data from port, also just cannot illustrate that data are to mail to which port, can only to two ports, transmit simultaneously, reduce transmission rate.

Utility model content

The utility model has overcome the deficiencies in the prior art, and FC network dual-port artificial card is provided, and can to test port information, identify judgement by interface adapter, and process information is sent to central processing unit, improves efficiency of transmission.

For solving above-mentioned technical problem, the utility model is by the following technical solutions: FC network dual-port artificial card, comprise central processing unit, interface test adapter, the first reference clock chip, the second reference clock chip and on-site programmable gate array FPGA, described interface test adapter, the first reference clock chip, the second reference clock chip are all connected with central processing unit with on-site programmable gate array FPGA; On described interface test adapter, connect a plurality of test ports.

On described on-site programmable gate array FPGA, connect optical transceiver module.

The model of described optical transceiver module is FTRJ-8519-1-2.5.

Connection data buffer storage FLASH, static random access memory SRAM and PCI-EXPRESS X4 interface on described on-site programmable gate array FPGA.

The model of the first described reference clock chip is MAX DS4106.

The model of the second described reference clock chip is MAX DS4212.

Compared with prior art, the beneficial effects of the utility model are:

1, interface test adapter of the present utility model can be that AD converter and codec chip form, by interface test adapter, central processing unit is processed and sent to the data that receive from test interface, realization, to the identification of test interface information and effectively transmission, improves efficiency of transmission.

2, the optical transceiver module in the utility model is the interface device that a kind of signal of telecommunication is converted to light signal, realizes any conversion to photosignal.

Accompanying drawing explanation

Fig. 1 is schematic diagram of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model is further elaborated, embodiment of the present utility model is not limited to this.

Embodiment:

As shown in Figure 1, the utility model comprises central processing unit, interface test adapter, the first reference clock chip, the second reference clock chip and on-site programmable gate array FPGA, on on-site programmable gate array FPGA, connect optical transceiver module, the model of optical transceiver module is FTRJ-8519-1-2.5.Connection data buffer storage FLASH, static random access memory SRAM and PCI-EXPRESS X4 interface on on-site programmable gate array FPGA.The interface test adapter of the present embodiment, the first reference clock chip, the second reference clock chip are all connected with central processing unit with on-site programmable gate array FPGA; On described interface test adapter, connect a plurality of test ports.The model of the first reference clock chip is MAX DS4106, and the model of the second reference clock chip is MAX DS4212, and the model of FPGA is XC5VLX110T, and the model of central processing unit is ARMCORTEX M3.

FC network dual-port artificial card has two data transmission interfaces, by interface test adapter, central processing unit is processed and sent to the data that receive from test interface, and interface test adapter can be that AD converter and codec chip form.Interface test adapter wherein can be identified the information of test port, carries out effective transmission of data, has improved efficiency of transmission.

Just can realize this utility model as mentioned above.

Claims

1.FC network dual-port artificial card, it is characterized in that: comprise central processing unit, interface test adapter, the first reference clock chip, the second reference clock chip and on-site programmable gate array FPGA, described interface test adapter, the first reference clock chip, the second reference clock chip are all connected with central processing unit with on-site programmable gate array FPGA; On described interface test adapter, connect a plurality of test ports.

2. FC network dual-port artificial card according to claim 1, is characterized in that: on described on-site programmable gate array FPGA, connect optical transceiver module.

3. FC network dual-port artificial card according to claim 2, is characterized in that: the model of described optical transceiver module is FTRJ-8519-1-2.5.

4. FC network dual-port artificial card according to claim 1 and 2, is characterized in that: connection data buffer storage FLASH, static random access memory SRAM and PCI-EXPRESS X4 interface on described on-site programmable gate array FPGA.

5. FC network dual-port artificial card according to claim 1, is characterized in that: the model of the first described reference clock chip is MAX DS4106.

6. FC network dual-port artificial card according to claim 1, is characterized in that: the model of the second described reference clock chip is MAX DS4212.