CN206282271U

CN206282271U - A kind of Serial Ports Extension System based on FPGA

Info

Publication number: CN206282271U
Application number: CN201620986602.3U
Authority: CN
Inventors: 高峰; 崔文梅; 徐成; 刘勇; 陶思磊; 莫翟; 刘雪侠; 马小群
Original assignee: ANHUI XINLONG AUTOMATION Co Ltd
Current assignee: ANHUI XINLONG AUTOMATION Co Ltd
Priority date: 2016-08-30
Filing date: 2016-08-30
Publication date: 2017-06-27
Anticipated expiration: 2026-08-30

Abstract

The utility model discloses a kind of Serial Ports Extension System based on FPGA, including controller, it is characterised in that：Described controller is connected with FPGA module, and described FPGA module is connected with serial ports transceiver module.Described FPGA module includes protocol resolution module and dual port RAM module, and described serial ports transceiver module is connected with protocol resolution module, and described protocol resolution module is connected with dual port RAM module, and described dual port RAM module is connected with controller.The utility model has the advantages that realizing that FPGA possesses enough I/O port resources as the hardware of serial ports expansion using FPGA, the fpga chip of different number of pins, reduces cost according to different demands, can be selected.Take GPIO mouthfuls of resource of controller few.And FPGA can make the parallel gathered data of serial ports, and the data of collection are stored in the dual port RAM of design, controller only be responsible for extract data and and upper machine communication, greatly improve communication efficiency.

Description

A kind of Serial Ports Extension System based on FPGA

Technical field

The utility model is related to a kind of serial expanded circuit system, more particularly to a kind of serial ports expansion realized based on FPGA System.

Background technology

In commercial Application, we are frequently encountered a controller needs the scene of multiple serial ports.But in controller MCU chip resource in only one of which or two serial port resources, so we need to use serial port extended chip.In market Extended chip species is a lot of, such as SC16C654, can extend 4 serial ports.If now we will extend the serial ports money of more than 4 Source, it is necessary to multi-disc SC16C654.At this moment we will run into the feelings that design cost is higher and occupancy MCU is more GPIO mouthfuls Scape, the design to us brings many troubles.And serial port extended chip by MCU control carry out serial port data acquisition when Wait, work that can only be serial so have impact on the efficiency of serial communication.Therefore controller expanded circuit cost of the prior art High, circuit is complicated, it is impossible to meet the demand of practical application.

Utility model content

The purpose of this utility model is to solve the less defect of existing controller chip serial ports, there is provided a kind of serial ports expansion System, increases serial ports number.

In order to achieve the above object, the technical solution of the utility model is as follows：

The utility model includes controller, it is characterised in that：Described controller is connected with FPGA module, described FPGA Module is connected with serial ports transceiver module.

Described FPGA module includes protocol resolution module and dual port RAM module, described serial ports transceiver module and agreement Parsing module is connected, and described protocol resolution module is connected with dual port RAM module, and described dual port RAM module connects with controller Connect.

Described dual port RAM module is connected by address bus and data/address bus with controller.

The model RSM3485 of described serial ports transceiver module.

The utility model has the advantages that being realized as the hardware of serial ports expansion using FPGA, FPGA possesses enough I/O port money Source, according to different demands, can select the fpga chip of different number of pins, reduces cost.Take GPIO mouthfuls of resource of controller It is few.And FPGA can make the parallel gathered data of serial ports, the data of collection are stored in the dual port RAM of design, controller Only be responsible for extract data and and upper machine communication, greatly improve communication efficiency.

Brief description of the drawings

The utility model is described further below in conjunction with the accompanying drawings.

Fig. 1 is structured flowchart of the present utility model.

Fig. 2 is serial ports transceiver module schematic diagram.

Reference in figure is respectively：1. serial ports transceiver module；2.FPGA modules；3. protocol resolution module；4. twoport RAM module；5. controller.

Specific embodiment

As shown in figure 1, for the serial ports number of extending controller, the utility model includes controller 5, controller 5 and FPGA Module 2 is connected, and FPGA module 2 is connected with serial ports transceiver module 1.FPGA module 2 includes protocol resolution module 3 and dual port RAM mould Block 4, serial ports transceiver module 1 is connected with protocol resolution module 3, and protocol resolution module 3 is connected with dual port RAM module 4, dual port RAM Module 4 is connected with controller 5.FPGA module 2 includes protocol resolution module 3 and dual port RAM module 4.Protocol resolution module 3 is main Bag is unpacked and organized for different protocol massages, and the data that serial ports transceiver module 1 is transmitted through are unpacked, will be effective Data are reached in dual port RAM module 4；The data that dual port RAM module 4 is transmitted through are packaged, is sent to serial ports transceiver module 1。

Dual port RAM module 4 is connected by address bus and data/address bus with controller 5.Dual port RAM module 4, mainly bears The controller of duty and upper end carries out data interaction.It is kept in the data that protocol resolution module is passed over, according to upper end Controller 5 send request, the data being consistent with request address are uploaded to controller 5；The control of the upper end that will be received simultaneously The control command of device processed 5, is issued in protocol resolution module 3.Serial ports transceiver module 1 is mainly responsible for the data transmit-receive behaviour of serial ports Make, the data that will be received are sent in protocol resolution module 3, while the data that protocol resolution module 3 is transmitted, are sent out by sending mouth See off.

The model RSM3485 of serial ports transceiver module 1.As described in Figure 2, serial ports transceiver module 1 includes receiver module and hair Module is sent, sending module includes that fifo module, serial ports send top layer control module and serial ports sending module, and data pass through agreement solution Analysis module is sent to fifo module, and top layer control module and serial ports sending module are sent by data is activation then in turn through serial ports Go out；Receiver module includes that fifo module, serial ports receive top layer control module and serial ports receiver module, and data sequentially pass through serial ports Receiver module, serial ports are sent to protocol resolution module after receiving top layer control module and fifo module.Outlet transceiver module design The characteristics of be portable relatively strong, when we need N number of serial interface, we just can be with the N number of serial ports transmitting-receiving mould of directly transplanting Block.As long as by just can be with the IO one-to-one corresponding of corresponding pin and FPGA.Simultaneously it is to be noted that in the utility model The place do not mentioned can be realized using prior art.Therefore be not described in detail in the utility model.

The present invention is exemplarily described above in conjunction with accompanying drawing, it is clear that the utility model is implemented not by above-mentioned The limitation of mode, if the improvement of the various unsubstantialities that technical solutions of the utility model are carried out is employed, or not improved general Design of the invention and technical scheme directly apply to other occasions, within protection domain of the present utility model.

Claims

1. a kind of Serial Ports Extension System based on FPGA, including controller (5), it is characterised in that：Described controller (5) with FPGA module (2) is connected, and described FPGA module (2) is connected with serial ports transceiver module (1)；Described FPGA module (2) includes Protocol resolution module (3) and dual port RAM module (4), described serial ports transceiver module (1) are connected with protocol resolution module (3), institute The protocol resolution module (3) stated is connected with dual port RAM module (4), and described dual port RAM module (4) is connected with controller (5).

2. a kind of Serial Ports Extension System based on FPGA as claimed in claim 1, it is characterised in that：Described dual port RAM mould Block (4) is connected by address bus and data/address bus with controller (5).

3. a kind of Serial Ports Extension System based on FPGA as claimed in claim 1, it is characterised in that：Described serial ports transmitting-receiving mould The model RSM3485 of block (1).