CN209517382U - A kind of ZYNQ processing system for video based on H264 - Google Patents
A kind of ZYNQ processing system for video based on H264 Download PDFInfo
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Abstract
The utility model discloses a kind of ZYNQ processing system for video based on H264, comprising: high-definition camera, infrared camera, ZYNQ chip, external memory chip and OLED display screen in ZYNQ chip；The video of acquisition is streamed in the ZYNQ chip by the high-definition camera and infrared camera, and the ZYNQ chip and memory chip are bi-directionally connected, and the OLED display screen is connect with the ZYNQ chip, for showing ZYNQ chip processing rear video stream.The utility model is realized carries out H264 video coding and decoding technology HD video encoding and decoding in the system that single ZYNQ chip designs, so that video stores occupied space very little, in addition have the advantages that single chip physics area occupied is small, logic area occupied is small, high transfer rate, high-performance, small power consumption, low latency.
Description
Technical field
The utility model relates to coding and decoding video fields, and in particular to a kind of ZYNQ video processing system based on H264
System.
Background technique
For ZYNQ chip as single SOC double-core chip, inside is divided into the ARM core of double A9 as master control, the i.e. part PS, separately
Outer a part is programmable logic device, the i.e. part PL.Each processor has the (resistance of independent SIMD multi-media processing engine
ON), memory management unit (MMU) and Ll instruction and data cache.Each ARM Cortex A9 processor mentions for SCU
2 AXI main interfaces have been supplied, have been 64 bit instruction interfaces and 64 data-processing interfaces respectively.According to address and attribute difference, processing
Task will by route assignment on piece memory (OCM), mouth cache, DDR memory, or by the end PS be connected internally to from
Equipment or the end PL.The interface of each processor and SCU provide Ll data high-speed caching for processor and shared mouth high speed is slow
Consistency monitoring signal between depositing.ARM Cortex A9 and its subsystem additionally provide complete necessary to user security
TrustZone extends function.ARM Cortex A9 processor also achieves necessary hardware capability, provide program debugging and with
Track, which generates, to be supported.The processor additionally provides hardware counter to collect the operation information of simultaneously statistical disposition device and memory system.
H264 video decompression technology is very useful in video processing, with very high data compression ratio, simultaneously
It is also by engineers and research staff institute due to low bit- rate, the advantages such as high quality graphic, fault-tolerant ability is strong, network adaptability is strong
Favor.
To the encoding and decoding of video using being also weak in existing ZYNQ system design, there are still occupied spaces for video storage
Greatly, the problem of poor video quality；For the system of other main control processors design, then it is short of similar to the flexible programmable in ZYNQ
Parallel processing of logical device etc. improves system performance, even if FPGA can be cooperated to use, but is non-single chip, occupies
The disadvantages of area is big, and power consumption is big.
Utility model content
Purpose of utility model: for overcome the deficiencies in the prior art, the utility model provides a kind of ZYNQ based on H264
Processing system for video, the system can solve the disadvantages such as video storage area occupied is big, and power consumption is big, and transmission rate is low.
Technical solution: the ZYNQ processing system for video described in the utility model based on H264, comprising: high-definition camera,
Infrared camera, ZYNQ chip, external memory chip and OLED display screen in ZYNQ chip；The high-definition camera and red
The video of acquisition is streamed in the ZYNQ chip by outer camera, and the ZYNQ chip and memory chip are bi-directionally connected.Institute
It states OLED display screen to connect with the ZYNQ chip, for showing ZYNQ chip processing rear video stream.
Preferably, encapsulation two H.264IP core encoder, H.264IP a core decoder, OSD in the ZYNQ chip
H.264_2 IP kernel and AXI4-Stream to video out IP kernel, the H.264IP core encoder are denoted as respectively,
H.264_3, the video flowing H.264_2 and H.264_3 acquired respectively to high-definition camera and infrared camera encodes,
And respectively stored video stream data into the memory chip by the VDMA of ZYNQ, it is described to be connect with the memory chip,
For being decoded to data of the storage into memory chip, the OSD IP kernel is connected with the H.264IP core decoder,
QT data flow for removing to decoded data and VDMA0 is overlapped processing, the AXI4-Stream to video
Out IP kernel is connect with the OSD IP kernel, for carrying out output processing to the video stream data after superposition processing.
Preferably, double OLED display screens are also encapsulated in the ZYNQ chip and drive IP kernel mdp02, with AXI4-Stream
One output of to video out IP kernel is connected, the driving shown as video.
Preferably, also encapsulate a H.264IP core encoder in the ZYNQ chip, be denoted as H.264_1 with RGB core,
The RGB core is used to carry out the conversion of standard rgb format, input terminal and the AXI4-Stream to the video stream data of output
To video out IP kernel connection, output end be H.264_1 connected, the output end H.264_1 and the memory chip company
It connects, is encoded for the video stream data after being converted to format, and the result after coding is stored into the memory chip
In case used in QT application.
H.264_0 and RGB2YUV preferably, a H.264IP core encoder is also encapsulated in the ZYNQ chip, be denoted as
Core, the input terminal of the RGB2YUV core connect with the output end of the AXI4-Stream to video out IP kernel, are used for
Rgb format is converted into yuv format, then is H.264_0 encoded by described, the output end H.264_0 and described interior
Chip is deposited to be connected.
Preferably, it is described H.264_0, H.264_2 and H.264_3 H.264_1, encoded for the H.264IP core of same model
Device.
Preferably, the H.264IP core includes for accessing rambus and reading the S00_AXIS interface of original image
With the S00_AXI interface of M00_AXIS interface and access internal register.
Preferably, the S00_AXI interface type is AXI_LITE, the S00_AXIS interface and M00_AXIS interface
Type is AXI4-Stream.
The utility model has the advantages that the utility model is realized is what single ZYNQ chip designed by H.264 video coding and decoding technology
HD video encoding and decoding are carried out on system, so that video stores occupied space very little, 1080p 30fps, double-core is may be implemented in monokaryon
The HD video that 1080p@60fps may be implemented shows that the HD video that 4K@30fps may be implemented in three cores is shown, and required deposits
It is minimum to store up space, in addition with single chip physics area occupied is small, logic area occupied is small, high transfer rate, high-performance, function
The advantages of consuming small, low latency.
Detailed description of the invention
Fig. 1 is system architecture diagram described in the utility model；
Fig. 2 is the structural schematic diagram of video processing part described in the utility model；
Fig. 3 is ZYNQ chip interior video processing block diagram described in the utility model；
Fig. 4 is H.264IP core described in the utility model；
Fig. 5 is the encoding software control flow chart based on ZYNQ processing system for video H.264；
Fig. 6 is the decoding software control flow chart based on ZYNQ processing system for video H.264；
Fig. 7 is the H.264 synthesis result figure based on ZYNQ processing system for video H.264.
Specific embodiment
Technical solution used by the utility model is by also make outside hardware-accelerated design to entire ZYNQ system
Entire video flowing is handled with H.264 video coding and decoding technology designed, designed and the IP kernel of encapsulation, then by video into
It is stored after row coding compression, occupied space is very small and does not influence its video quality, is finally carried out again by video decoding high
Clear output display.This scheme has many advantages, such as to save memory space, improves performance, high transfer rate, low-power consumption, low latency.
This programme specifically uses single SoC chip, and model xc7z020 inside has the part PS and PL, and the side PS is by double ARM groups
At being mainly used for QT application system, the side PL is made of programmable logic device, is mainly used for logical gate.Whole system is by regarding
Frequency processing part and control section composition.Video processing part includes importation, inter-process part, overlapping portion, output
Part is handled video flowing using H.264 technology in video processing part.Control section is mainly that the side PL and the side PS carry out
Control the communication of signal and agreement.
Fig. 1 show the system architecture diagram based on ZYNQ processing system for video H.264.In the architecture, mainly by two
Most of composition, a part is BlockDesign, and another part is MicroBlaze, is predominantly regarded in BlockDesign
Frequency stream process and the H.264 design of equal processing part, MicroBlaze are the design of the control section of system.
As shown in Fig. 2, video flow processing and the H.264 design of equal processing part include: high-definition camera 1, infrared photography
First 2, ZYNQ chip 3, external memory chip 4 and OLED display screen 5 in ZYNQ chip；CMOS high-definition camera is defeated all the way
Enter: resolution ratio 1280*1024, maximum 50Hz；Infrared camera IR is inputted all the way: resolution ratio 1080p, 25Hz, by acquisition
Video is streamed in the ZYNQ chip 3, and the ZYNQ chip 3 and memory chip 4 are bi-directionally connected, and the memory chip uses
DDR3 or DDR4 memory.The OLED display screen 5 is connect with the ZYNQ chip 3, for showing that ZYNQ chip 3 handles rear video
Stream.
As shown in figure 3, ZYNQ chip in encapsulation two H.264IP core encoder, one H.264IP core decoder 31,
OSD IP kernel 32 and AXI4-Stream to video out IP kernel 33, the H.264IP core encoder is denoted as respectively
H.264_2, H.264_3, the video that H.264_2 and H.264_3 high-definition camera 1 and infrared camera 2 are acquired respectively
Stream is encoded, and before the coding, the data stream reception IP kernel of BT_IN and IR_IN camera acquisition acquires video flowing first, and
Video stream data is stored into the memory chip by the VDMA1 and VDMA2 of ZYNQ chip respectively, ZYNQ chip with it is described
Memory chip connection, for being decoded to data of the storage into memory chip, the OSD IP kernel 32 with it is described H.264IP
Core decoder is connected, and is denoted as decoder IP core H.264_4, the QT data for removing to decoded data with VDMA0 flow into
Row superposition processing, the AXI4-Stream to video out IP kernel are connect with the OSD IP kernel, for superposition processing
Video stream data afterwards carries out output processing, and mdp02 is that double OLED display screens drive IP kernel, the driving as OLED display screen.
In this design, related H.264 relevant IP kernel and processing design are designated.In the data flow block diagram, wherein
H.264 it is substantially carried out the encoding and decoding processing to video.H.264_2, H.264_3 the data flow of two paths of data acquisition passes through respectively
Coded treatment, compressed data flow will be encoded by VDMA1 and VDMA2 and carry out data-moving to corresponding storage sky
Between, then by alternative pass through again VDMA5 moved with scale operate, arrive other memory space afterwards, then will be newest
H.264_4, data flow is moved by VDMA3 is decoded operation, then enters OSD together with the QT data flow that VDMA0 is removed
IP kernel is overlapped processing, finally carries out output again and shows.The result data stream of output passes through RGB core 33 all the way and is converted into standard
Rgb format data flow, using H.264_1 performing the encoding operation, as a result by VDMA4 by data flow be stored in corresponding storage space with
Used in standby QT application.Another way carries out for rgb format being converted into yuv format by RGB2YUV core, then by H.264_0 being compiled
Code operates, and the result after coding carries out Y, U, V component separation, then by VDMA6, VDMA7, VDMA8 that data deposit is respective respectively
Memory headroom in case QT application used in.
H.264_2 and H.264_3 wherein, H.264_0, H.264_1, be H.264IP core encoder, H.264_4 for
H.264IP core decoder, according to this, H.264 encoding and decoding principle carries out designed, designed and encapsulates suitable for the technical solution
H.264IP core is as shown in Figure 4.The present embodiment, can by coding framework and decoding frame based on ZYNQ processing system for video H.264
To know, encoding and decoding principle H.264.Based on this principle designed, designed with encapsulation based on ZYNQ video processing system H.264
System H.264IP core as shown in figure 4, wherein S00_AXI interface be AXI_LITE type, be mainly used for access internal register；
S00_AXIS and M00_AXIS interface is the bus for accessing memory, reads original image, reads reference frame image, write-in reconstruction figure
The interface of picture, write-in encoding code stream；Frm_lcnt_cap input signal is just useful only under encoder low-delay mode.It indicates
Front end grabgraf module is toward the how many row raw image datas of write-in inside DDR.If it is 1080p format.In a frame grabgraf knot
Shu Hou, this value should set 1088.Core_int signal is interrupt signal, every one frame of encoding or decoding, is generated in primary
It is disconnected, software can be carried out and write register " OE " clear 0, it also can automatically clear 0 in the new frame of software starting.Based on H.264
ZYNQ processing system for video in H.264 using monokaryon encoding-decoding efficiency be 1080p@30fps:110MHz (CAVLC)/
130MHZ (CABAC), 720P@30fps:50MHZ (CAVLC)/58MHZ (CABAC), area 36Block RAMs.Coding mode
Bandwidth demand be I frame: about 1.1~1.2 times of primitive frame bandwidth, P frame: about 5.5~5.8 times of primitive frame bandwidth,
Bandwidth of this bandwidth without primitive frame write-in memory.
Decoding mode bandwidth demand is 1.1~1.2 times of primitive frame bandwidth of I frame:About, P frame:About
4.2~4.5 times of primitive frame bandwidth.H.264 comprehensive speed is 166MHZ (CAVLC)；150MHZ (CABAC), Fig. 7 be based on
H.264 the H.264 synthesis result of ZYNQ processing system for video, the figure are to be only in designed, designed H.264IP core (encoder
With decoder) encapsulation it is comprehensive when, occupied ZYNQ resource results figure.1080p@30fps, double-core may be implemented in monokaryon
May be implemented 1080p@60fps, three cores may be implemented 4K@30fps, and intraframe coding allow H.264 encoder realize that frame frequency prolongs
Late, macroblock pipelined architecture design then further decreases delay: about 0.3 millisecond.The pipeline design is supported at each clock
Eight pixels are managed, realize that real-time 4K@60fps Video coding, HD video memory space are minimum.
For the present embodiment based on ZYNQ processing system for video H.264, Fig. 5 is based on ZYNQ processing system for video H.264
Encoding software control flow chart, preparation first and detects original image, if be ready to complete, is just configured matching H.264
Register and other registers are set, judge whether that receiving coding interrupts, and continues to test if not, if triggering is interrupted,
Carry out corresponding registers read operation, then remove interrupt flag bit, from memory read walk encoding code stream, after continue prepare original graph
Picture.Fig. 6 is the decoding software control flow chart based on ZYNQ processing system for video H.264, has first prepared decoded bit stream
Finish, software decoding PPS/SPS/Slice Header is carried out if ready, the configuration of each register is then carried out, configures
It detects whether to receive decoding discontinuities after the completion, interrupt flag bit is removed if receiving, walk to decode image from Memory reading, it is subsequent
It is continuous to prepare decoded bit stream.
Claims (8)
1. a kind of ZYNQ processing system for video based on H264 characterized by comprising high-definition camera, infrared camera,
ZYNQ chip, external memory chip and OLED display screen in ZYNQ chip；The high-definition camera and infrared camera will
The video of acquisition is streamed in the ZYNQ chip, and the ZYNQ chip and memory chip are bi-directionally connected, and the OLED is shown
Screen is connect with the ZYNQ chip, for showing ZYNQ chip processing rear video stream.
2. the ZYNQ processing system for video according to claim 1 based on H264, which is characterized in that in the ZYNQ chip
Encapsulation two H.264IP core encoder, H.264IP core decoder, OSD IP kernel and an AXI4-Stream to video
Out IP kernel, H.264_2 the H.264IP core encoder is denoted as respectively, H.264_3, described H.264_2 and H.264_3 to distinguish
The video flowing acquired to high-definition camera and infrared camera encodes, and respectively by the VDMA of ZYNQ by video stream data
It stores in the memory chip, it is described to be connect with the memory chip, for being carried out to data of the storage into memory chip
Decoding, the OSD IP kernel are connected with the H.264IP core decoder, the QT number for removing to decoded data and VDMA
Superposition processing is carried out according to stream, the AXI4-Stream to video out IP kernel is connect with the OSD IP kernel, for folded
Adding treated, video stream data carries out output processing.
3. the ZYNQ processing system for video according to claim 2 based on H264, which is characterized in that in the ZYNQ chip
It also encapsulates double OLED display screens and drives IP kernel mdp02, an output phase with AXI4-Stream to video out IP kernel
Even, the driving shown as video.
4. the ZYNQ processing system for video according to claim 2 based on H264, which is characterized in that in the ZYNQ chip
A H.264IP core encoder is also encapsulated, is denoted as H.264_1 with RGB core, the RGB core is for the video stream data to output
Carry out standard rgb format conversion, input terminal are connect with the AXI4-Stream to video out IP kernel, output end with
H.264_1 it is connected, the output end H.264_1 is connect with the memory chip, for the video fluxion after converting to format
It stores into the memory chip according to being encoded, and by the result after coding in case used in QT application.
5. the ZYNQ processing system for video according to claim 4 based on H264, which is characterized in that in the ZYNQ chip
Also encapsulate a H.264IP core encoder, be denoted as H.264_0 with RGB2YUV core, the input terminal of the RGB2YUV core with it is described
The output end of AXI4-Stream to video out IP kernel connects, and for rgb format to be converted into yuv format, then passes through institute
It states and is H.264_0 encoded, the output end H.264_0 is connected with the memory chip.
6. according to the described in any item ZYNQ processing system for video based on H264 of claim 2-5, which is characterized in that described
It H.264_0, H.264_1, H.264_2 and is H.264_3 the H.264 IP kernel encoder of same model.
7. the ZYNQ processing system for video according to claim 6 based on H264, which is characterized in that the H.264 IP kernel
Including the S00_AXIS interface and M00_AXIS interface for accessing rambus and reading original image and access internal post
The S00_AXI interface of storage.
8. the ZYNQ processing system for video according to claim 7 based on H264, which is characterized in that the S00_AXI connects
Mouth type is AXI_LITE, and the S00_AXIS interface and M00_AXIS interface type are AXI4-Stream.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929690A (en) * | 2021-01-22 | 2021-06-08 | 中国人民解放军32181部队 | Video fractional order differential operator enhancement system and implementation method thereof |
| CN113727161A (en) * | 2021-09-03 | 2021-11-30 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
-
2018
- 2018-12-14 CN CN201822103632.7U patent/CN209517382U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112929690A (en) * | 2021-01-22 | 2021-06-08 | 中国人民解放军32181部队 | Video fractional order differential operator enhancement system and implementation method thereof |
| CN113727161A (en) * | 2021-09-03 | 2021-11-30 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
| CN113727161B (en) * | 2021-09-03 | 2022-07-29 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
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Effective date of registration: 20211022 Address after: No.2 Tianyu Road, high tech Zone, Chengdu, Sichuan 610000 Patentee after: GUORONG TECHNOLOGY Co.,Ltd. Address before: Room 1002, No. 301, Hanzhongmen street, Gulou District, Nanjing, Jiangsu 210036 Patentee before: CHINA COMMUNICATION TECHNOLOGY (NANJING) Co.,Ltd. |