CN102970546B - Video encoding unit and its implementation - Google Patents
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Abstract
The invention discloses a kind of video encoding unit and its implementation, this video encoding unit comprises DVI video interface chip etc., DVI video interface chip, LVDS video interface chip is all connected with the first bus-selection switch, DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip is all connected with CPLD chip, rgb video interface chip, YPbPr video interface chip is also all connected with the second bus-selection switch, first bus-selection switch, second bus-selection switch, CPLD chip is connected with asic chip, asic chip is connected with bridging chip.The present invention have be easy to exploitation, low in energy consumption, performance high, the needs of airborne HD video register system can be met completely.
Description
Technical field
The present invention relates to a kind of coding unit, particularly relate to a kind of video encoding unit and its implementation.
Background technology
Video recording device is the device being specifically designed to record Cockpit Display device video pictures in avionics system, all flight control interfaces in flight course are intactly recorded in non-volatile storage medium by it, Ground analysis after terminating for flight, video recording device is primarily of video encoding unit, main control unit, memory cell is formed, signal flow graph as shown in Figure 1, video encoding unit receives multi-path high-definition video and carries out compression coding to it, main control unit is given by the bit stream data compressed by PCIE bus, main control unit is responsible for packing to bit stream data, file management, finally be sent in memory cell and preserve.
Video encoding unit is the part of most critical in video recording device, because the quality of video coding performance directly determines the quality of picture quality, also the demand of remote-effects to video recording device internal bus data throughput and the capacity requirement of rear end storage medium, at present, the H.264/AVC standard that the joint video team (JVT) that video encoding standard adopts ISO/IEC and ITU-T to form mostly is formulated, and realize this standard and can pass through number of ways, realize as adopted the mode running video compression algorithm on a cpu or dsp, the soft coding of namely what is often called, or adopt FPGA(Field-Programmable Gate Array, field programmable gate array) chip realizes the coded treatment to video by the means of field programming, but more or less all there are some inevitable defects in aforesaid way, soft coded system technical difficulty is large, exploitation threshold is high, construction cycle is long and head end video interface chip selects face little, although and the coding adopting the mode of fpga chip can realize multi-channel video more neatly, but because fpga chip is while achieving Video coding, inner redundancy unit is still in running order, cause power consumption larger.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of video encoding unit and its implementation, its have be easy to exploitation, low in energy consumption, performance high, the needs of airborne HD video register system can be met completely.
The present invention solves above-mentioned technical problem by following technical proposals: a kind of video encoding unit, is characterized in that, it comprises DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip, first bus-selection switch, second bus-selection switch, CPLD chip, asic chip, bridging chip, DVI video interface chip, LVDS video interface chip is all connected with the first bus-selection switch, DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip is all connected with CPLD chip, rgb video interface chip, YPbPr video interface chip is also all connected with the second bus-selection switch, the first bus-selection switch, second bus-selection switch, CPLD chip is connected with asic chip, and asic chip is connected with bridging chip, DVI video interface chip, LVDS video interface chip, rgb video interface chip, the effect of YPbPr video interface chip is the digital video modes that asic chip can accept by the Video Quality Metric of the various different-formats of input, and the first bus-selection switch and the second bus-selection switch select a wherein railway digital vision signal output according to the level signal that asic chip GPIO exports.
Preferably, described asic chip comprises the interface such as video input module, video pre-filtering module, H.264 coding engine, CPU module, DDR controller module, clock module, GPIO module, I2C module, pci interface, RS232 debug serial port, JTAG debug port; Video input module receives the digital video signal of input, and carry out decoding process to it, output stream waits for video pre-filtering to buffering area; Video pre-filtering module performs the operations such as de interlacing, denoising, OSD superposition to video; H.264 coding engine is responsible for H.264 encoding to video, carries out coded treatment according to the frame per second arranged, quantization parameter, code stream size, Rate Control mode, key frame interval to video; CPU module is the control unit of asic chip inside, it manages scheduling and the execution of whole chip task; DDR controller module is the interface between memory request person and DDR memory, it performs all DDR memory controlling functions and goes to support from the read-write operation of user interface, makes user logic access DDR memory without the need to considering the control of DDR memory and clock problem; Clock module receives outside clock signal and produces the dominant frequency clock of CPU module and the work clock of DDR memory needs by inner PLL circuit; GPIO module for generating or gather output or the input signal of application-specific, as low and high level signal or rising, trailing edge signal; I2C module, by the serial interface devices of I2C bus marco outside, as video interface chip, meets the demand of different video interface; The inner integrated pci bus controller of pci interface, the final data of Video coding will output to PCI main equipment or bridging chip by pci interface, and PCI main equipment is also by the internal resource of pci bus access asic chip; RS232 debug serial port exports the work state information of asic chip, can the working condition of Real Time Observation chip; JTAG debug port is used for debugging, can the resource of Computer Aided Design personnel read-write chip inside.
The present invention also provides a kind of implementation method of video encoding unit, it is characterized in that, it comprises the following steps:
Step one: select asic chip type selecting; Asic chip is as the master chip of Video coding, powerful video encoding capability must be possessed, support H.264Main profile and Baseline profile video compression format, at least possess the ability that two-way HD video is encoded simultaneously, there is video processing function and peripheral interface;
Step 2: select video interface chip type selecting; Need with different interface chips for different video inputs, primary signal is converted to the digital video that asic chip can receive by video interface chip;
Step 3: PCI to PCIE general line system; This step need according to asic chip interface type determine the need of, if asic chip itself has PCIE bus interface, then this step does not need, if asic chip is pci bus interface, then need the conversion of PCI to PCIE bus, general line system can be completed by increase cpu chip or bridging chip;
Step 4: the logic realization of CPLD chip, CPLD chip completes the logic control of video encoding unit, is produced the signal of video encoding unit needs by Received signal strength.
Positive progressive effect of the present invention is: the present invention is that the video encoding unit of Airborne Video Recording System inside provides a kind of new realization means, it is strong that it takes full advantage of asic chip specificity, efficiency is high, realize simple feature, coordinate different video interface chips can realize the compression coding of multiple different pattern of the input video, external bus adopts PCIE bus to be cross-linked with main control unit, annexation is simple, efficiently, CPLD chip is adopted to realize some simple necessary logic controls, decrease the use of a large amount of control chip, in addition, the efficient and rational advanced person of global design of the present invention, power consumption comparatively like product has absolute predominance, unprecedented change will be brought for Airborne Video Recording System.
Accompanying drawing explanation
Fig. 1 is the theory diagram of existing video recording device.
Fig. 2 is the theory diagram of video encoding unit of the present invention.
Fig. 3 is the theory diagram of asic chip in the present invention.
Fig. 4 is the function schematic block diagram of video encoding unit of the present invention.
Embodiment
Present pre-ferred embodiments is provided, to describe technical scheme of the present invention in detail below in conjunction with accompanying drawing.
As shown in Figure 2, video encoding unit of the present invention comprises DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip, first bus-selection switch, second bus-selection switch, CPLD(Complex Programmable Logic Device, CPLD) chip, ASIC(Application Specific Integrated Circuit, application-specific integrated circuit (ASIC)) chip, bridging chip, DVI video interface chip, LVDS video interface chip is all connected with the first bus-selection switch, DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip is all connected with CPLD chip, rgb video interface chip, YPbPr video interface chip is also all connected with the second bus-selection switch, first bus-selection switch, second bus-selection switch, CPLD chip is connected with asic chip, asic chip is connected with bridging chip.
The effect of video interface chip (comprising DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip etc.) is the digital video modes that asic chip can accept by the Video Quality Metric of the various different-formats of input, is generally 24bit RGB (8:8:8) or 16bit YCbCr4:2:2 pattern; Because single asic chip generally processes 2 road HD videos, when input four road HD video, four can be realized by two bus-selection switch and select two, namely the first bus-selection switch selects the railway digital video frequency output that DVI or LVDS video interface chip exports, the railway digital video frequency output that the second bus-selection switch selects RGB or YPbPr video interface chip to export; CPLD chip realizes detecting with presence or absence of head end video; The 2 road HD videos of asic chip to input carry out compression coding H.264 and give bridging chip by coded data by pci bus; Bridging chip realizes the conversion of pci bus to PCIE bus, and the PCIE bus realizing same main control unit connects.
DVI video interface chip type selecting has kinds of schemes to select, the conventional AD9388 having TFP401 and the ADI company designs of TI company designs, the maximum video resolution that two chips are supported is all UXGA(1600 × 1200), maximum pixel frequency is 165MHz, so can receive the DVI vision signal of single TMDS chain.Two chip differences are: TFP401 digital video exports as 24bit RGB (8:8:8) pattern, and AD9388 is 16bit YCbCr4:2:2 pattern.
LVDS video interface chip selects the DS90CF384MTD of National Semiconductor, it supports that resolution sizes has VGA(640 × 480), SVGA(800 × 600), XGA(1024 × 768), DS90CF384MTD chip can receive A0-A2 serial signal or A0-A3 serial signal, and be translated into 18bit RGB (6:6:6) single pixel format or 24bit RGB (8:8:8) single pixel format, when exporting as 18bit RGB (6:6:6), can by the mode of low two ground connection of RGB being treated as 24bitRGB (8:8:8) process.
Rgb video is divided into 5 line rgb videos and 3 line rgb videos, 5 line RGB represent that synchronizing signal H, V are independent of RGB, and 3 line RGB represent that H, V are embedded in G-signal, rgb video interface chip can select ADV7401 and AD9883 of ADI company designs, analog rgb video is converted into 16bit YCbCr4:2:2 pattern by ADV7401 chip, and analog rgb video is converted into 24bit RGB (8:8:8) pattern by AD9883 chip;
YPbPr video is color difference components Interface Video, by Y, Pb, Pr signal of simulation separately, three cables are used to carry out individual transmission, ensure the accuracy of color rendition, the input of color difference signal is all supported in a lot of field at present, as HDTV (High-Definition Television), YPbPr video interface chip can select the ADV7401 of ADI company designs, and simulation YPbPr video is converted into 16bit YCbCr4:2:2 pattern by ADV7401 chip;
First bus-selection switch and the second bus-selection switch select a wherein railway digital vision signal export and be sent to the VIDEOINPUT mouth of asic chip according to the level signal that asic chip GPIO exports, first bus-selection switch, the second bus-selection switch can select the SN74CB3516212 type switch of TI company designs, and it is a 12 BITBUS network selector switches;
CPLD chip adopts the XC95144XL-7CSG144I cake core of Xilinx company designs, the DE signal be mainly used in video interface chip exports judges, if there is video input, DE signal is the waveform signal of rule, a high level signal can be exported by the logical operation of CPLD inside to hold to the GPIO of asic chip, if without video input, DE signal is improper waveform signal, then CPLD exports a low level signal to GPIO end, and the low and high level that asic chip is held by GPIO can be known with or without video input.Other logic controls of video interface unit also can be completed by CPLD chip, as the multi-mode generation etc. selecting output, clock.
In order to encode to 2 road HD videos, we need to have selected a high performance asic chip, the Hi35 series of Hai Si semiconductor company and the FH87 family chip of the vast company designs of richness can both meet demand of the present invention, they adopt pure hardware mode to complete and H.264 encode, the digital video receiving various ways can be coordinated with various video interface chip, have Video coding option flexibly to arrange and abundant video pre-filtering function, lower power consumption and less encapsulation ensure that its job stability and ease for use.
In order to realize interconnected with PCIE bus of PCI, present invention uses PCI-PCIE bridging chip PEX8114-BC13BI G, this chip is simple and easy to use, and area is little is easy to layout, and power consumption is little is easy to heat radiation and stable.
In sum, video encoding unit of the present invention selects a asic chip with pci bus to realize encoding to 2 road HD videos simultaneously, the access of DVI video, LVDS video, analog rgb video can be completed, 2 × N(N=1,2,3,4 is realized by selecting N sheet asic chip) extended coding of road video, adopt PCI-PCIE bridging chip to realize PCI to PCIE general line system, thus complete and being cross-linked of main control unit.
As shown in Figure 3, asic chip inside comprises video input module, video pre-filtering module, H.264 coding engine, CPU module, DDR controller module, clock module, GPIO module, I2C module is totally eight modules, also comprise pci interface, RS232 debug serial port, the interfaces such as JTAG debug port, video input module and video pre-filtering model calling, video pre-filtering module is connected with H.264 coding engine, CPU module, DDR controller module is all connected with H.264 coding engine, DDR memory, CPU module is all connected with DDR controller module, I2C module, clock module, GPIO module, pci interface, RS232 debug serial port, JTAG debug port etc. is all connected with CPU module.Video input module receives the digital video signal of input, and carry out decoding process to it, output stream waits for video pre-filtering to buffering area; Video pre-filtering module performs the operations such as de interlacing, denoising, OSD superposition to video; H.264 coding engine is responsible for H.264 encoding to video, carries out coded treatment according to the frame per second arranged, quantization parameter, code stream size, Rate Control mode, key frame interval to video; CPU module is the control unit of asic chip inside, it manages scheduling and the execution of whole chip task; DDR controller module is the interface between memory request person and DDR memory, it performs all DDR memory controlling functions and goes to support from the read-write operation of user interface, makes user logic access DDR memory without the need to considering the control of DDR memory and clock problem; Clock module receives outside clock signal and produces the dominant frequency clock of CPU module and the work clock of DDR memory needs by inner PLL circuit; GPIO module for generating or gather output or the input signal of application-specific, as low and high level signal or rising, trailing edge signal; I2C module, by the serial interface devices of I2C bus marco outside, as video interface chip, meets the demand of different video interface; The inner integrated pci bus controller of pci interface, the final data of Video coding will output to PCI main equipment or bridging chip by pci interface, and PCI main equipment is also by the internal resource of pci bus access asic chip; RS232 debug serial port exports the work state information of asic chip, can the working condition of Real Time Observation chip; JTAG debug port is used for debugging, can the resource of Computer Aided Design personnel read-write chip inside, as register or buffer area, thus debugs video encoding unit efficiently.
As shown in Figure 4, in the present embodiment, video encoding unit needs reception 1 tunnel high definition DVI video, 1 tunnel high definition LVDS video, 1 tunnel high definition rgb video and 1 tunnel high definition YPbPr video, and select any 2 tunnels wherein to carry out real-time compression coding, the bit stream data after coding is sent to main control unit by PCIE high-speed bus.Take asic chip as core, the head end video interface chip different according to different video input format configuration, increase the logic control that CPLD chip is used for video encoding unit, adopt PCI-PCIE bridging chip to realize pci bus to change to the bridge joint of PCIE bus, this implementation method comprises the following steps:
Step one: select asic chip type selecting.Asic chip is as the master chip of Video coding, powerful video encoding capability must be possessed, support H.264Main profile and Baseline profile video compression format, at least possesses the ability that 2 road HD videos (XGA resolution or more) are encoded simultaneously, there is abundant video processing function, comprise de interlacing, denoising, OSD superposes, image scaling etc., there is abundant peripheral interface, as I2C, PCI etc., the digital video of multiple format can be received, as 16bit YCbCr4:2:2, 24bit RGB (8:8:8) and interior External synchronization mode all can be selected.In order to encode to 2 road HD videos, we have selected a high performance asic chip (the Hi35 series of such as Hai Si semiconductor company or the FH87 chip of rich vast company designs), its inside function block diagram as shown in Figure 3, it adopts pure hardware mode to complete and H.264 encodes, the digital video receiving various ways can be coordinated with various video interface chip, have Video coding option flexibly to arrange and abundant video pre-filtering function, lower power consumption and less encapsulation ensure that its job stability and ease for use;
Step 2: select video interface chip type selecting.Airborne HD video register system has various video pattern of the input, common are: analog rgb video, LVDS video, DVI video, need with different interface chips for different video inputs, interface chip can select the Related product of TI company or ADI company.DVI video, LVDS video, rgb video and YPbPr video are the several types that current video field is conventional, also be widely adopted in airborne avionics field, DVI video and LVDS video are the form being carried out transmission of video by dedicated digital interface, there is transmission performance at a high speed and good antijamming capability, rgb video and YPbPr video are more traditional video interface forms, also retain use in a lot of system or equipment always, to encode to the video of these four kinds of interface shapes, the digital video corresponding video interface chip must being selected primary signal to be converted to asic chip can receive, because asic chip can accept multi-form digital video, therefore the selection face of interface chip is very extensive,
Step 3: PCI to PCIE general line system.This step need according to asic chip interface type determine the need of, if asic chip itself has PCIE bus interface, then this step does not need, if asic chip is pci bus interface, then need the conversion of PCI to PCIE bus, general line system can be completed by increase cpu chip or bridging chip., complete the connection to main control unit PCIE bus, have two kinds of modes can complete this conversion:
A () can be interconnected by double bus by bridging chip, bridging chip is as the first order peripheral hardware of main control unit, and asic chip is as the second level peripheral hardware of main control unit;
B () can by adding cpu chip, this cpu chip need have PCI and PCIE bus interface simultaneously, can complete the local link of double bus, can also be separated the partial function of main control unit simultaneously, as video data packing and file management;
Step 4: the logic realization of CPLD chip, CPLD chip completes the logic control of video encoding unit, as generation or the output of some mode bits of some clock signals, produces the signal of some necessity that video encoding unit needs by receiving some signals.Video encoding unit is encoded to video, there is a kind of more special situation, be exactly that video encoding unit just normally inputs at the rear video that works on power, this just causes asic chip cannot identify input video, in order to head it off, we are by increasing CPLD chip, the DE signal that video interface chip exports detected by writing logic and exports low and high level signal to the GPIO mouth of asic chip, once there be video input, the high level signal of GPIO mouth just can be used as asic chip input signal and informs asic chip, thus video is identified and starts coding.
Because video encoding unit adopts asic chip to be main coding chip, ASIC(ApplicationSpecific Integrated Circuits) i.e. application-specific integrated circuit (ASIC), CPU module, H.264 coding engine, video pre-filtering module, DDR controller etc. are integrated in single-chip by it, decrease design volume and weight, simultaneously because of the specificity of chip, do not comprise other redundancy unit, idle is wasted, therefore master-plan power consumption is lower.Further, the design of video encoding unit is centered by asic chip, increases peripheral chip to realize allomeric function, because asic chip is integrated with several functions unit, therefore the simplicity of design of peripheral chip, line reduces, hardware designs is simple, and reliability also will significantly improve; Meanwhile, be integrated with the functional modules such as Video coding engine because of asic chip inside, without the need to additionally developing video compression algorithm, make software development only need the exploitation of the application software for different demand, reducing development difficulty.Further, asic chip is custom-designed for Video coding, combines closely between functional performance design, circuit design, technological design, and the design of this integration will make video encoding unit have unprecedented high-performance.Further, because Video coding realizes in asic chip inside completely, operation principle, data flow, call resource etc. be equivalent to one " black box " for user, enhance confidentiality, more can be applicable to the demand under military airborne circumstance.
Although the foregoing describe the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, under the prerequisite not deviating from principle of the present invention and essence, various changes or modifications can be made to these execution modes.Therefore, protection scope of the present invention is defined by the appended claims.
Claims (3)
1. a video encoding unit, it is characterized in that, it comprises video interface chipset, first bus-selection switch, second bus-selection switch, CPLD chip, asic chip and bridging chip, described video interface chipset comprises DVI video interface chip, LVDS video interface chip, rgb video interface chip and YPbPr video interface chip, DVI video interface chip, LVDS video interface chip is all connected with the first bus-selection switch, DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip is all connected with CPLD chip, rgb video interface chip, YPbPr video interface chip is also all connected with the second bus-selection switch, first bus-selection switch, second bus-selection switch, CPLD chip is connected with asic chip, asic chip is connected with bridging chip,
It is the digital video modes that asic chip can accept that DVI video interface chip, LVDS video interface chip, rgb video interface chip, YPbPr video interface chip are respectively used to the Video Quality Metric of DVI, LVDS, RGB, YPbPr form of input;
First bus-selection switch and the second bus-selection switch select the video interface chip having video input to send into asic chip according to the level signal that asic chip GPIO exports from video interface chipset;
CPLD chip to detect the DE signal that video interface chipset exports by writing logic and to export low and high level signal to the GPIO mouth of asic chip;
Asic chip receives by GPIO mouth the low and high level signal that CPLD chip sends and knows video input state, and controls the first bus-selection switch and the second bus-selection switch by GPIO mouth thus make asic chip identify video and start coding.
2. video encoding unit as claimed in claim 1, it is characterized in that, described asic chip comprises video input module, video pre-filtering module, H.264 coding engine, CPU module, DDR controller module, clock module, GPIO module, I2C module, pci interface, RS232 debug serial port and JTAG debug port; Video input module receives the digital video signal of input, and carry out decoding process to it, output stream waits for video pre-filtering to buffering area; Video pre-filtering module performs de interlacing, denoising, OSD overlap-add operation to video; H.264 coding engine is responsible for H.264 encoding to video, carries out coded treatment according to the frame per second arranged, quantization parameter, code stream size, Rate Control mode, key frame interval to video; CPU module is the control unit of asic chip inside, it manages scheduling and the execution of whole chip task; DDR controller module is the interface between memory request person and DDR memory, it performs all DDR memory controlling functions and goes to support from the read-write operation of user interface, makes user logic access DDR memory without the need to considering the control of DDR memory and clock problem; Clock module receives outside clock signal and produces the dominant frequency clock of CPU module and the work clock of DDR memory needs by inner PLL circuit; GPIO module is for generating or gather output or the input signal of application-specific; I2C module, by the serial interface devices of I2C bus marco outside, as video interface chip, meets the demand of different video interface; The inner integrated pci bus controller of pci interface, the final data of Video coding will output to PCI main equipment or bridging chip by pci interface, and PCI main equipment is also by the internal resource of pci bus access asic chip; RS232 debug serial port exports the work state information of asic chip, the working condition of Real Time Observation chip; JTAG debug port is used for debugging, the resource of Computer Aided Design personnel read-write chip inside.
3. video encoding unit as claimed in claim 2, is characterized in that the output of described application-specific or input signal are low and high level signal or rising, trailing edge signal.
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