CN204131646U - A kind of digital video signal decoder - Google Patents
A kind of digital video signal decoder Download PDFInfo
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- CN204131646U CN204131646U CN201420617605.0U CN201420617605U CN204131646U CN 204131646 U CN204131646 U CN 204131646U CN 201420617605 U CN201420617605 U CN 201420617605U CN 204131646 U CN204131646 U CN 204131646U
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Abstract
The utility model discloses a kind of digital video signal decoder, described video signal decoder comprises server master board, be arranged on the CPU on mainboard, memory, network interface and video signal output interface, memory is provided with SVAC decoding unit, H.264 decoding unit, MPEG-4 decoding unit and self-adaption of decoding switch unit, and described video signal output interface port comprises 8 road bnc interfaces and 8 road DP interfaces.Described digital video signal decoder can improve digital video decoder to ordinary numbers Video Decoder, obtaining stream format information, increasing Decode engine to carry out adaptive decoding by resolving video flowing, comprising SVAC, H.264 and MPEG-4 form; Increase by two kinds of video output interfaces, and switchable multiple converting interface, to access command centre's video wall of different interface type; By optimizing decoding arithmetic element, making real-time decoding export way and can reach 8 road 1080P.
Description
Technical field
The utility model relates to decoder technique field, is specifically related to a kind of digital video decoder.
Background technology
Existing video signal decoder generally can only be decoded SVAC, one H.264 and in the code stream of MPEG-4 compressed encoding form, or only configurable selection one comes into force, and when code stream format conversion, needs to reconfigure selection code/decode format.The interface of common decoder is generally the one in DVI or HDMI or BNC.
Along with issuing and implementation and the application of SVAC standard (Ministry of Public Security and the Ministry of Industry and Information Technology combine the recommendatory standard GB/T/T25724-2010 " safety precaution monitoring digital video-audio encoding and decoding technique require " of formulation), safety monitoring market will have SVAC, H.264 with MPEG-4 tri-kinds of simultaneous situations of video code model.In order to reach the object enabling to meet SVAC, H.264 interconnect with the encoder of MPEG-4 standard, can the video flowing of simultaneously compatible decoding various video compressed encoding form in the urgent need to decoder, and multiple output interface can be had.
Chinese patent ZL 201010255086.4 discloses a kind of Video Decoder, comprises: length-changeable decoding and inverse quantization module fast, performs quick length-changeable decoding and inverse quantization to incoming bit stream, produces inverse quantization result; Inverse transformation unit, performs inverse transformation to inverse quantization result, produces inverse transformation result; Motion compensating module, comprises time prediction unit and spatial prediction unit, performs motion compensation and produce the prediction associated to export according to incoming bit stream; Arithmetical unit, exports inverse transformation result with prediction and is added, and produces to compensate to export; Reconstruction frames output unit, exports according to compensation and produces reconstruction frames; And frame memory, temporarily store reconstruction frames at least partially; Wherein, time prediction unit according to the resolution operation of reconstruction frames, with reduce running time prediction complexity.Above-mentioned Video Decoder is not the resolution executable operations of primitive frame according to being represented by incoming bit stream, but according to the resolution executable operations of reconstruction frames, can reduce the complexity of operation.But above-mentioned Video Decoder also can only be decoded to a kind of code stream of form, can not decode respectively or simultaneously to different-format code stream simultaneously.
Chinese patent ZL 200910162213.3 discloses a kind of Video Decoder, comprises ADC, main processing path, sample rate converter, filter, buffer, output sample rate converter and parallel-to-serial transducer.ADC operates with the first sampling rate, by analog video signal digitlization to obtain multiple sample.Main processing path is collected odd samples and is exported and synchronizing information to provide the first decoded video.Even samples is converted to the first conversion sample in the first preset frequency with the second sampling rate by sample rate converter.Filter, by the first conversion sample filtering, to obtain the second Y-signal.Buffer is for storing the second Y-signal.Export sample rate converter, in the second preset frequency, buffer output is converted to the second conversion sample.Parallel-to-serial converter accepts first decoded video exports changes sample with second, exports to drive the second decoded video.Above-mentioned Video Decoder can improve the sharpness of vision signal.But this Video Decoder equally also can only be decoded to a kind of code stream of form, can not decode respectively or simultaneously to different-format code stream simultaneously.
Utility model content
The utility model object is, overcome defect of the prior art, there is provided one can improve digital video decoder to ordinary numbers Video Decoder, stream format information is obtained by resolving video flowing, increase Decode engine to carry out adaptive decoding, comprising SVAC, H.264 and MPEG-4 form; Increase by two kinds of video output interfaces, and switchable multiple converting interface, to access command centre's video wall of different interface type; By optimizing decoding arithmetic element, making real-time decoding export way and can reach 8 road 1080P.
For achieving the above object, the technical solution of the utility model is: provide a kind of digital video signal decoder, described video signal decoder comprises server master board, be arranged on the CPU on mainboard, memory, network interface and video signal output interface, memory is provided with SVAC decoding unit, H.264 decoding unit, MPEG-4 decoding unit and self-adaption of decoding switch unit.
Preferred technical scheme is, described video signal output interface port comprises 8 road bnc interfaces and 8 road DP interfaces.
Preferred technical scheme also has, the model of described CPU is:: Intel to strong E5-1650V2, the model of described mainboard is: ultra micro X9SRA, the model of described memory is: West Digital WD30PURX3T, and to be its model of network card chip be described network interface: One (1) Inte182579LmandOne (1) nte182574LGbLAN.
Preferred technical scheme also has, and described server master board is arranged in housing.
Advantage of the present utility model and beneficial effect are that this digital video signal decoder changes the working method that ordinary numbers Video Decoder can only support one to two kinds of form decoding computings simultaneously.Embedded in three the decoding arithmetic elements corresponding respectively to SVAC, MPEG-4, H.264 algorithm in decoder inside of the present utility model, these three arithmetic elements can simultaneously load operating, decoding digital video module identifies its Coding Compression Algorithm adopted automatically by analysis code stream format content, and is the decoding arithmetic element that code stream selection one is correct.When the code stream change of format of decoder input, the selection of decoding arithmetic element also can change thereupon, in this way, reaches the object of multi-format multiresolution code stream real-time adaptive decoding.
Change the way of output that ordinary numbers Video Decoder can only have a kind of output interface.Add two kinds of decoding output units in decoder inside of the present utility model, BNC and Display (DP) interface, and turn HDMI/DVI/SDI interface by DP, the video wall of different interface type can be accessed.
Different stage, interconnecting of different framework video surveillance network become the development trend of city monitoring alarm networking system.The utility model is that video surveillance network provides the higher decoding scheme of a kind of performance and equipment.Can greatly reduce different coding Format network interconnected time transformation, reconstructed cost.
Such as: A, B, C tri-monitor networks adopt respectively SVAC, H.264, MPEG-4 video compression coding form, and respectively have 100/road high-definition monitoring encoding device.When A, B, C network interconnection, because ordinary numbers Video Decoder can only support that a kind of video format is decoded simultaneously, and it is limited to export way, this just needs in three networks, increase the decoder supporting the other side's video format, and corresponding decoder must be selected by code stream form, this way had both added the cost (increase by 6 decoders by each network to calculate, estimate to increase equipment cost 60000-180000 unit) of equipment investment, again limit the flexibility that code stream uses alternately.When networked system is more, also can be more complicated to the application configuration of equipment.Sometimes, in order to ensure the flexibility of networking between system and reliability, even need to upgrade encoding device, the expense that this equipment purchase and engineering drop into is larger, for 100/road monitoring encoding device, estimate that the total input renovated will reach hundreds of thousands to unit up to a million.
In addition, if Surveillance center's video wall interface is inconsistent with ordinary numbers Video Decoder interface, then or cannot use, or need to change video wall.
Decoding scheme of the present utility model and equipment only need the equipment cost of increase about 1000 yuan relative to the every platform of ordinary numbers Video Decoder, just can solve the problem completely.In actual applications, be the scheme that a kind of cost performance is very high and equipment.
Accompanying drawing explanation
Fig. 1 is the circuit block diagram of the utility model digital video signal decoder;
Fig. 2 is the example block diagram with the dual output interface of multi-format adaptive decoding of the utility model digital video signal decoder.
In figure: 1-server master board, 2-CPU, 3-memory, 3.1-SVAC decoding unit, 3.2-H.26 decoding unit, 3.3-MPEG-4 decoding unit, 3.4-self-adaption of decoding switch unit, 4-network interface, 5-BNC interface, 6-DP interface.
Embodiment
As shown in Figure 1, 2, a kind of digital video signal decoder of the utility model, described video signal decoder comprises server master board 1, be arranged on the CPU2 on mainboard, memory 3, network interface 4 and video signal output interface, memory is provided with SVAC decoding unit 3.1, H.26 decoding unit 3.2, MPEG-4 decoding unit 3.3 and self-adaption of decoding switch unit 3.4.
The preferred embodiment of the utility model is, described video signal output interface port comprises 4 road bnc interface 5 and 8 road DP interfaces 6.
The preferred embodiment of the utility model also has, the model of described CPU2 is:: Intel to strong E5-1650V2, the model of described mainboard is: ultra micro X9SRA, the model of described memory is: West Digital WD30PURX3T, and to be its model of network card chip be described network interface: One (1) Inte182579LmandOne (1) nte182574LGbLAN.
The preferred embodiment of the utility model also has, and described server master board 1 is arranged in housing.
Embodiment
In the utility model digital video signal decoder, server master board 1 comprises memory 3 (hard disk, internal memory), power supply etc.; Network interface 4; CPU2; 8 road BNC card interfaces 5; 8 road DP video card interface 6 and converting interfaces thereof.After server master board 1 powers on, operating system brings into operation; Application program and 3.1-SVAC decoding unit, 3.2-H.264 decoding unit, 3.3-MPEG-4 decoding unit, 3.4-self-adaption of decoding switch unit runs in CPU2; CPU2 receives Internet video encoding stream, and the application program in CPU2 is by judging that video stream format is called corresponding decoding arithmetic element and decoded; Decoded video flowing carries out output display by BNC card interface 5 or DP interface 6.
The performance index using the digital video decoder with the dual output interface of multi-format adaptive decoding of this programme to have are:
● video decoding standards: SVAC, H.264, MPEG-4;
● video decode resolution: 1080P, 720P, D1, CIF;
● single channel real-time decoding code check and frame per second: 12Mbps@30FPS;
● decoding performance: 8 road 1080P;
● codec format switching mode: real-time adaptive;
● decoding output display form: BNC, DP and converting interface thereof;
The utility model is not limited to above-mentioned execution mode, those skilled in the art make to any apparent improvement of above-mentioned execution mode or change, all can not exceed the protection range of design of the present utility model and claims.
Claims (4)
1. a digital video signal decoder, it is characterized in that, described video signal decoder comprises server master board, be arranged on the CPU on mainboard, memory, network interface and video signal output interface, memory is provided with SVAC decoding unit, H.264 decoding unit, MPEG-4 decoding unit and self-adaption of decoding switch unit.
2. digital video signal decoder as claimed in claim 1, it is characterized in that, described video signal output interface port comprises 8 road bnc interfaces and 8 road DP interfaces.
3. digital video signal decoder as claimed in claim 1, it is characterized in that, the model of described CPU is: Intel to strong E5-1650V2, the model of described mainboard is: ultra micro X9SRA, and the model of described memory is: West Digital WD30PURX3T.
4. digital video signal decoder as claimed in claim 1, it is characterized in that, described server master board is arranged in housing.
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| CN201420617605.0U CN204131646U (en) | 2014-10-23 | 2014-10-23 | A kind of digital video signal decoder |
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| CN201420617605.0U CN204131646U (en) | 2014-10-23 | 2014-10-23 | A kind of digital video signal decoder |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105592316A (en) * | 2014-10-23 | 2016-05-18 | 公安部第一研究所 | Digital video signal decoder |
| CN108989740A (en) * | 2018-08-06 | 2018-12-11 | 北京数码视讯科技股份有限公司 | A kind of video conferencing system and method |
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2014
- 2014-10-23 CN CN201420617605.0U patent/CN204131646U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105592316A (en) * | 2014-10-23 | 2016-05-18 | 公安部第一研究所 | Digital video signal decoder |
| CN108989740A (en) * | 2018-08-06 | 2018-12-11 | 北京数码视讯科技股份有限公司 | A kind of video conferencing system and method |
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