CN1889667A - Video frequency signal multi-processor parallel processing method - Google Patents
Video frequency signal multi-processor parallel processing method Download PDFInfo
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Abstract
A multiple processor parallel-processing method of video signal includes using sub block processor to carry out zonal parallel processing on complete frame of image and utilizing each sub block processor to process one zone of video image, enabling to carry out communication between those processors through video I/O interface and carrying out communication with sub block processor by synthetic processor through communication interface for realizing integration of processing results from each sub block processor.
Description
Technical field
The present invention relates to a kind of parallel video signal processing method, especially the Code And Decode processing method of high resolution digital video signal.
Background technology
The data volume of digital video signal is very big, and particularly the real-time processing of high definition video signal needs googol according to disposal ability.
DSP (digital signal processor) at present commonly used carries out vision signal to be handled, the special-purpose DSP that has been the video and audio signal Treatment Design especially, these processors have special-purpose video and voice data input/output interface, the certain video that also has that has is assisted disposal ability, as data format conversion, VLC (variable-length encoding), VLD (variable length decoding) and OSD (the screen stack shows) etc., can carry out the digital video-audio Signal Processing easily, as compressed encoding and decoding etc., such processor is referred to as multimedia processor or Media Processor.
Programmable logic device (PLD, as FPGA and CPLD), because of having powerful parallel processing capability, being highly suitable for vision signal handles, programmable logic device is extending video input and output interface also, and the also embedded MCU or the MPU that have can be advantageously used in vision signal and handle, become multimedia and handle special-purpose programmable logic device, the present invention also is classified as multimedia processor with it.
Yet the disposal ability of multimedia processor is limited, and people are more and more higher to the requirement of vision signal resolution, and the disposal ability Chang Buneng of single processor satisfies the requirement of handling high definition video signal.Such as, at present the monolithic multimedia processor can't realize the 1080i form high definition video signal H.264, the real-time video compressed encoding of standards such as AVS or MPEG4, more can not handle more high-resolution vision signals such as 4 mega pixels.A solution is the processing of adopting multi-disc processor Parallel Implementation high definition video signal, but because Video processing often needs signal feedback, this just needs to realize high-speed data communication between each processor of parallel processing, method commonly used is to adopt to increase dual port RAM or the mutual high-speed data communication of FIFO realization, but this method realizes complicated, development difficulty is big, and the cost of dual port RAM and FIFO is higher, thereby practicality is relatively poor.The multiprocessors parallel processing mode that adopts the differential high speed serial interface to realize inter-processor communication is also arranged at present, but the processor of this class band differential high speed serial interface is high-end processor at present, cost is higher.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of multi-processor parallel processing method of vision signal, utilize this method can realize the parallel processing of a plurality of multimedia processors more conveniently, thereby reduce the complexity of multiprocessors parallel processing, solve the disposal ability bottleneck problem that high definition video signal is handled.
For achieving the above object, the technical solution used in the present invention is such:
Adopt a plurality of sub-piece processors with video input and video output interface, this sub-piece processor is a multimedia processor, can be DSP with one or more video input and output interfaces (can be configured to have 4 video input interfaces and 2 working methods such as video output interface as the TMS320DM642 processor of TI company), also can be the programming device with video input and output interface.Described sub-piece processor constitutes a parallel video treatment system, and the video image of input is divided into a plurality of sub-pieces (subregion), and each sub-piece is handled with a processor.
In order to realize that each sub-piece processor processing result's fusion also is provided with a synthesis processor in the system that the present invention constituted, this synthesis processor can be a multimedia processor or a MPU (microprocessor is as ARM, MIPS).For example, this system is used for high-resolution video when coding, and the output result of each sub-piece processor all is passed to this synthesis processor, finishes the synthetic and multiple connection of data etc. by synthesis processor, forms a complete data flow.Synthesis processor can be born simultaneously other task of application system, and as audio interface and encoding and decoding, multiple connection is conciliate in the video flowing multiple connection, also the video data of separating after the multiple connection can be distributed to each sub-piece processor by bi-directional data interface (as Ethernet, HPI, EMIF).
If synthesis processor adopts a slice multimedia processor to realize, then it can receive the raster video data from each processor output, is fused to the high-resolution gration video data in synthesis processor, and by its video output output.It is that high definition video decoding and multi-channel video are pieced together screen that the typical case of such system uses.
The video image of Chu Liing is big or algorithm is complicated if desired, then needs video is divided into more sub-piece, promptly needs more sub-piece processor parallel processing, and at this moment available a plurality of processors are formed the synthesis processor groups.For example, adopt the multi-disc multimedia processor to constitute the synthesis processor group, every synthesis processor receives the raster video signal of wherein a few way piece processor outputs, the output signal of each synthesis processor is imported another synthesis processor, synthesize high definition video signal at last, again by its video output output.
Because the input of row, (or frame) control of video signal can be adopted in the video input port of multimedia processor, be input to the data volume of multimedia processor for minimizing, as to given processor, the sub-blocks of data of video that only needs branch to be tasked this processor is imported this processor, and parallel video treatment system of the present invention also can comprise some interface control circuits.Each video input port at corresponding each sub-piece processor, an interface control circuit all can be set, thereby a plurality of interface control circuits are arranged in the system that is constituted, be used to change row, field (or frame) control signal of vision signal, thereby control is input to the view data effective range of processor, promptly only with sub-piece of specific video or the corresponding sub-piece processor of zone input.Described interface control circuit can be realized with programming device such as one or more pieces CPLD, FPGA or other logical circuit.Row, (or frame) control signal can be row, (or frame) useful signal or synchronizing signal, can use signal wire transmits, or adopt special code to be embedded in the video data.
Utilize the video interface of multimedia processor also can realize high-speed data communication between a plurality of processors.The present invention adopts multimedia processor video output outputting video signal and other signal, and another multimedia processor adopts the video input port to receive this signal, thereby realizes the transfer of data between multimedia processor.Because used multimedia processor has a plurality of video inputs and video output interface, just can realize large-scale parallel video processing in this way.In order only to import the data that need, adopt the effective range of interface control circuit control of video data input equally.
Among the present invention because the video input and output port limited amount of multimedia processor, for the ease of realizing the MPP of vision signal, the division of the sub-piece of video should make the quantity of the adjacent sub-blocks of each sub-piece be no more than the video inputs mouth quantity of multimedia processor, as video image can being divided into the sub-piece of horizontal or vertical strip, or the video image matrix pattern is divided into four sub-pieces.
Description of drawings
Fig. 1 is the schematic diagram that the sub-piece of several video images is divided.
Fig. 2 is that the sub-piece of corresponding diagram 1 (a) is divided an embodiment who realizes parallel processing.
Fig. 3 be corresponding diagram 1 (b) or (c) sub-piece divide an embodiment who realizes parallel processing.
Fig. 4 adopts Fig. 3 example structure mode to carry out the embodiment that video code conversion is handled.
Fig. 5 is similar with Fig. 4, adopts two video code conversion Processing Examples that processor is decoded.
Embodiment
To high-resolution video data, each frame has bigger size, HDTV video data as 1920 * 1080 resolution, every two field picture can be divided into shown in Fig. 1 (a) 4, every block size is 960 * 540, also video image can be divided into shown in Fig. 1 (b) 4, and every block size is 480 * 1080, also video image can be divided into shown in Fig. 1 (c) 4, every block size is 1920 * 270.Can handle wherein one respectively with 4 multimedia processors like this, the data behind every video image compression coding send synthesis processor to synthesize complete vision signal.For resolution bigger vision signal or the higher algorithm of processing complexity, then can be divided into more sub-piece in this way, shown in Fig. 1 (d).For the interlaced video signal as HDTV 1080i, then each sub-piece input multimedia processor is that Fen Erchang carries out.
Because the data after picture frame was handled before the inter-frame video treatment technology need utilize, need utilize the data reconstruction (reconstruction frames) of former frame image to carry out estimation as the inter-frame video coding, be the called reference frame, H.264 with video encoding standard such as AVS even need a plurality of reference frames.Other Video processing is also used former image frame data possibly.Problem is that reference frame image data or the intermediate treatment result data that the inter-frame video processing need be used is not limited in the piecemeal at place, also promptly needs the video data of adjacent piecemeal correspondence.When carrying out estimation, use surrounding image data, as using the reference frame data in the frame of broken lines among the figure to the estimation of macro block in the C piece among Fig. 1 (a) with the inter-frame video encryption algorithm.That is to say, adopting partitioned mode to carry out inter-frame video handles, if one of them piecemeal of each processor processing, then each processor all needs to use the reference frame image data from other processor, these data can be exported by video output interface by respective processor, and the video input port by current processor receives in the memory again.As Fig. 1 (a), if piecemeal A handles with processor 1, piecemeal B handles with processor 2, piecemeal C handles with processor 3, piecemeal D handles with processor 4, the video output data of processor 1, processor 2 and processor 4 need be input to processor 3, and processor 1, processor 2 and processor 4 can utilize its video output dateout, and three video input interfaces by processor 3 receive these video datas respectively.
For Fig. 1 (b), (c) and sub-piece division methods (d), as long as adjacent two data are used in the processing of each sub-piece at most.That is to say, handle as figure (b), (c) and (d) as shown in the processor of each sub-piece, need the video data of reception from the sub-piece processor of the adjacent two sub-pieces of this sub-piece of processing.The sub-piece processor that we claim to handle adjacent sub-blocks is adjacent processor.The benefit of this seed block division methods is, can be with the very big video sequence data of a lot of processor parallel processings.
Fig. 2 is an embodiment with said method, and the sub-piece of corresponding diagram 1 (a) is divided.This embodiment adopts the TMS320DM642 multimedia processor of TI, also can adopt other that multimedia processor of a plurality of video input/output interfaces is arranged.DM642 contains 3 video ports, and each video port can be used as 2 10 bit ports again and uses, if all as input, 6 video input ports can be arranged altogether then.
The vision signal of input can be can be by the video data of multimedia processor video port input from the vision signal of the video data of transducer (as CCD or cmos image sensor) or the output of other HD video equipment or other, and we are called outer video signal.By the interface control circuit control of corresponding each processor and row, a control signal of change vision signal, these signals can be row, (or frame) useful signal or synchronizing signal, thereby control is input to the view data effective range of sub-piece processor, promptly only the sub-piece of specific video is imported corresponding processor.And video data can directly be imported the video input port of multimedia processor or do certain time-delay for sequential coupling.
Each processor is with its processed video data, as the reconstruction frames in the coding and decoding video algorithm, intermediate object program or data in the video image analysis, export by video output, we are called internal video signal, same through interface control circuit, select the effective video data by row, field (or frame) control signal in control and the change vision signal, pass through the video input port input processor of processor again.
Because each processor need receive one road outer video signal and from three road internal video signals of corresponding three adjacent processors, promptly need to receive four road video datas altogether, this four road video data all needs to select valid data through interface control circuit, also promptly need four independently interface control circuits altogether, but realize in one or more pieces logical circuits of these interface control circuits.When adopting the multi-disc logical circuit to realize, because interface control circuit is for changing row, (or frame) control signal in the vision signal, the interface control circuit of corresponding same data source (outer video signal or internal video signal) can be combined, thereby simplifies circuit.Interface control circuit can be CLPD, FPGA or other logical circuit.
Each processor receives this four tunnel vision signal with four video input ports, exports one tunnel vision signal with a video output and gives adjacent processor.
Each exports one tunnel processed video signal to synthesis processor with a video interface in addition each processor, and synthesis processor receives this four tunnel vision signal with four video input ports.Synthetic processing also can be communicated by letter with each video processor by interfaces such as Ethernet, HPI, EMIF, thereby realization is to the control of each video processor, to each video processor distributing data stream.
Fig. 3 is another embodiment with said method, and corresponding diagram 1 (b) or sub-piece (c) are divided.Wherein processor 1, processor 2, processor 3, processor 4 are respectively applied for and handle the sub-piece A of video, the sub-piece B of video, the sub-piece C of video, the sub-piece D of video, processor 1 receives the vision signal of outer video signal and from processor 2, processor 2 receives the vision signal of outer video signal and from processor 1 and processor 3, processor 3 receives the vision signal of outer video signal and from processor 2 and processor 4, and processor 4 receives the vision signal of outer video signal and from processor 3.Control mode to vision signal is identical with Fig. 1 example.Especially, for the video coding and the decoding algorithm that H.264 have intra prediction mode with AVS etc., the Code And Decode of its inter-coded macroblocks all needs to use its left side and top neighbor, and the sub-piece shown in Fig. 1 (c) is divided and more can be adapted to real-time coding and decoding.
Fig. 4 is an embodiment who is used for video code conversion who utilizes method shown in Figure 3 to realize.This embodiment realizes video decode with a slice processor, as realize the MPEG2 video decode of HDTV resolution, decoded vision signal is delivered to each video processor, operation principle is identical with Fig. 3, different is decoding processor with in the code stream about the motion vector of macro block, message transmission such as quantization parameter are given synthesis processor, and pass through Ethernet by synthetic the processing, HPI, interfaces such as EMIF are transferred to processor 1, processor 2, processor 3, processor 4, also can directly these information be transferred to each video processor (as shown in phantom in Figure 4) by data/address bus by decoding processor, thereby the speed of estimation in the raising video coding algorithm, perhaps these information can be embedded in the video data, be used as video data and be transferred to each video processor, at this moment need original image is expanded by video interface.
For needs complex video when decoding more, as will realizing the H.264/AVC video decode of 1080i resolution, then available 2 or 4 multimedia processors are realized the parallel video decoding processing with said method.
Fig. 5 is an embodiment who realizes video code conversion with 6 multimedia processors and a slice synthesis processor.
Synthetic processor controls will need the source code flow of transcoding to be transferred to decoding processor 1 and decoding processor 2 by interfaces such as Ethernet, HPI, EMIF, and they all are multimedia processors.Owing to need in the decode procedure to obtain reference frame video data from adjacent processor (being another decoding processor) here, these two processors all are transferred to the other side by video output and input port with reconstruction frames.Decoding processor 1 is transferred to encode processor 1 and encode processor 2 with decoded video data by video port, and decoding processor 2 is transferred to encode processor 3 and encode processor 4 with decoded video data by video port.Simultaneously, decoding processor 1 and decoding processor 2 are transferred to each encode processor (can directly transmit or transmit by synthetic processor controls) with information such as motion vectors by interfaces such as Ethernet, HPI, EMIF.
Main feature of the present invention is to adopt the video port of multimedia processor to carry out transmitting between the processor of video data, thereby realizes the large-scale parallel Video processing.Can be used for but be not limited to the sub-piece of above-mentioned video dividing and embodiment.The inventive method also can be used for video data and merges, and as the multi-channel video splicing with merge, the inventive method can be used for various high-resolution videos to be handled, and cuts apart and understanding etc. as the high-resolution objects in video.
Claims (5)
1, a kind of video frequency signal multi-processor parallel processing method, adopt a plurality of sub-piece processors and synthesis processor to realize the parallel processing of vision signal, it is characterized in that: sub-piece processor carries out the subregion parallel processing to entire image, a zone of each sub-piece processor processing video image can communicate by video input and output interface between these processors; Synthesis processor is realized the fusion to each sub-piece processor processing result by communication interface and sub-piece processor communication.
2, video frequency signal multi-processor parallel processing method according to claim 1, it is characterized in that: in the video input port of sub-piece processor, one interface control circuit can be set, in order to row, a control signal that changes vision signal, control is input to the view data effective range of sub-piece processor, wherein row, a control signal can adopt independently control line, also can be embedded in the video data.
3, video frequency signal multi-processor parallel processing method according to claim 1 and 2, it is characterized in that: the video output interface of sub-piece processor can be connected with the video input interface of other one or more sub-piece processors, in order to realize the data communication between processor.
4, according to claim 1 or 2 or 3 described video frequency signal multi-processor parallel processing methods, it is characterized in that: can realize the video code conversion processing, video decode is handled decoded video data is input to sub-piece processor by video interface, simultaneously with parameters such as former operation vector, quantifications by communication interface or be embedded in the video data, be transferred to each sub-piece processor.
5, video frequency signal multi-processor parallel processing method according to claim 4, it is characterized in that: adopt a plurality of decoding processors to realize video decode, adopt video interface to carry out video Data Transmission between decoding processor, decoded video data is transferred to corresponding sub-piece processor by video interface and control circuit.
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