CN111064937A - Video optical fiber seat receiving device - Google Patents
Video optical fiber seat receiving device Download PDFInfo
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- CN111064937A CN111064937A CN201911342447.6A CN201911342447A CN111064937A CN 111064937 A CN111064937 A CN 111064937A CN 201911342447 A CN201911342447 A CN 201911342447A CN 111064937 A CN111064937 A CN 111064937A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/22—Adaptations for optical transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
The invention relates to a video optical fiber seat receiving device, which comprises a redundant optical module receiving circuit, a main FPGA signal processing circuit and a video optical fiber seat receiving circuit, wherein the redundant optical module receiving circuit is connected with the main FPGA signal processing circuit and is used for converting a received serial video optical signal into a serial video electrical signal and inputting the serial video electrical signal into the main FPGA signal processing circuit; the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits; the sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the processed video electric signal and transmitting the processed video electric signal to the output coding circuit; the output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished; and the output interface circuit is used for outputting the complete video electric signal. The invention optimizes signal processing, reduces system delay, simplifies system design and enhances reliability.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array) based processing, in particular to a video optical fiber seat receiving device.
Background
In the current video receiving device of the optical fiber seat, in the prior art, a processing process of an optical fiber access network video signal stream is to access an ethernet network through a switch chip, then use a proprietary decoding chip or FPGA to decode and restore the received video signal, transmit the video signal to a video transmitting interface chip in a specific format, and drive the video signal to a display unit through the interface chip to complete a receiving process of the optical fiber video signal stream.
In prior art systems, the video stream is transmitted based on a network protocol, and the video stream is decoded and restored in a video decoder and the main video signal processing is completed. Because multi-frame images need to be cached in the decoding process, different degrees of time delay exist between the video signal source and the output real-time video, and because the processing process of the video signal is highly concentrated at a special decoding chip, the requirement on the chip is high, the requirement on the heat dissipation condition is high, and the reliability of the system is reduced.
Disclosure of Invention
The present invention is directed to overcoming at least one of the above-mentioned deficiencies in the prior art and providing a video fiber-optic seat receiver for optimizing signal processing of the original video, reducing system latency, simplifying system design and enhancing reliability of system operation.
The technical scheme adopted by the invention is that,
a video optical fiber seat receiving device comprises a redundant optical module receiving circuit, an FPGA signal processing circuit group, an output coding circuit and an output interface circuit, wherein the FPGA signal processing circuit group comprises a main FPGA signal processing circuit and at least two sub FPGA signal processing circuits;
the redundant optical module receiving circuit is connected with the main FPGA signal processing circuit and used for converting the received serial video optical signals into serial video electrical signals and inputting the serial video electrical signals into the main FPGA signal processing circuit;
the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits;
the sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the video electric signal processed by the main FPGA signal processing circuit and transmitting the video electric signal to the output coding circuit;
the output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished; and the output interface circuit is used for outputting the complete video electric signal synthesized by the output coding circuit.
The video optical fiber receiving device is integrated by a redundant optical module receiving circuit, a main FPGA signal processing circuit, at least two sub FPGA signal processing circuits, an output coding circuit and an output interface circuit to realize the functions of reducing system delay and optimizing signal processing. The redundant optical module receiving circuit is used for receiving real-time serial video optical signals, converting the serial video optical signals into serial video electrical signals, inputting the converted serial video electrical signals into the main FPGA signal processing circuit, deserializing the serial video electrical signals through the main FPGA signal processing circuit to reduce the clock frequency of the video electrical signals and complete a main signal processing process, the processed video electrical signals are respectively transmitted to at least two sub FPGA signal processing circuits, specific time sequence conversion is carried out on the video electrical signals processed by the main FPGA signal processing circuit in the sub FPGA signal processing circuits, finally a plurality of video electrical signals after the time sequence conversion is completed in the output coding circuit are synthesized, and the synthesized complete video electrical signals are output through the output interface circuit. According to the invention, from receiving the real-time serial video optical signal to outputting the complete video electrical signal after signal processing, the signal processing completed in the process of the original video is greatly optimized, and the buffered image is reduced, so that the device delay is optimized; in the process of processing the video signal, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; video signals of the device are directly input into the FPGA signal processing circuit for processing after photoelectric conversion, and Ethernet protocol conversion is not needed, so that system design is simplified; and the maximum resolution supported by the device can reach 4k ultrahigh definition resolution. In addition, the device adopts a plurality of FPGA signal processing circuits to respectively complete different signal processing, reduces the requirement of the integration level of the main FPGA, enables the FPGA to be more flexible in combination and type selection, reduces the power consumption of the main FPGA and enhances the running reliability of the device.
A control method of a video fiber agent receiving device, the control method comprising the steps of:
s1, receiving a serial video optical signal and converting the serial video optical signal into a serial video electrical signal;
s2, deserializing the serial video electrical signal, reducing the clock frequency of the deserialized video electrical signal, and shunting the processed video electrical signal into at least two sub video electrical signals;
s3, respectively carrying out time sequence conversion processing on the at least two sub video electric signals;
s4, synthesizing at least two sub-video electric signals subjected to time sequence conversion into a complete video electric signal and carrying out coding processing;
and S5, outputting the coded complete video electric signal.
The invention discloses a control method of a video optical fiber receiving device, which comprises the following steps: firstly, controlling a video optical fiber receiving device to receive a real-time serial video optical signal and converting the real-time serial video optical signal into a serial video electrical signal; secondly, deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal, completing a main signal processing process to obtain a processed video electrical signal, and dividing the processed video electrical signal into at least two sub-video electrical signals according to the division condition of a display screen displayed corresponding to the video signal; then, carrying out specific time sequence conversion on at least two sub-video electric signals, synthesizing into a complete video electric signal, and carrying out coding processing on the complete video electric signal; and finally outputting the integrated video electric signal after the synthesis and coding. The control method of the invention greatly optimizes the signal processing completed by the original video in the process from receiving the real-time serial video optical signal to outputting the complete video electric signal, reduces the buffered image and optimizes the delay problem; in the process of processing the video signal, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; and the control method of the device enables the maximum resolution supported by the device to reach 4k ultra-high definition resolution. In addition, the method reduces the power consumption of main signal processing by shunting a plurality of sub-video electric signals, so that the running reliability of the system is enhanced.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a video optical fiber receiving device and a control method, from receiving a real-time serial video optical signal to outputting a complete video electrical signal after signal processing, the signal processing completed in the whole process of an original video is greatly optimized, buffered images are reduced, and the delay of the device is reduced; in the process of processing the video signal, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; video signals of the device are directly input into the FPGA signal processing circuit for processing after photoelectric conversion, and Ethernet protocol conversion is not needed, so that system design is simplified; and the maximum resolution supported by the device can reach 4k ultrahigh definition resolution. In addition, the device adopts a plurality of FPGA signal processing circuits to respectively complete different signal processing, reduces the signal processing pressure of the main FPGA compared with the situation that the whole function is completed by a single FPGA, reduces the integration requirement of the main FPGA, enables the FPGA to be more flexibly combined and selected, reduces the power consumption of the main FPGA, and enhances the running reliability of the device.
Drawings
Fig. 1 is a schematic structural connection diagram according to an embodiment of the present invention.
Fig. 2 is a structural diagram of a plurality of FPGA signal processing circuits in the embodiment of the present invention.
Fig. 3 is a block diagram of the entire apparatus according to the embodiment of the present invention.
Fig. 4 is a flowchart of a control method according to an embodiment of the invention.
Detailed Description
The drawings are only for purposes of illustration and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
Example 1
As shown in fig. 1, fig. 1 is a schematic diagram of a structural connection of a video fiber seat receiving device according to an embodiment of the present invention, where the video fiber seat receiving device may include a redundant optical module receiving circuit, an FPGA signal processing circuit group, an output encoding circuit, and an output interface circuit, where the FPGA signal processing circuit group includes a main FPGA signal processing circuit and at least two sub FPGA signal processing circuits;
the redundant optical module receiving circuit is connected with the main FPGA signal processing circuit and used for converting a received serial video optical signal into a serial video electrical signal and inputting the serial video electrical signal to the main FPGA signal processing circuit, and specifically, the redundant optical module receiving circuit is connected with an optical fiber and receives the serial video optical signal transmitted from the optical fiber;
the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits;
in the embodiment of the invention, the high-speed serial video electrical signal input by the receiving circuit of the redundant optical module completes main signal processing processes such as deserializing and OSD superposition of the signal at the main FPGA signal processing circuit, the clock frequency of the video electrical signal is reduced, and then the video signal after the main signal processing is completed is transmitted to at least two sub FPGA signal processing circuits according to the actual screen splitting condition.
The sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the video electric signal processed by the main FPGA signal processing circuit and transmitting the video electric signal to the output coding circuit;
preferably, the embodiment of the present invention at least includes two sub-FPGA signal processing circuits, and the number of the sub-FPGA signal processing circuits is determined by the following method:
dividing a display screen displayed correspondingly to the video signal into at least two screen division areas, and correspondingly determining the number of the FPGA signal processing circuits according to the number of the screen division areas.
Preferably, the display screen is divided into an upper split screen area and a lower split screen area or a left split screen area and a right split screen area, the plurality of split FPGA signal processing circuits are provided with two split FPGA signal processing circuits corresponding to the two split screen areas, the two split FPGA signal processing circuits respectively complete video signal time sequence conversion of the two split screen areas and then transmit the video signal time sequence conversion to the output encoding circuit, specifically, the two split screen areas can be divided into the upper split screen area and the lower split screen area or the two split screen areas in the left split screen area and the right split screen area according to the split screen areas, and the embodiment only proposes the case.
Specifically, as shown in fig. 2, the display screen is divided into a left split-screen area and a right split-screen area, after the main FPGA signal processing circuit completes signal processing of the high-speed serial electrical signal, the left split-screen video signal and the right split-screen video signal are divided into a left split-screen video signal and a right split-screen video signal according to the split-screen area and input to the two split-screen FPGA signal processing circuits, the left split-screen signal processing circuit and the right split-screen signal processing circuit respectively receive the left half-image video signal and the right half-image video signal, complete a signal timing sequence conversion processing process.
The output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished;
in the embodiment of the invention, the output coding circuit adopts an HDMI output coding circuit, and the HDMI output coding circuit comprises an HDMI coding and equalizing chip and is used for realizing the coding function of the serial video electric signals. For a plurality of video signals after the two sub FPGA signal processing circuits complete the time sequence conversion processing of the video electric signals, the HDMI output coding circuit codes the video electric signals and synthesizes a complete image signal and then transmits the complete image signal to the output interface circuit.
And the output interface circuit is used for outputting the complete video electric signal synthesized by the output coding circuit.
In the embodiment of the invention, the output interface circuit adopts an HDMI output interface circuit, the HDMI (high definition multimedia interface) is a digital video/audio interface technology, is a special digital interface suitable for image transmission, has the highest data transmission speed of 2.25GB/s, and does not need line/analog or analog/digital conversion before signal transmission. The embodiment of the invention adopts the HDMI interface, has high signal transmission speed and low video signal quality loss, and can provide the best video quality.
Preferably, the embodiment of the present invention further includes a control circuit, which is connected to the main FPGA signal processing circuit, and is configured to control transceiving and scheduling of the video signal.
As shown in fig. 3, fig. 3 is a block diagram of the whole apparatus according to the embodiment of the present invention. The control circuit comprises an MPU main controller and a peripheral circuit connected with the MPU main controller, and the MPU main controller is connected with the main FPGA signal processing circuit.
The MPU is used as a main controller of the control circuit, and has the functions of controlling the transceiving and dispatching of video signals and controlling the processing process of the FPGA signal processing circuit in the device on the video signals. And the peripheral circuit connected with the MPU main controller is controlled by the MPU main controller and is used for completing a series of seat functions.
Preferably, in the embodiment of the present invention, the peripheral circuit includes a USB interface circuit and a USB HUB interface circuit, where the USB interface circuit is configured to import an external existing video data signal;
and the USB HUB interface circuit is used for accessing keyboard and mouse information and finishing the interaction between the optical fiber seats.
Specifically, the embodiment of the invention comprises a USB interface circuit and two USB HUB interface circuits, wherein the USB interface circuit can import a USB disk data signal, so that the device can read not only a real-time video source but also an existing video file, wherein a specific signal processing process of the existing video signal is the same as a real-time video signal processing process, the signal processing process is completed through an FPGA signal processing circuit, and finally, a complete video signal is output through an HDMI output encoding circuit and an HDMI output interface circuit. The two USB HUB interface circuits are used for accessing keyboard and mouse information and finishing interaction between the optical fiber seats through the keyboard and mouse information.
The peripheral circuit in the embodiment of the invention can also comprise a storage chip set circuit, an Ethernet interface circuit, an RS232 debugging circuit, an LCD control circuit and an audio receiving and looping-out circuit, wherein a developer can simply debug the running state of the serial port real-time observation device through the RS232 debugging circuit or debug the device circuit through the Ethernet interface circuit in real time; the LCD control circuit is adopted to directly output the configuration information of the display device, so that the running state of the device can be observed conveniently in real time; and the audio receiving and loop-out circuit is used for accessing audio signals to the video signal processing based on the embodiment, processing the audio signals and realizing the effect of outputting complete images by combining video and audio.
According to the video optical fiber receiving device provided by the embodiment of the invention, from the time of receiving the real-time serial video optical signal to the time of outputting the complete video electrical signal after signal processing, the signal processing of the original video is greatly optimized in the whole process, and the actual situation is optimized in terms of signal delay from tens of milliseconds to several seconds, so that buffered images are reduced, and the delay of the device is reduced; in the process of processing the video signal, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; video signals of the device are directly input into the FPGA signal processing circuit for processing after photoelectric conversion, and Ethernet protocol conversion is not needed, so that system design is simplified; and the maximum resolution supported by the device can reach 4k ultrahigh definition resolution. In addition, the device adopts a plurality of FPGA signal processing circuits to respectively complete different signal processing, reduces the signal processing pressure of the main FPGA compared with the situation that the whole function is completed by a single FPGA, reduces the integration requirement of the main FPGA, enables the FPGA to be more flexibly combined and selected, reduces the power consumption of the main FPGA, and enhances the running reliability of the device.
Example 2
As shown in fig. 4, fig. 4 is a step diagram of a control method of a video fiber agent receiving device, where the control method includes the following steps:
s1, receiving a serial video optical signal and converting the serial video optical signal into a serial video electrical signal;
s2, deserializing the serial video electrical signal, reducing the clock frequency of the deserialized video electrical signal, and shunting the processed video electrical signal into at least two sub video electrical signals;
s3, respectively carrying out time sequence conversion processing on the at least two sub video electric signals;
s4, synthesizing at least two sub-video electric signals subjected to time sequence conversion into a complete video electric signal and carrying out coding processing;
and S5, outputting the coded complete video electric signal.
Preferably, in step S2 in this embodiment of the present invention, the number of sub video signals is determined as follows:
the display screen corresponding to the video signal is divided into an upper split screen area, a lower split screen area, a left split screen area and a right split screen area, and the video signal is divided into two split video signals corresponding to the upper split screen area, the lower split screen area, the left split screen area and the right split screen area.
Preferably, in step S2 in this embodiment of the present invention, the processed video electrical signal is divided into at least two sub video electrical signals.
The control method of the invention greatly optimizes the signal processing completed by the original video in the process from receiving the real-time serial video optical signal to outputting the complete video electric signal, reduces the buffered image and optimizes the delay problem; in the process of processing the video signal, the image quality of the original video signal is highly reserved, and the image quality reduction caused by different video coding is reduced; and the control method of the device enables the maximum resolution supported by the device to reach 4k ultra-high definition resolution. In addition, the method reduces the power consumption of main signal processing by shunting a plurality of sub-video electric signals, so that the running reliability of the system is enhanced.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention claims should be included in the protection scope of the present invention claims.
Claims (10)
1. A video optical fiber seat receiving device is characterized by comprising a redundant optical module receiving circuit, an FPGA signal processing circuit group, an output coding circuit and an output interface circuit, wherein the FPGA signal processing circuit group comprises a main FPGA signal processing circuit and at least two sub FPGA signal processing circuits;
the redundant optical module receiving circuit is connected with the main FPGA signal processing circuit and used for converting the received serial video optical signals into serial video electrical signals and inputting the serial video electrical signals into the main FPGA signal processing circuit;
the main FPGA signal processing circuit is connected with the at least two sub FPGA signal processing circuits and is used for deserializing the serial video electrical signal, reducing the clock frequency of the video electrical signal and respectively transmitting the processed video electrical signal to the at least two sub FPGA signal processing circuits;
the sub FPGA signal processing circuit is connected with the output coding circuit and is used for completing time sequence conversion on the video electric signal processed by the main FPGA signal processing circuit and transmitting the video electric signal to the output coding circuit;
the output coding circuit is connected with the output interface circuit and is used for synthesizing the plurality of video electric signals after the time sequence conversion is finished;
and the output interface circuit is used for outputting the complete video electric signal synthesized by the output coding circuit.
2. The video fiber agent receiving device according to claim 1, wherein the number of the sub-FPGA signal processing circuits is determined by: dividing a display screen displayed correspondingly to the video signal into at least two screen division areas, and correspondingly determining the number of the FPGA signal processing circuits according to the number of the screen division areas.
3. The video fiber optic seat receiving device according to claim 2, wherein the display screen is divided into two split screen areas, an upper split screen area, a lower split screen area, a left split screen area, a right split screen area, and a plurality of the split FPGA signal processing circuits comprises two split FPGA signal processing circuits corresponding to the two split screen areas,
and the two sub FPGA signal processing circuits respectively complete the time sequence conversion of the video signals of the two sub screen areas and then transmit the video signals to the output coding circuit.
4. The video fiber agent reception device according to claim 1, further comprising a control circuit connected to the main FPGA signal processing circuit for controlling transceiving and scheduling of the video electrical signal.
5. The video fiber agent reception device according to claim 4, wherein the control circuit comprises an MPU master controller and a peripheral circuit connected to the MPU master controller, and the MPU master controller is connected to the main FPGA signal processing circuit.
6. The video fiber optic agent receiving device of claim 5, wherein said peripheral circuitry comprises USB interface circuitry and USB HUB interface circuitry,
the USB interface circuit is used for importing an external existing video data signal;
and the USB HUB interface circuit is used for accessing keyboard and mouse information and finishing the interaction between the optical fiber seats.
7. The video fiber agent reception device according to claim 1, wherein the output encoding circuit is an HDMI output encoding circuit.
8. A control method of a video fiber agent receiving device is characterized by comprising the following steps:
s1, receiving a serial video optical signal and converting the serial video optical signal into a serial video electrical signal;
s2, deserializing the serial video electrical signal, reducing the clock frequency of the deserialized video electrical signal, and shunting the processed video electrical signal into at least two sub video electrical signals;
s3, respectively carrying out time sequence conversion processing on the at least two sub video electric signals;
s4, synthesizing at least two sub-video electric signals subjected to time sequence conversion into a complete video electric signal and carrying out coding processing;
and S5, outputting the coded complete video electric signal.
9. The method according to claim 8, wherein in step S2, the number of the sub video electrical signals is determined by:
the display screen corresponding to the video signal is divided into an upper split screen area, a lower split screen area, a left split screen area and a right split screen area, and the video signal is divided into two split video signals corresponding to the upper split screen area, the lower split screen area, the left split screen area and the right split screen area.
10. The method according to claim 8, wherein in step S2, the processed video signal is divided into two sub video signals.
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| CN201911342447.6A CN111064937A (en) | 2019-12-23 | 2019-12-23 | Video optical fiber seat receiving device |
| PCT/CN2020/141934 WO2021129887A1 (en) | 2019-12-23 | 2020-12-31 | Video optical fiber seat receiving device |
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| CN201911342447.6A CN111064937A (en) | 2019-12-23 | 2019-12-23 | Video optical fiber seat receiving device |
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| WO2021129887A1 (en) * | 2019-12-23 | 2021-07-01 | 威创集团股份有限公司 | Video optical fiber seat receiving device |
| CN114598592A (en) * | 2022-01-24 | 2022-06-07 | 浙江大华技术股份有限公司 | Seat cooperation system and method |
| WO2022141207A1 (en) * | 2020-12-28 | 2022-07-07 | 威创集团股份有限公司 | Video signal flow conversion apparatus and attendant collaboration system |
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| WO2021129887A1 (en) * | 2019-12-23 | 2021-07-01 | 威创集团股份有限公司 | Video optical fiber seat receiving device |
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| WO2022116352A1 (en) * | 2020-12-01 | 2022-06-09 | 威创集团股份有限公司 | 4k high-definition receiver box and video output system thereof |
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