CN114339045A - Image processing system and display device - Google Patents
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Abstract
The invention provides an image processing system and a display device, wherein the image processing system comprises: RISC-V microprocessor, sensing control chip, image processing chip and display control chip; the RISC-V microprocessor is used for controlling the sensing control chip to acquire image data; the sensing control chip is used for acquiring the image data under the control of the RISC-V microprocessor; the image processing chip is used for processing the image data acquired by the sensing control chip and transmitting the processed image data to the display control chip; and the display control chip is used for displaying the processed image data. The image processing system provided by the embodiment of the invention integrates the RISC-V microprocessor, the sensing control chip, the image processing chip and the display control chip, can realize extremely simple image transmission, not only saves the hardware cost, but also can reduce the time delay in the image data transmission process.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to an image processing system and a display device.
Background
The existing display screen has single function, and usually needs an application processor or a micro control unit for processing to realize the intelligent display function, so that the realization is complex, the power consumption is large, and the time delay is high; for scenes with strict delay requirements or scenes with single display requirements, the implementation mode has redundant functions and cannot meet the requirements. Most of the existing graph transmission systems use application processors, the hardware cost is high, the performances such as power consumption and time delay are not good, and the requirements of current intelligent vision products are not met.
Disclosure of Invention
The invention provides an image processing system and a display device, which solve the problems of high hardware cost, large power consumption and low time delay of the image processing system in the prior art.
In a first aspect of the present invention, there is provided an image processing system, comprising:
RISC-V microprocessor, sensing control chip, image processing chip and display control chip;
the RISC-V microprocessor is used for controlling the sensing control chip to collect image data and controlling the display control chip to display the processed image data, and the image data comprises a plurality of pixel data;
the sensing control chip is used for acquiring the image data under the control of the RISC-V microprocessor and transmitting the acquired image data to the image processing chip;
the image processing chip is used for processing the image data acquired by the sensing control chip and transmitting the processed image data to the display control chip;
and the display control chip is used for displaying the processed image data.
Optionally, the sensing control chip includes a local exposure module or a block exposure module;
the image is divided into a local area or a block area;
the local exposure module is used for exposing the image of the local area;
and the block exposure module is used for exposing the image of the block area.
Optionally, the display control chip specifically includes: the device comprises a pixel sorting module, an RAM palette, a gray scale voltage generation module and a panel formatting module;
the pixel sorting module is used for sorting the pixel data of the local area or the block area according to the horizontal and vertical coordinates of the local area or the block area to generate an index value of the pixel data;
the RAM palette is used for acquiring RGB color components of each pixel data according to the index value of the pixel data;
the gray scale voltage generation module is used for generating corresponding gray scale voltages according to the RGB color components of each pixel data;
and the panel formatting module is used for outputting the image data in an RGB (red, green and blue) arrangement mode according to the RGB arrangement mode set by the panel and formatting and outputting the image data.
Optionally, the display control chip further includes:
and the hardware cursor is used for displaying the cursor supported by the hardware in a manner of matching with the image.
Optionally, the image processing chip includes:
a pixel sampling module and a Mini ISP chip;
the pixel sampling module is used for receiving the image data;
and the Mini ISP chip is used for processing the image data in real time and outputting the image data after lens correction, dead pixel correction, denoising and format conversion.
Optionally, the image processing chip further comprises: the output module is used for receiving the image data processed by the Mini ISP chip;
the output module includes: the first output module, the second output module and the third output module;
the first output module is used for realizing the preview of image data, and the first output module comprises a 2D image scaler and a pixel formatter, wherein the 2D image scaler is used for realizing the scaling of an image, and the pixel formatter is used for realizing the cutting of the image;
the second output module is used for realizing direct display of the image data;
the third output module is configured to implement encoding and decoding of image data, and the third output module includes: the device comprises a coder and a decoder and a packing formatter, wherein the coder is used for coding and decoding image data, and the packing formatter is used for packing the image data.
Optionally, the image processing chip further includes:
and the core video arbitrator is used for merging the image data output by the first output module, the second output module and the third output module respectively.
Optionally, the image processing system further includes an extension module connected to the core video arbitrator, and configured to receive a user instruction or automatically detect an application scene in different application scenes, and then implement mode switching; and
the method is used for displaying a menu under different application scenes, and the menu at least comprises a mode switching option.
The embodiment of the invention has the following beneficial effects:
the image processing system provided by the embodiment of the invention integrates the RISC-V microprocessor, the sensing control chip, the image processing chip and the display control chip, can realize extremely simple image transmission, not only saves the hardware cost, but also can reduce the time delay in the image data transmission process.
The image processing chip of the image processing system provided by the embodiment of the invention comprises a mini ISP (Internet service provider), wherein the image processing chip is cut on the original function of the ISP, and only lens correction, dead pixel correction, denoising and format conversion are reserved, so that the basic display effect is ensured, and the delay of image processing is reduced.
The display control chip of the image processing system provided by the embodiment of the invention is convenient for designing a user interaction interface by adding a hardware cursor.
Drawings
Fig. 1 is a schematic diagram of a display device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an image processing flow of an image processing system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a sensing control chip and an image processing chip according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a display control chip according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
The open-source instruction set RISC-V is free to use for any purpose, compared to other instruction sets, allowing anyone to design, manufacture and sell RISC-V chips and software, because of these features, the industry is also constantly building ecosystems around it.
The technology of the internet of things is continuously developed, and the support of multiple scenes is emphasized more from the simple emphasis on connection. More and more intelligent hardware with visual ability appears, including intelligent door lock, intelligent cat eye, 86 intelligent panel, accuse, network camera etc. in the area screen intelligence. These smart devices will basically have a camera function as "eyes". After the camera collects the image data, the image data is processed and transmitted to the display screen.
However, the existing display screen has a single function, and usually needs an application processor or a micro control unit for processing to realize an intelligent display function, so that the realization is complex, the power consumption is large, and the time delay is high; for scenes with strict delay requirements or scenes with single display requirements, the implementation mode has redundant functions and cannot meet the requirements. Most of the existing graph transmission systems use application processors, the hardware cost is high, the performances such as power consumption and time delay are not good, and the requirements of current intelligent vision products are not met.
The invention provides an image processing system and a display device, which solve the problems of high hardware cost, large power consumption and low time delay of the image processing system in the prior art.
An embodiment of the present invention provides an image processing system, including:
RISC-V microprocessor, sensing control chip, image processing chip and display control chip;
the RISC-V microprocessor is used for controlling the sensing control chip to collect image data and controlling the display control chip to display the processed image data, and the image data comprises a plurality of pixel data;
the sensing control chip is used for acquiring the image data under the control of the RISC-V microprocessor and transmitting the acquired image data to the image processing chip;
the image processing chip is used for processing the image data acquired by the sensing control chip and transmitting the processed image data to the display control chip;
and the display control chip is used for displaying the processed image data.
Referring to fig. 1, the RISC-V microprocessor is connected to a sensing control chip through an APB peripheral bus, the sensing control chip controls a sensor (sensor) to collect an image and sample original data; then the original data is processed by an image processing chip and is transmitted to a system bus; the display of the control panel (panel) module is realized through the system bus and the display control chip.
The image processing system provided by the embodiment of the invention integrates the RISC-V microprocessor, the sensing control chip, the image processing chip and the display control chip, can realize extremely simple image transmission, not only saves the hardware cost, but also can reduce the time delay in the image data transmission process.
Illustratively, the sensing control chip comprises a local exposure module or a block exposure module;
the image is divided into a local area or a block area;
the local exposure module is used for exposing the image of the local area;
and the block exposure module is used for exposing the image of the block area.
The sensor can perform operations such as local exposure, block exposure and the like during image acquisition. Through local exposure and block exposure, the acquired image can be clearer.
Optionally, the display control chip specifically includes: the device comprises a pixel sorting module, an RAM palette, a gray scale voltage generation module and a panel formatting module;
the pixel sorting module is used for sorting the pixel data of the local area or the block area according to the horizontal and vertical coordinates of the local area or the block area to generate an index value of the pixel data;
the RAM palette is used for acquiring RGB color components of each pixel data according to the index value of the pixel data;
the gray scale voltage generation module is used for generating corresponding gray scale voltages according to the RGB color components of each pixel data;
and the panel formatting module is used for outputting the image data in an RGB (red, green and blue) arrangement mode according to the RGB arrangement mode set by the panel and formatting and outputting the image data.
Referring to fig. 4, the AHB main line control data is read into the internal register, subjected to pixel sorting and RAM palette to generate gray scale voltages, and then formatted by the panel to output display data.
The pixel sorting is that pixel data is locally updated according to horizontal and vertical coordinates of a local exposure area or a block exposure area, and sorting is carried out according to the coordinates.
The RAM palette selects the required RGB color components by using the index values, has small coding length, reduces the system burden, solves the contradiction between the data width and the color depth, and ensures that the color display is relatively rich.
The panel formatting is to perform data formatting output according to different panel display modes and RGB arrangement modes.
Illustratively, the display control chip further includes:
and the hardware cursor is used for displaying the cursor supported by the hardware in a manner of matching with the image.
The hardware cursor is used to simplify a Graphical User Interface (GUI) for facilitating design of the GUI.
Illustratively, the image processing chip includes:
a pixel sampling module and a Mini ISP chip;
the pixel sampling module is used for receiving the image data;
and the Mini ISP chip is used for processing the image data in real time and outputting the image data after lens correction, dead pixel correction, denoising and format conversion.
Referring to fig. 3, the image processing chip includes a mini ISP, which is cut on the original function of the ISP, and only lens correction, dead pixel correction, denoising and format conversion are retained, so that not only is the basic display effect ensured, but also the delay of image processing is reduced.
Illustratively, the image processing chip further includes: the output module is used for receiving the image data processed by the Mini ISP chip;
the output module includes: the first output module, the second output module and the third output module;
the first output module is used for realizing the preview of image data, and the first output module comprises a 2D image scaler and a pixel formatter, wherein the 2D image scaler is used for realizing the scaling of an image, and the pixel formatter is used for realizing the cutting of the image;
the second output module is used for realizing direct display of the image data;
the third output module is configured to implement encoding and decoding of image data, and the third output module includes:
the device comprises a coder and a decoder and a packing formatter, wherein the coder is used for coding and decoding image data, and the packing formatter is used for packing the image data.
Referring to fig. 3, the pixel data is received by the pixel sampling module, processed by the mini ISP, and has three output paths, one for the normal preview path, without encoding and decoding, and the data of the preview path can be used to implement simple video scaling and clipping by passing through the 2D image scaler and the pixel formatter; a codec path for storing the image data passed through the codec in a packed format in a memory; and the other direct display path is the display path with the lowest delay without other processing.
Illustratively, the image processing chip further comprises:
and the core video arbitrator is used for merging the image data output by the first output module, the second output module and the third output module respectively.
Referring to fig. 3, the image data output by the first output module, the second output module, and the third output module are all input to the core video arbitrator, and the image data is shared by the core video arbitrator.
Illustratively, the image processing system further comprises an extension module connected with the core video arbitrator, and the extension module is used for receiving a user instruction or automatically detecting an application scene to realize mode switching under different application scenes; and
the method is used for displaying a menu under different application scenes, and the menu at least comprises a mode switching option.
Referring to fig. 3, an extension module is further connected to the core video arbiter end, and may be used for application scene extension, mode switching, menu display, and the like, where the module needs to display a hardware cursor in the control chip for use in cooperation, and in some application scenes, such as an intelligent doorbell, menu options may be superimposed in a camera picture, and a menu switch signal is linked with a mechanical signal of the door lock, so as to implement intelligent control.
The mode switching includes switching of the three output paths described above, i.e., switching between the preview path, the codec path, and the direct display path.
Referring to fig. 1 and 2, the image processing system adopts RISC-V architecture, RISC-V microprocessor controls sensor image acquisition through APB peripheral bus, sampling original data; then the original data is processed by the image and transmitted to a system bus; and the panel module is controlled to display through a system bus and a display control chip. The sensing control chip comprises frame synchronization control, a pixel clock and register configuration; the image processing chip comprises a mini ISP, cutting is carried out on the original function of the ISP, and only lens correction, dead pixel correction, denoising and format conversion are reserved, so that the basic display effect is ensured, and the delay of image processing can be reduced; the image processing chip also comprises display mode selection, including options of original image direct output, image magnification and reduction, mode switching, menu display and the like; the display control chip comprises display data processing, time sequence control, interrupt output and the like.
Referring to fig. 3, a detailed flowchart of the operation of the sensing control chip and the image processing chip is shown. As shown in fig. 3, the microkernel controls the configuration of the sensor register through the APB bus, and sends a reset signal and a system clock MCLK to the sensor, the sensor starts to operate after being reset, and the PLL inside the sensor generates the pixel clock PCLK and the corresponding Vsync and Hsync synchronization signals to control the synchronous transmission of the pixel data. The pixel data is received through a sampling unit, processed by a mini ISP (Internet service provider), and provided with three output paths, wherein one output path is used for a normal preview path, coding and decoding are not needed, and the data of the preview path can be used for realizing simple video scaling and shearing through a 2D (two-dimensional) image scaler and a pixel formatter; a codec path for storing the image data passed through the codec in a packed format in a memory; and the other direct display path is the display path with the lowest delay without other processing. The core video arbiter end is also connected with an extension module which can be used for application scene extension, mode switching, menu display and the like, the module needs to display the hardware cursor in the control chip for matching use, menu options can be superposed in a camera picture in some application scenes such as an intelligent doorbell, and a menu switch signal is linked with a door lock mechanical signal to realize intelligent control.
Referring to fig. 4, a detailed flowchart of the operation of the control chip is shown. The AHB main line is responsible for converting pixel encoded data into a data format required by the display device, and the data format is as follows: the AHB main line control data is read into an internal register, gray scale voltage is generated through pixel sorting and RAM palette, display data is output after the display data is formatted by a panel, the display data comprises a hardware cursor to simplify a Graphical User Interface (GUI), and finally a data signal is output by a source driver. In the data reading process, the block scanning or line-by-line scanning data reading can be realized, refreshing of one frame of data is not needed, and the time delay is saved. The AHB master line and slave line are responsible for display clock control, as follows: the AHB main line signal is subjected to mode selection to distinguish between command mode and video mode, to determine whether a frame buffer GRAM is required, and then the signal is subjected to a DIP digital image processing chip (which may have CABC, DCE, etc.) to determine a clock controller signal together with a dc conversion signal of a clock generator. The clock controller signal and the panel clock generator signal together determine the gate control output. In addition, when a bus is in error or data is abnormal, an interrupt signal is sent out, and data is transmitted and managed through interrupt and DMA, so that the efficiency of image transmission is improved.
The embodiment of the invention also discloses a display device which comprises an image acquisition system, the image processing system and the image display system.
Wherein, image acquisition system includes: cameras, sensors, etc. The image display system comprises a liquid crystal screen, an LED screen, an organic light emitting display screen and the like.
Wherein, image processing system includes:
RISC-V microprocessor, sensing control chip, image processing chip and display control chip;
the RISC-V microprocessor is used for controlling the sensing control chip to collect image data and controlling the display control chip to display the processed image data, and the image data comprises a plurality of pixel data;
the sensing control chip is used for acquiring the image data under the control of the RISC-V microprocessor and transmitting the acquired image data to the image processing chip;
the image processing chip is used for processing the image data acquired by the sensing control chip and transmitting the processed image data to the display control chip;
and the display control chip is used for displaying the processed image data.
Referring to fig. 1, the RISC-V microprocessor is connected to a sensing control chip through an APB peripheral bus, the sensing control chip controls a sensor (sensor) to collect an image and sample original data; then the original data is processed by an image processing chip and is transmitted to a system bus; the display of the control panel (panel) module is realized through the system bus and the display control chip.
The image processing system provided by the embodiment of the invention integrates the RISC-V microprocessor, the sensing control chip, the image processing chip and the display control chip, can realize extremely simple image transmission, not only saves the hardware cost, but also can reduce the time delay in the image data transmission process.
Illustratively, the sensing control chip comprises a local exposure module or a block exposure module;
the image is divided into a local area or a block area;
the local exposure module is used for exposing the image of the local area;
and the block exposure module is used for exposing the image of the block area.
The sensor can perform operations such as local exposure, block exposure and the like during image acquisition. Through local exposure and block exposure, the acquired image can be clearer.
Optionally, the display control chip specifically includes: the device comprises a pixel sorting module, an RAM palette, a gray scale voltage generation module and a panel formatting module;
the pixel sorting module is used for sorting the pixel data of the local area or the block area according to the horizontal and vertical coordinates of the local area or the block area to generate an index value of the pixel data;
the RAM palette is used for acquiring RGB color components of each pixel data according to the index value of the pixel data;
the gray scale voltage generation module is used for generating corresponding gray scale voltages according to the RGB color components of each pixel data;
and the panel formatting module is used for outputting the image data in an RGB (red, green and blue) arrangement mode according to the RGB arrangement mode set by the panel and formatting and outputting the image data.
Referring to fig. 4, the AHB main line control data is read into the internal register, subjected to pixel sorting and RAM palette to generate gray scale voltages, and then formatted by the panel to output display data.
The pixel sorting is that pixel data is locally updated according to horizontal and vertical coordinates of a local exposure area or a block exposure area, and sorting is carried out according to the coordinates.
The RAM palette selects the required RGB color components by using the index values, has small coding length, reduces the system burden, solves the contradiction between the data width and the color depth, and ensures that the color display is relatively rich.
The panel formatting is to perform data formatting output according to different panel display modes and RGB arrangement modes.
Illustratively, the display control chip further includes:
and the hardware cursor is used for displaying the cursor supported by the hardware in a manner of matching with the image.
The hardware cursor is used to simplify a Graphical User Interface (GUI) for facilitating design of the GUI.
Illustratively, the image processing chip includes:
a pixel sampling module and a Mini ISP chip;
the pixel sampling module is used for receiving the image data;
and the Mini ISP chip is used for processing the image data in real time and outputting the image data after lens correction, dead pixel correction, denoising and format conversion.
Referring to fig. 3, the image processing chip includes a mini ISP, which is cut on the original function of the ISP, and only lens correction, dead pixel correction, denoising and format conversion are retained, so that not only is the basic display effect ensured, but also the delay of image processing is reduced.
Illustratively, the image processing chip further includes: the output module is used for receiving the image data processed by the Mini ISP chip;
the output module includes: the first output module, the second output module and the third output module;
the first output module is used for realizing the preview of image data, and the first output module comprises a 2D image scaler and a pixel formatter, wherein the 2D image scaler is used for realizing the scaling of an image, and the pixel formatter is used for realizing the cutting of the image;
the second output module is used for realizing direct display of the image data;
the third output module is configured to implement encoding and decoding of image data, and the third output module includes:
the device comprises a coder and a decoder and a packing formatter, wherein the coder is used for coding and decoding image data, and the packing formatter is used for packing the image data.
Referring to fig. 3, the pixel data is received by the pixel sampling module, processed by the mini ISP, and has three output paths, one for the normal preview path, without encoding and decoding, and the data of the preview path can be used to implement simple video scaling and clipping by passing through the 2D image scaler and the pixel formatter; a codec path for storing the image data passed through the codec in a packed format in a memory; and the other direct display path is the display path with the lowest delay without other processing.
Illustratively, the image processing chip further comprises:
and the core video arbitrator is used for merging the image data output by the first output module, the second output module and the third output module respectively.
Referring to fig. 3, the image data output by the first output module, the second output module, and the third output module are all input to the core video arbitrator, and the image data is shared by the core video arbitrator.
Illustratively, the image processing system further comprises an extension module connected with the core video arbitrator, and the extension module is used for receiving a user instruction or automatically detecting an application scene to realize mode switching under different application scenes; and
the method is used for displaying a menu under different application scenes, and the menu at least comprises a mode switching option.
Referring to fig. 3, an extension module is further connected to the core video arbiter end, and may be used for application scene extension, mode switching, menu display, and the like, where the module needs to display a hardware cursor in the control chip for use in cooperation, and in some application scenes, such as an intelligent doorbell, menu options may be superimposed in a camera picture, and a menu switch signal is linked with a mechanical signal of the door lock, so as to implement intelligent control.
The mode switching includes switching of the three output paths described above, i.e., switching between the preview path, the codec path, and the direct display path.
The display device includes but is not limited to: radio frequency unit, network module, audio output unit, input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. It will be appreciated by those skilled in the art that the above described configuration of the display device does not constitute a limitation of the display device, and that the display device may comprise more or less of the components described above, or some components may be combined, or a different arrangement of components. In the embodiment of the present invention, the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
In the embodiments of the methods of the present invention, the sequence numbers of the steps are not used to limit the sequence of the steps, and for those skilled in the art, the sequence of the steps is not changed without creative efforts.
It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments, since they are substantially similar to the product embodiments, the description is simple, and the relevant points can be referred to the partial description of the product embodiments.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. An image processing system, comprising:
RISC-V microprocessor, sensing control chip, image processing chip and display control chip;
the RISC-V microprocessor is used for controlling the sensing control chip to collect image data and controlling the display control chip to display the processed image data, and the image data comprises a plurality of pixel data;
the sensing control chip is used for acquiring the image data under the control of the RISC-V microprocessor and transmitting the acquired image data to the image processing chip;
the image processing chip is used for processing the image data acquired by the sensing control chip and transmitting the processed image data to the display control chip;
and the display control chip is used for displaying the processed image data.
2. The image processing system according to claim 1, wherein the sensing control chip includes a local exposure module or a block exposure module;
the image is divided into a local area or a block area;
the local exposure module is used for exposing the image of the local area;
and the block exposure module is used for exposing the image of the block area.
3. The image processing system according to claim 2, wherein the display control chip specifically includes: the device comprises a pixel sorting module, an RAM palette, a gray scale voltage generation module and a panel formatting module;
the pixel sorting module is used for sorting the pixel data of the local area or the block area according to the horizontal and vertical coordinates of the local area or the block area to generate an index value of the pixel data;
the RAM palette is used for acquiring RGB color components of each pixel data according to the index value of the pixel data;
the gray scale voltage generation module is used for generating corresponding gray scale voltages according to the RGB color components of each pixel data;
and the panel formatting module is used for outputting the image data in an RGB (red, green and blue) arrangement mode according to the RGB arrangement mode set by the panel and formatting and outputting the image data.
4. The image processing system of claim 3, wherein the display control chip further comprises:
and the hardware cursor is used for displaying the cursor supported by the hardware in a manner of matching with the image.
5. The image processing system according to claim 1, wherein the image processing chip comprises:
the device comprises a pixel sampling module and a MiniISP chip;
the pixel sampling module is used for receiving the image data;
and the Mini ISP chip is used for processing the image data in real time and outputting the image data after lens correction, dead pixel correction, denoising and format conversion.
6. The image processing system of claim 5, wherein the image processing chip further comprises: the output module is used for receiving the image data processed by the Mini ISP chip;
the output module includes: the first output module, the second output module and the third output module;
the first output module is used for realizing the preview of image data, and the first output module comprises a 2D image scaler and a pixel formatter, wherein the 2D image scaler is used for realizing the scaling of an image, and the pixel formatter is used for realizing the cutting of the image;
the second output module is used for realizing direct display of the image data;
the third output module is configured to implement encoding and decoding of image data, and the third output module includes: the device comprises a coder and a decoder and a packing formatter, wherein the coder is used for coding and decoding image data, and the packing formatter is used for packing the image data.
7. The image processing system of claim 6, wherein the image processing chip further comprises:
and the core video arbitrator is used for merging the image data output by the first output module, the second output module and the third output module respectively.
8. The image processing system of claim 7, further comprising an extension module connected to the core video arbitrator, for implementing mode switching after receiving a user command or automatically detecting an application scene in different application scenes; and
the method is used for displaying a menu under different application scenes, and the menu at least comprises a mode switching option.
9. A display device comprising an image acquisition system, an image processing system according to any one of claims 1 to 8 and an image display system.
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