CN115379070A - Method for dynamically configuring clock to transmit HDMI image in real time based on FPGA - Google Patents
Method for dynamically configuring clock to transmit HDMI image in real time based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
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Abstract
The invention discloses a method for transmitting HDMI images in real time by dynamically configuring a clock based on FPGA, which comprises a GTX data receiving module, a clock dynamic configuration module and a GTX data output module, wherein the GTX data receiving module recovers a pixel clock according to the image input by HDMI to obtain the pixel clock input by HDMI, the clock dynamic configuration module calculates an output clock according to the current input resolution and locks the clock, and the GTX data output module refers to the current pixel clock and outputs the HDMI images. The invention has the beneficial effects that: the transmission clock signal of the HDMI is generated by adopting the internal clock of the FPGA, the clock can be dynamically transmitted in real time according to images with different resolutions at the front end, the clock signal synchronization is realized, the requirements of different resolutions are met, the real-time transmission of the HDMI images is realized, and the testability of the images is provided in the loop test design.
Description
Technical Field
The invention relates to an HDMI image transmission method, in particular to a method for transmitting HDMI images in real time by dynamically configuring a clock based on an FPGA, and belongs to the technical field of HDMI image transmission.
Background
In the process of designing and using the HDMI image transmission, in order to ensure the data transmission synchronization, an external clock crystal oscillator chip is generally selected during output, so that the data transmission is ensured to be effective. In the prior art: one way is that the configurable clock chip is mostly an import chip in the selection type; the other mode is that in a domestic chip, the clock precision is not enough, and the deviation is large. By using the two modes, an additional clock chip control mode is required to be added, and an external interface is added, so that the pressure-resistant risk of the system is increased, and the image processing speed is reduced.
Disclosure of Invention
The present invention is directed to solve at least one of the above problems, and an object of the present invention is to provide a method for transmitting an HDMI image in real time by dynamically configuring a clock based on an FPGA, which can improve transmission efficiency, save resources, save PCB space by reducing one clock chip, reduce output interfaces, generate a clock signal of an HDMI inside an FPGA, and efficiently transmit image data.
The invention achieves the above purpose through the following technical scheme: a method for dynamically configuring a clock to transmit an HDMI image in real time based on an FPGA comprises a GTX data receiving module, a clock dynamic configuration module and a GTX data output module;
the GTX data receiving module recovers a pixel clock according to an image input by an HDMI to obtain the pixel clock input by the HDMI, the clock dynamic configuration module calculates an output clock according to the current input resolution and locks the clock, and the GTX data output module refers to the current pixel clock and outputs an HDMI image;
the transmission method comprises the following steps:
firstly, realizing dynamic configuration of a clock by using an FPGA (field programmable gate array) and outputting HDMI (high-definition multimedia interface) image data with any resolution, and realizing dynamic response of the clock by using clock resources inside the FPGA;
step two, the GTX data receiving module analyzes and obtains the resolution information of the input image, and an input clock signal is recovered to obtain a pixel clock of the current resolution;
thirdly, an input signal of the clock dynamic configuration module is derived from a current clock signal, in the clock dynamic configuration module, when the input clock is lower than 80MHz, the clock at the moment needs frequency multiplication output, and the GTX data output module assigns an output clock to be 3 times of the current input clock;
step four, comparing the frequency-doubled clock with 80MHz, if the frequency-doubled clock is lower than 80MHz, changing the output clock into 4 frequency-doubled current input clock, and comparing again until the output clock is higher than 80MHz;
step five, when the input clock is higher than 80MHz, the output clock of the GTX data output module is the current clock output, and the output clock is determined;
and step six, waiting for clock locking after determining the output clock.
As a still further scheme of the invention: in the first step, the HDMI image data input clocks distinguished at will are different, and the input clock signals are selected to ensure that the clock is homologous, and the polarity and the phase are kept consistent, so that the image data synchronous transmission is realized.
As a still further scheme of the invention: in the third step, when the clock signal is output, the clock signal is output from the interior of the FPGA in a single-end-to-differential mode, and the GTX data sending module is started to synchronously output the clock signal and the front-end BRAM cache data.
As a still further scheme of the invention: in the third step, in the data transmission process, in order to ensure real-time synchronization of data, an interrupt controller of a Microblaze processor or an ARM processor is used inside the FPGA to collect interrupt events generated by each module in the system, and the interrupt events are fed back to the Microblaze processor for corresponding processing.
The invention has the beneficial effects that: the transmission clock signal of the HDMI is generated by adopting the internal clock of the FPGA, the clock can be dynamically transmitted in real time according to images with different resolutions at the front end, the clock signal synchronization is realized, the requirements of different resolutions are met, the real-time transmission of the HDMI images is realized, and the testability of the images is provided in the loop test design.
Drawings
FIG. 1 is a block diagram of the system of the present invention;
FIG. 2 is a flow chart of the dynamic clock configuration of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 1 to 2, a method for transmitting an HDMI image in real time by dynamically configuring a clock based on an FPGA includes a GTX data receiving module, a clock dynamic configuration module, and a GTX data output module;
the GTX data receiving module recovers a pixel clock according to an image input by an HDMI to obtain the pixel clock input by the HDMI, the clock dynamic configuration module calculates an output clock according to the current input resolution and locks the clock, and the GTX data output module refers to the current pixel clock and outputs an HDMI image;
the transmission method comprises the following steps:
firstly, realizing dynamic configuration of a clock by using an FPGA (field programmable gate array) and outputting HDMI (high-definition multimedia interface) image data with any resolution, and realizing dynamic response of the clock by using clock resources inside the FPGA;
step two, a GTX data receiving module analyzes the resolution information of the input image, and recovers an input clock signal to obtain a pixel clock of the current resolution;
thirdly, an input signal of the clock dynamic configuration module is derived from a current clock signal, in the clock dynamic configuration module, when the input clock is lower than 80MHz, the clock at the moment needs frequency multiplication output, and the GTX data output module assigns an output clock to be 3 times of the current input clock;
step four, comparing the frequency-doubled clock with 80MHz, if the frequency is lower than 80MHz, changing the output clock to 4 frequency-doubled of the current input clock, and comparing again until the output clock is higher than 80MHz;
step five, when the input clock is higher than 80MHz, the output clock of the GTX data output module is the current clock output, and the output clock is determined;
and step six, waiting for clock locking after determining the output clock.
In the embodiment of the invention, in the first step, the HDMI image data input clocks with any resolution are different, and the input clock signal is selected to ensure that the clock is homologous, and the polarity and the phase are kept consistent, so as to realize the synchronous transmission of the image data.
In the third step of the present invention, when the clock signal is output, the clock signal is output from the interior of the FPGA from single end to differential end, and the GTX data transmission module is started to output the clock signal and the front-end BRAM cache data synchronously.
In the third step of the present invention, in order to ensure real-time synchronization of data during data transmission, an interrupt controller of a Microblaze processor or an ARM processor is used inside the FPGA to collect interrupt events generated by each module in the system, and the interrupt events are fed back to the Microblaze processor for corresponding processing.
Example two
A method for dynamically configuring a clock to transmit an HDMI image in real time based on an FPGA comprises the following steps:
the method comprises the following steps: after the HDMI signal source sends out image data, the GTX receiving module analyzes resolution information of a current input image according to a transmission protocol of the HDMI, caches the image data in a BRAM, and recovers an input clock signal to obtain a pixel clock of the current resolution;
step two: the input signals of the clock dynamic configuration module are derived from the current clock signals, the input clock signals with different resolutions are different, the input clock signals are selected, the clock homology is ensured, the polarity and the phase are kept consistent, the synchronous transmission of image data is realized, meanwhile, the internal data cache is reduced, and the BRAM resource is saved;
step three: in the clock dynamic configuration module, in order to display any resolution, the reconfigured clock is a GTX reference clock, and in order to ensure the normal output of the back-end GTX module, the internal clock threshold is 80MHz;
when the input clock is lower than 80MHz, the clock needs frequency multiplication output, the output clock is assigned to be 3 times of the current input clock, the frequency multiplied clock is compared with 80MHz, if the frequency is lower than 80MHz, the output clock is changed to be 4 times of the current input clock, and the comparison is carried out again until the output clock is higher than 80MHz;
step four: if the input clock of the clock module is higher than 80MHz, the output clock is the input clock, and after the output clock is determined, the clock module is written to wait for the clock to be locked;
step five: when the output clock is stable, the clock signal is output from the interior of the FPGA in a single-end-to-differential mode, a GTX data sending module is started, and the HDMI clock signal and the data are synchronously output;
in the data transmission process, in order to ensure real-time synchronization of data, an interrupt controller of a Microblaze processor (ARM processor) is used in the FPGA for collecting interrupt events generated by each module in the system and feeding the interrupt events back to the Microblaze processor for corresponding processing;
the Microblaze processor controls the internal information, so that synchronous transmission of internal data can be realized, and the real-time performance of the data is ensured.
The working principle is as follows: the transmission clock signal of the HDMI is generated by adopting the internal clock of the FPGA, the clock can be dynamically transmitted in real time according to images with different resolutions at the front end, the clock signal synchronization is realized, the requirements of different resolutions are met, the real-time transmission of the HDMI images is realized, and the testability of the images is provided in the loop test design.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it is to be understood that all embodiments may be combined as appropriate by one of ordinary skill in the art to form other embodiments as will be apparent to those of skill in the art from the description herein.
Claims (4)
1. A method for dynamically configuring a clock to transmit an HDMI image in real time based on an FPGA is characterized in that: the system comprises a GTX data receiving module, a clock dynamic configuration module and a GTX data output module;
the GTX data receiving module recovers a pixel clock according to an image input by an HDMI to obtain the pixel clock input by the HDMI, the clock dynamic configuration module calculates an output clock according to the current input resolution and locks the clock, and the GTX data output module refers to the current pixel clock and outputs an HDMI image;
the transmission method comprises the following steps:
firstly, realizing dynamic configuration of a clock by using an FPGA (field programmable gate array) and outputting HDMI (high-definition multimedia interface) image data with any resolution, and realizing dynamic response of the clock by using clock resources in the FPGA;
step two, a GTX data receiving module analyzes the resolution information of the input image, and recovers an input clock signal to obtain a pixel clock of the current resolution;
thirdly, an input signal of the clock dynamic configuration module is derived from a current clock signal, in the clock dynamic configuration module, when the input clock is lower than 80MHz, the clock at the moment needs frequency multiplication output, and the GTX data output module assigns an output clock to be 3 times of the current input clock;
step four, comparing the frequency-doubled clock with 80MHz, if the frequency-doubled clock is lower than 80MHz, changing the output clock into 4 frequency-doubled current input clock, and comparing again until the output clock is higher than 80MHz;
step five, when the input clock is higher than 80MHz, the output clock of the GTX data output module is the current clock output, and the output clock is determined;
and step six, waiting for clock locking after determining the output clock.
2. The method for real-time transmission of HDMI images according to claim 1, wherein said method comprises: in the first step, the HDMI image data input clocks distinguished at will are different, and the input clock signals are selected to ensure that the clock is homologous, and the polarity and the phase are kept consistent, so that the image data synchronous transmission is realized.
3. The method for real-time transmission of HDMI images according to claim 1, wherein said method comprises: in the third step, when the clock signal is output, the clock signal is output from the interior of the FPGA in a single-end-to-differential mode, and the GTX data sending module is started to synchronously output the clock signal and the front-end BRAM cache data.
4. The method for real-time transmission of HDMI images according to claim 1, wherein said method comprises: in the third step, in the data transmission process, an interrupt controller of a Microblaze processor or an ARM processor is used inside the FPGA to collect interrupt events generated by each module in the system, and the interrupt events are fed back to the Microblaze processor for corresponding processing.
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