CN104601910B - A kind of full HD video processing circuits in four tunnels based on FPGA - Google Patents
A kind of full HD video processing circuits in four tunnels based on FPGA Download PDFInfo
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Abstract
The full HD video processing circuits in four tunnels based on FPGA that the invention discloses a kind of, it includes fpga chip, and the fpga chip includes storage control, channel selection switch module, the first video layer laminating module, the second video layer laminating module, third video layer laminating module, the 4th video layer laminating module, video time-sequence control module, Video Composition module, video mode parameter controller, four video input processing modules and four video amplifier modules.By using the present invention is based on the both pip and pop video processing circuits of fpga chip, can meet the needs of acquisition process is carried out at the same time to multichannel full HD vision signal, but also have many advantages, such as that framework is simple, easily designed realization.The present invention can be widely applied to as a kind of full HD video processing circuits in four tunnels based on FPGA in HD video process field.
Description
Technical field
The present invention relates to FPGA technology more particularly to a kind of full HD video picture-in-pictures in four tunnels and picture out picture based on FPGA
Processing circuit.
Background technology
Technical term is explained
PIP：Picture-in-picture is to utilize digital image processing techniques, multiple pictures is shown simultaneously on same screen-picture,
I.e. on the key frame normally watched, while one or more sprites through overcompression are inserted into, to appreciate key frame
Meanwhile monitoring other pictures, picture-in-picture is that sprite is placed within key frame.
POP：Picture out picture, principle as picture-in-picture, difference lies in picture out picture be by sprite be placed in key frame it
Outside.
DSP：The abbreviation of digital signal processor, i.e. digital signal processor.
CPU：The abbreviation of Central Processing Unit, i.e. central processing unit.
Currently, the both pip and pop video processing technique in most of full HD recorded broadcast equipment is usually all using soft
The method of part design is realized, but is constrained to the operational capability and serial frame of DSP or CPU processor, generally at most can only be same
When sample the full HD video in 2 tunnels, and vision signal that cannot be full HD to multichannel simultaneously samples.Now, with high definition
Video camera is more and more universal, is carried out at the same time sampling to the full HD vision signal of multichannel to carry out the need of both pip and pop processing
Asking also becomes more and more, and therefore, a kind of can be simultaneously current to the circuit of multichannel full HD vision signal progress sampling processing
Problem in the urgent need to address.
Invention content
In order to solve the above-mentioned technical problem, at the object of the present invention is to provide a kind of full HD video in four tunnels based on FPGA
Manage circuit.
The technical solution adopted in the present invention is：A kind of full HD video processing circuits in four tunnels based on FPGA comprising
Fpga chip, the fpga chip include storage control, channel selection switch module, the first video layer laminating module, second
Video layer laminating module, third video layer laminating module, the 4th video layer laminating module, video time-sequence control module, video close
At module, video mode parameter controller, four video input processing modules and four video amplifier modules；
The output end of four video input processing modules is connect with the input terminal of storage control, the storage control
The output end of device processed is connect with the first input end of four video amplifier modules respectively, the output of four video amplifier modules
End is connect with the first input end of channel selection switch module, and the output end of the channel selection switch module is respectively with first
The first input end of video layer laminating module, the first input end of the second video layer laminating module, third video layer laminating module
First input end and the 4th video layer laminating module first input end connection, the output of the video time-sequence control module
End is regarded with the second input terminal of the first video layer laminating module, the second input terminal of the second video layer laminating module, third respectively
The second input terminal connection of the second input terminal and the 4th video layer laminating module of frequency layer laminating module, first video layer
The output end of laminating module passes sequentially through the second video layer laminating module, third video layer laminating module and the stacking of the 4th video
Add and module and then connect with the input terminal of Video Composition module, the output end of the video mode parameter controller respectively with four
The of the input terminal of video input processing module, the second input terminal of four video amplifier modules and channel selection switch module
Two input terminals connect；
The video input processing module includes that Video decoding module and video reduce module, the Video decoding module
The first input end that output end and video reduce module connect, the output end of the video diminution module and storage control it is defeated
Enter end connection, the output end of the video mode parameter controller reduces mould with the input terminal of Video decoding module and video respectively
Second input terminal of block connects；
The storage control is connected with memory.
Further, the storage control is DDR2 controllers, and the memory is DDR2 chips.
Further, the video mode parameter controller includes：
First control module for providing video format parameter for Video decoding module, and controls Video decoding module
Collected vision signal is decoded, to obtain effective video pixel；
Second control module, for providing diminution parameter for video diminution module and providing amplification for video amplifier module
Parameter, and control video and reduce the processing that module and video amplifier module are reduced and amplified to the vision signal of input；
Third control module makes channel selection switch module according to elder generation for controlling channel selection switch module
The vision signal of four video amplifier modules output is respectively correspondingly input to the first video layer laminating module, second by sequence afterwards
Video layer laminating module, third video layer laminating module and the 4th video layer laminating module, to realize that video layer is superimposed.
Further, the channel selection switch module is believed according to the video that sequencing exports four video amplifier modules
Number be respectively correspondingly input to the first video layer laminating module, the second video layer laminating module, third video layer laminating module with
And the 4th video layer laminating module is specially to realize that video layer is superimposed：
The vision signal of four video amplifier modules of channel selection switch module pair output is chosen, the channel
Selecting switch module exports the vision signal that first chooses to the first video layer laminating module as the first input foreground, described
First input background of the first video layer laminating module is preset color layers, and the first video layer laminating module pair first is defeated
Enter background and the first input foreground is overlapped, and the vision signal after superposition is exported as the second input background to second and is regarded
Frequency layer laminating module；The channel selection switch module exports the vision signal that second chooses to the as the second input foreground
Two video layer laminating modules, the second video layer laminating module pair second inputs background and the second input foreground is overlapped,
And it is exported the vision signal after superposition as third input background to third video layer laminating module；The channel selection switch
Module exports the vision signal that third is chosen to third video layer laminating module, the third video as third input foreground
Layer laminating module inputs background to third and third input foreground is overlapped, and the vision signal after superposition is defeated as the 4th
Enter background to export to the 4th video layer laminating module；The vision signal that the channel selection switch module is chosen the 4th is as the
Four input foregrounds are exported to the 4th video layer laminating module, and the 4th video layer laminating module pair the 4th inputs background and the 4th
Input foreground is overlapped, and the vision signal after superposition is sent to Video Composition module.
Further, second control module is specifically used for judging the place whether vision signal is reduced and amplified
Reason, if desired, then provided for video diminution module and reduce parameter and provide amplifying parameters for video amplifier module, and controlled
Video reduces the processing that module and video amplifier module are reduced and amplified to the vision signal of input, conversely, then control regards
Frequency reduces module and video amplifier module does not do the processing reduced and amplified to the vision signal of input.
Further, the video reduces module for using bilinear interpolation algorithm in the control of video mode parameter controller
Parameter is reduced in the lower adjustment of system, to be cut to the vision signal of input, to realize that the diminution of vision signal is handled；
The video amplifier module is used to lower in the control of video mode parameter controller using bilinear interpolation algorithm
Whole amplifying parameters, to be cut to the vision signal of input, to realize the enhanced processing of vision signal.
Further, the video time-sequence control module is used for the first video layer laminating module, the second video layer superposition mould
Block, third video layer laminating module and the 4th video layer laminating module carry out video timing control, to make video layer be superimposed
The vision signal that module generates is required video format.
The beneficial effects of the invention are as follows：Fpga chip has the advantages that parallel processing architecture, therefore, video of the invention electricity
Realize that vision signal that can be full HD to 4 tunnels simultaneously carries out parallel acquisition and processing, can be big by using fpga chip in road
Meets the needs of acquisition process is carried out at the same time to multichannel full HD vision signal greatly.Moreover, the circuit of the present invention uses FPGA
The parallel processing structure of chip realizes, therefore, circuit of the invention also has that system architecture is simple, easily designed realize, is
The advantages that system is stablized, is inexpensive.
Description of the drawings
The specific implementation mode of the present invention is described further below in conjunction with the accompanying drawings：
Fig. 1 is a kind of structural principle block diagram of the full HD video processing circuits in four tunnels based on FPGA of the present invention；
Fig. 2 is an a kind of specific embodiment structural principle of the full HD video processing circuits in four tunnels based on FPGA of the present invention
Block diagram.
Specific implementation mode
As shown in Figure 1, a kind of full HD video processing circuits in four tunnels based on FPGA comprising fpga chip, it is described
Fpga chip includes storage control, channel selection switch module, the first video layer laminating module, the second video layer superposition mould
Block, third video layer laminating module, the 4th video layer laminating module, video time-sequence control module, Video Composition module, video screen module
Formula parameter controller, four video input processing modules and four video amplifier modules；
The output end of four video input processing modules is connect with the input terminal of storage control, the storage control
The output end of device processed is connect with the first input end of four video amplifier modules respectively, the output of four video amplifier modules
End is connect with the first input end of channel selection switch module, and the output end of the channel selection switch module is respectively with first
The first input end of video layer laminating module, the first input end of the second video layer laminating module, third video layer laminating module
First input end and the 4th video layer laminating module first input end connection, the output of the video time-sequence control module
End is regarded with the second input terminal of the first video layer laminating module, the second input terminal of the second video layer laminating module, third respectively
The second input terminal connection of the second input terminal and the 4th video layer laminating module of frequency layer laminating module, first video layer
The output end of laminating module passes sequentially through the second video layer laminating module, third video layer laminating module and the stacking of the 4th video
Add and module and then connect with the input terminal of Video Composition module, the output end of the video mode parameter controller respectively with four
The of the input terminal of video input processing module, the second input terminal of four video amplifier modules and channel selection switch module
Two input terminals connect；
The video input processing module includes that Video decoding module and video reduce module, the Video decoding module
The first input end that output end and video reduce module connect, the output end of the video diminution module and storage control it is defeated
Enter end connection, the output end of the video mode parameter controller reduces mould with the input terminal of Video decoding module and video respectively
Second input terminal of block connects；
The storage control is connected with memory.Since the circuit of the present invention is for full HD vision signal, because
This, the video time-sequence control module is substantially HD video time-sequence control module, and the Video Composition module is substantially
HD video synthesis module.
It is further used as preferred embodiment, the storage control is DDR2 controllers, and the memory is
DDR2 chips.Preferably, the number of the DDR2 chips is 2.
It is further used as preferred embodiment, the video mode parameter controller includes：
First control module for providing video format parameter for Video decoding module, and controls Video decoding module
Collected vision signal is decoded, to obtain effective video pixel；
Second control module, for providing diminution parameter for video diminution module and providing amplification for video amplifier module
Parameter, and control video and reduce the processing that module and video amplifier module are reduced and amplified to the vision signal of input；
Third control module makes channel selection switch module according to elder generation for controlling channel selection switch module
The vision signal of four video amplifier modules output is respectively correspondingly input to the first video layer laminating module, second by sequence afterwards
Video layer laminating module, third video layer laminating module and the 4th video layer laminating module, to realize that video layer is superimposed.
It is further used as preferred embodiment, the channel selection switch module puts four videos according to sequencing
The vision signal of big module output is respectively correspondingly input to the first video layer laminating module, the second video layer laminating module, the
Three video layer laminating modules and the 4th video layer laminating module are specially to realize that video layer is superimposed：
The vision signal of four video amplifier modules of channel selection switch module pair output is chosen, the channel
Selecting switch module exports the vision signal that first chooses to the first video layer laminating module as the first input foreground, described
First input background of the first video layer laminating module is preset color layers, and the first video layer laminating module pair first is defeated
Enter background and the first input foreground is overlapped, and the vision signal after superposition is exported as the second input background to second and is regarded
Frequency layer laminating module；The channel selection switch module exports the vision signal that second chooses to the as the second input foreground
Two video layer laminating modules, the second video layer laminating module pair second inputs background and the second input foreground is overlapped,
And it is exported the vision signal after superposition as third input background to third video layer laminating module；The channel selection switch
Module exports the vision signal that third is chosen to third video layer laminating module, the third video as third input foreground
Layer laminating module inputs background to third and third input foreground is overlapped, and the vision signal after superposition is defeated as the 4th
Enter background to export to the 4th video layer laminating module；The vision signal that the channel selection switch module is chosen the 4th is as the
Four input foregrounds are exported to the 4th video layer laminating module, and the 4th video layer laminating module pair the 4th inputs background and the 4th
Input foreground is overlapped, and the vision signal after superposition is sent to Video Composition module.
It is further used as preferred embodiment, second control module is specifically used for judging whether vision signal needs
The processing reduced and amplified, if desired, then reduce module for video and provide and reduce parameter and be that video amplifier module is put forward
For amplifying parameters, and controls video and reduce what module and video amplifier module were reduced and amplified to the vision signal of input
Processing, conversely, then controlling, video reduces module and video amplifier module does not do the place for reducing and amplifying to the vision signal of input
Reason.
It is further used as preferred embodiment, the video reduces module and is used for using bilinear interpolation algorithm in video
Parameter is reduced in adjustment under the control of mode parameter controller, to be cut to the vision signal of input, to realize that video is believed
Number diminution processing；
The video amplifier module is used to lower in the control of video mode parameter controller using bilinear interpolation algorithm
Whole amplifying parameters, to be cut to the vision signal of input, to realize the enhanced processing of vision signal.
It is further used as preferred embodiment, the video time-sequence control module is used for the first video layer superposition mould
Block, the second video layer laminating module, third video layer laminating module and the 4th video layer laminating module carry out video sequential control
System, to make the vision signal that video layer laminating module generates be required video format.
The specific embodiment of the present invention
As shown in Fig. 2, a kind of full HD video processing circuits in four tunnels based on FPGA comprising four video input processing
Module, DDR2 controllers, the first DDR2 chips, the 2nd DDR2 chips, four video amplifier modules, channel selection switch module,
First video layer laminating module, the second video layer laminating module, third video layer laminating module, the 4th video layer laminating module,
HD video time-sequence control module, HD video synthesis module and video mode parameter controller；
Four video input processing modules, each video input processing module include a Video decoding module and a video
Module is reduced, as shown in Fig. 2, four video input processing modules specifically include the first Video decoding module, the decoding of the second video
Module, third Video decoding module, the 4th Video decoding module, the first video reduce module, the second video reduces module, third
Video reduces module and the 4th video reduces module, and the output end of first Video decoding module and the first video reduce mould
The first input end of block connects, the first input end of the output end of second Video decoding module and the second video diminution module
The output end of connection, the third Video decoding module is connect with the first input end of third video diminution module, and the described 4th
The first input end that the output end of Video decoding module reduces module with the 4th video is connect, the first video diminution module,
Second video reduces module, third video reduces module and the 4th video reduces module, this four videos reduce the defeated of module
Outlet is connect with the input terminal of DDR2 controllers；
The DDR2 controllers are connect with the first DDR2 chips and the 2nd DDR2 chips respectively；
As shown in Fig. 2, four video amplifier modules specifically include the first video amplifier module, the second video amplifier module,
Third video amplifier module and the 4th video amplifier module, the DDR2 controllers respectively with the first video amplifier module
One input terminal, the first input end of the second video amplifier module, the first input end of third video amplifier module and the 4th regard
The first input end of frequency amplification module connects, the first video amplifier module, the second video amplifier module, third video amplifier
Module and the 4th video amplifier module, the output ends of this four video amplifier modules with channel selection switch module first
Input terminal connects；
The output end of the channel selection switch module respectively with the first input end of the first video layer laminating module, second
The first input end of video layer laminating module, the first input end and the 4th video layer superposition mould of third video layer laminating module
The first input end of block connects, the output end of the HD video time-sequence control module respectively with the first video layer laminating module
Second input terminal, the second input terminal of the second video layer laminating module, third video layer laminating module the second input terminal and
Second input terminal of the 4th video layer laminating module connects；
The output end of the first video layer laminating module is connect with the third input terminal of the second video layer laminating module, institute
The output end for stating the second video layer laminating module is connect with the third input terminal of third video layer laminating module, the third video
The output end of layer laminating module is connect with the third input terminal of the 4th video layer laminating module, the 4th video layer laminating module
Output end connect with the input terminal of HD video synthesis module；
The output end of the video mode parameter controller respectively with the input terminal of the first Video decoding module, the second video
The input terminal of decoder module, the input terminal of third Video decoding module, the input terminal of the 4th Video decoding module, the contracting of the first video
Second input terminal of little module, the second video reduce the second input terminal of module, third video reduce module the second input terminal,
4th video reduces the second input terminal of module, the second input terminal of the first video amplifier module, the second video amplifier module
Second input terminal, the second input terminal of third video amplifier module, the second input terminal of the 4th video amplifier module and channel
Second input terminal of selecting switch module connects.
And shown in the concrete function of above-mentioned module is described below.
Video decoding module is mainly used for that the synchronizing signal of various video formats is responsible for parse, is effectively regarded with extraction
Frequency signal.
Video reduces module, is mainly used for lowering in the control of video mode parameter controller using bilinear interpolation algorithm
Whole diminution parameter, to be cut to the vision signal of input, to realize that the diminution of vision signal is handled.
Video amplifier module is mainly used for lowering in the control of video mode parameter controller using bilinear interpolation algorithm
Whole amplifying parameters, to be cut to the vision signal of input, to realize the enhanced processing of vision signal.
DDR2 chips, are mainly used for storage frame, are carried out respectively to 4 tunnel vision signals under the operation of DDR2 controllers
Read-write.
HD video time-sequence control module, be mainly used for the first video layer laminating module, the second video layer laminating module,
Third video layer laminating module and the 4th video layer laminating module carry out video timing control, to make video layer laminating module
The vision signal of generation is required video format.
The video mode parameter controller includes：
First control module for providing video format parameter for Video decoding module, and controls Video decoding module
Collected vision signal is decoded, to obtain effective video pixel；
Second control module, for providing diminution parameter for video diminution module and providing amplification for video amplifier module
Parameter, and control video and reduce the processing that module and video amplifier module are reduced and amplified to the vision signal of input,
Specifically, second control module is the processing whether reduced and amplified for judging vision signal, if desired,
It is then provided for video diminution module and reduces parameter and provide amplifying parameters for video amplifier module, and controlled video and reduce mould
The processing that block and video amplifier module are reduced and amplified to the vision signal of input, conversely, then controlling video reduces module
With video amplifier module the processing reduced and amplified is not done to the vision signal of input；
Third control module makes channel selection switch module according to elder generation for controlling channel selection switch module
The vision signal of four video amplifier modules output is respectively correspondingly input to the first video layer laminating module, second by sequence afterwards
Video layer laminating module, third video layer laminating module and the 4th video layer laminating module, to realize that video layer is superimposed；
The channel selection switch module is distinguished according to the vision signal that sequencing exports four video amplifier modules
Accordingly it is input to the first video layer laminating module, the second video layer laminating module, third video layer laminating module and the 4th
Video layer laminating module, to realize video layer be superimposed, be specially：
The vision signal of four video amplifier modules of channel selection switch module pair output is chosen, the channel
Selecting switch module exports the vision signal that first chooses to the first video layer laminating module as the first input foreground, described
First input background of the first video layer laminating module is preset color layers, and the preset color layers can be black or appoint
Meaning color；
The first video layer laminating module pair first inputs background and the first input foreground is overlapped, and will be after superposition
Vision signal as second input background export to the second video layer laminating module；The channel selection switch module is by second
The vision signal of selection is exported as the second input foreground to the second video layer laminating module, the second video layer laminating module
Second input background and the second input foreground are overlapped, and using the vision signal after superposition as third input background output
To third video layer laminating module；
The vision signal that third is chosen is exported as third input foreground to third and is regarded by the channel selection switch module
Frequency layer laminating module, the third video layer laminating module inputs background to third and third input foreground is overlapped, and will
Vision signal after superposition is exported as the 4th input background to the 4th video layer laminating module；
The vision signal that 4th chooses is exported as the 4th input foreground to the 4th and is regarded by the channel selection switch module
Frequency layer laminating module, the 4th video layer laminating module pair the 4th input background and the 4th input foreground are overlapped, and
Vision signal after superposition is sent to Video Composition module.
Channel selection switch module and 4 video layer laminating modules realize the superposition of video, that is, PIP/POP realities together
Existing core, by 4 tunnel vision signals of scaling under the control of HD video time-sequence control module by 4 stacking plus after
It is combined into full HD vision signal output all the way.
The principle that PIP/POP is realized：Assuming that foreground is front_ground, background back_ground, display output is
Display_ground, then there is display_ground=front_ground * alpha+back_ground *
Alpha_n, wherein+alpha_n=1 alpha, that is display_ground is front_ground and back_
Ground respectively multiplies what a coefficient was added, if alpha=0, the outputs of alpha_n=1 are background；Similarly, if alpha
=1, alpha_n=0 item output is foreground；Output is that two images are translucent folded if alpha=alpha_n=0.5
Add, that is, adjusts the value of alpha and alpha_n, transparency when its superposition may be implemented.
According to the circuit of aforementioned present invention, specific operation principle is as follows：
4 road high-definition video signals are input to 4 Video decoding modules simultaneously respectively（First Video decoding module, second regard
Frequency decoder module, third Video decoding module and the 4th Video decoding module）, video mode parameter controller is respectively four and regards
Frequency decoder module provide video format parameter, four Video decoding modules under the control of video mode parameter controller, to
Four tunnel vision signals are decoded, effective video pixel is obtained to extract；
It is corresponding respectively to be input to four and regard by four Video decoding modules, the four tunnel vision signals that are decoded that treated
Frequency reduces module（First video reduces module, the second video reduces module, third video reduces module and the 4th video reduces mould
Block）, then judge the vision signal of input, if its video format finally to be exported is more than or equal to original video format,
Video diminution processing is not done video diminution is carried out, if the video format finally to be exported is less than original video format to subtract
Data of few storage to DDR2 chips；Then, the 4 tunnel vision signals that module is reduced by four videos are input to DDR2 controls
It is written and read in device；
Four video amplifier modules（First video amplifier module, the second video amplifier module, third video amplifier module and
4th video amplifier module）The vision signal exported from DDR2 controllers is read respectively, next, it is determined that the video letter of input
Number, if the video format finally to be exported is more than or equal to original video format, video amplifier processing is done, if finally to export
Video format be less than original video format, then without video amplifier；
The third control module of video mode parameter controller finally needs the effect synthesized come control channel according to video
Selecting switch module, the vision signal point for making channel selection switch module be exported four video amplifier modules according to sequencing
Four video layer laminating modules Dui Ying be output to（First video layer laminating module, the second video layer laminating module, third video
Layer laminating module and the 4th video layer laminating module）, to realize that video layer is superimposed, wherein be overlapped in the following order：
First input background of the first video layer laminating module is pre-set color layer, which may be configured as black or arbitrary
Color, and the first of the first video layer laminating module the input background is the vision signal that channel selection switch module first is chosen,
First input background and the first input foreground are overlapped by the first video layer laminating module, and the video after superposition is believed
Number conduct second inputs background and exports to the second video layer laminating module；
The vision signal that second chooses is exported as the second input foreground to second and is regarded by the channel selection switch module
Frequency layer laminating module, the second video layer laminating module pair second inputs background and the second input foreground is overlapped, and will
Vision signal after superposition is exported as third input background to third video layer laminating module；
The vision signal that third is chosen is exported as third input foreground to third and is regarded by the channel selection switch module
Frequency layer laminating module, the third video layer laminating module inputs background to third and third input foreground is overlapped, and will
Vision signal after superposition is exported as the 4th input background to the 4th video layer laminating module；
The vision signal that 4th chooses is exported as the 4th input foreground to the 4th and is regarded by the channel selection switch module
Frequency layer laminating module, the 4th video layer laminating module pair the 4th input background and the 4th input foreground are overlapped, and
Vision signal after superposition is sent to Video Composition module.
It is obtained by above-mentioned, the both pip and pop video processing realized based on DSP or CPU processor compared to tradition
Circuit, circuit of the invention are realized using fpga chip, since fpga chip has the advantages that parallel processing architecture, this
The circuit of invention can carry out parallel acquisition and processing to the full HD vision signal in 4 tunnels simultaneously, to meet now to multi-path high-definition
Vision signal is carried out at the same time the demand of acquisition process.And the circuit of the present invention also simple, the easily designed reality with system architecture
The advantages that existing, system stabilization, low cost.
It is to be illustrated to the preferable implementation of the present invention, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalent variations or be replaced under the premise of without prejudice to spirit of that invention
It changes, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (7)
1. a kind of full HD video processing circuits in four tunnels based on FPGA, it is characterised in that：It includes fpga chip, the FPGA
Chip includes storage control, channel selection switch module, the first video layer laminating module, the second video layer laminating module,
Three video layer laminating modules, the 4th video layer laminating module, video time-sequence control module, Video Composition module, video mode ginseng
Number controller, four video input processing modules and four video amplifier modules；Four video input processing modules
Output end is connect with the input terminal of storage control, the output end of the storage control respectively with four video amplifier modules
First input end connection, the first input end of the output ends of four video amplifier modules with channel selection switch module
Connection, the output end of the channel selection switch module are regarded with the first input end of the first video layer laminating module, second respectively
The first input end of frequency layer laminating module, the first input end and the 4th video layer laminating module of third video layer laminating module
First input end connection, the output end of the video time-sequence control module is defeated with the second of the first video layer laminating module respectively
Enter end, the second input terminal of the second video layer laminating module, the second input terminal of third video layer laminating module and the 4th regards
Second input terminal of frequency layer laminating module connects, and the output end of the first video layer laminating module passes sequentially through the second video layer
Laminating module, third video layer laminating module and the 4th video layer laminating module connect with the input terminal of Video Composition module in turn
Connect, the output end of the video mode parameter controller respectively with the input terminal of four video input processing modules, four videos
Second input terminal of amplification module and the second input terminal connection of channel selection switch module；The video input processing module
Module is reduced including Video decoding module and video, first that output end and the video of the Video decoding module reduce module is defeated
Enter end connection, the input terminal for the output end and storage control that the video reduces module connects, the video mode parameter control
The second input terminal that the output end of device processed reduces module with the input terminal of Video decoding module and video respectively is connect；The storage
Controller is connected with memory；
The video mode parameter controller：
For providing video format parameter for Video decoding module, and Video decoding module is controlled to collected vision signal
It is decoded, to obtain effective video pixel；And
For providing diminution parameter for video diminution module and providing amplifying parameters for video amplifier module, and control video
Reduce the processing that module and video amplifier module are reduced and amplified to the vision signal of input；And
For controlling channel selection switch module, channel selection switch module is made to be put four videos according to sequencing
The vision signal of big module output is respectively correspondingly input to the first video layer laminating module, the second video layer laminating module, the
Three video layer laminating modules and the 4th video layer laminating module, to realize that video layer is superimposed.
2. a kind of full HD video processing circuits in four tunnels based on FPGA according to claim 1, it is characterised in that：Described
Storage control is DDR2 controllers, and the memory is DDR2 chips.
3. a kind of full HD video processing circuits in four tunnels based on FPGA according to claim 1 or claim 2, it is characterised in that：Institute
Stating video mode parameter controller includes：
First control module for providing video format parameter for Video decoding module, and controls Video decoding module to adopting
The vision signal collected is decoded, to obtain effective video pixel；
Second control module is joined for reducing module for video and providing to reduce parameter and provide amplification for video amplifier module
Number, and control video and reduce the processing that module and video amplifier module are reduced and amplified to the vision signal of input；
Third control module makes channel selection switch module according to successively suitable for controlling channel selection switch module
The vision signal that four video amplifier modules export respectively correspondingly is input to the first video layer laminating module, the second video by sequence
Layer laminating module, third video layer laminating module and the 4th video layer laminating module, to realize that video layer is superimposed.
4. a kind of full HD video processing circuits in four tunnels based on FPGA according to claim 3, it is characterised in that：It is described logical
The vision signal that four video amplifier modules export respectively correspondingly is input to by road selecting switch module according to sequencing
One video layer laminating module, the second video layer laminating module, third video layer laminating module and the 4th video layer laminating module,
To realize that video layer is superimposed, it is specially：
The vision signal of four video amplifier modules of channel selection switch module pair output is chosen, the channel selecting
Switch module exports the vision signal that first chooses to the first video layer laminating module as the first input foreground, and described first
First input background of video layer laminating module is preset color layers, the input of the first video layer laminating module pair first back of the body
Scape and the first input foreground are overlapped, and are exported the vision signal after superposition as the second input background to the second video layer
Laminating module；The vision signal that second chooses is exported as the second input foreground to second and is regarded by the channel selection switch module
Frequency layer laminating module, the second video layer laminating module pair second inputs background and the second input foreground is overlapped, and will
Vision signal after superposition is exported as third input background to third video layer laminating module；The channel selection switch module
The vision signal that third is chosen is exported as third input foreground to third video layer laminating module, the third video stacking
Add module to be overlapped third input background and third input foreground, and is carried on the back the vision signal after superposition as the 4th input
Scape is exported to the 4th video layer laminating module；The vision signal that the channel selection switch module is chosen the 4th is defeated as the 4th
Enter foreground to export to the 4th video layer laminating module, the 4th video layer laminating module pair the 4th input background and the 4th input
Foreground is overlapped, and the vision signal after superposition is sent to Video Composition module.
5. a kind of full HD video processing circuits in four tunnels based on FPGA according to claim 3, it is characterised in that：Described
Two control modules are specifically used for judging the processing whether vision signal is reduced and amplified, if desired, then contract for video
Little module provides to reduce parameter and provides amplifying parameters for video amplifier module, and controls video diminution module and video is put
The processing that big module is reduced and amplified to the vision signal of input, conversely, then controlling video reduces module and video amplifier
Module does not do the processing reduced and amplified to the vision signal of input.
6. a kind of full HD video processing circuits in four tunnels based on FPGA according to claim 3, it is characterised in that：It is described to regard
Frequency, which is reduced module and is used to be adjusted under the control of video mode parameter controller using bilinear interpolation algorithm, reduces parameter, to
The vision signal of input is cut, to realize that the diminution of vision signal is handled；The video amplifier module is used for using double
Linear interpolation algorithm adjusts amplifying parameters under the control of video mode parameter controller, to be carried out to the vision signal of input
It cuts, to realize the enhanced processing of vision signal.
7. a kind of full HD video processing circuits in four tunnels based on FPGA according to claim 1 or claim 2, it is characterised in that：Institute
Video time-sequence control module is stated for being superimposed to the first video layer laminating module, the second video layer laminating module, third video layer
Module and the 4th video layer laminating module carry out video timing control, to the vision signal for making video layer laminating module generate
For required video format.
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| CN111263208B (en) * | 2018-11-30 | 2022-11-04 | 杭州海康威视数字技术股份有限公司 | Picture synthesis method and device, electronic equipment and storage medium |
| CN111669517B (en) * | 2020-06-19 | 2022-10-11 | 艾索信息股份有限公司 | Video overlapping method |
| CN111757061B (en) * | 2020-06-29 | 2023-04-25 | 深圳市达程科技开发有限公司 | Camera for realizing single-channel transmission of two-way video data based on FPGA |
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| CN103813107A (en) * | 2014-03-05 | 2014-05-21 | 湖南兴天电子科技有限公司 | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) |
| CN204408493U (en) * | 2015-01-26 | 2015-06-17 | 广州海昇计算机科技有限公司 | A kind of four full HD video processing circuitss in tunnel based on FPGA |
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| CN103813107A (en) * | 2014-03-05 | 2014-05-21 | 湖南兴天电子科技有限公司 | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) |
| CN204408493U (en) * | 2015-01-26 | 2015-06-17 | 广州海昇计算机科技有限公司 | A kind of four full HD video processing circuitss in tunnel based on FPGA |
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