CN105430296A - Solving method for multi-picture division cracked screen display of high-definition video - Google Patents
Solving method for multi-picture division cracked screen display of high-definition video Download PDFInfo
- Publication number
- CN105430296A CN105430296A CN201510836098.9A CN201510836098A CN105430296A CN 105430296 A CN105430296 A CN 105430296A CN 201510836098 A CN201510836098 A CN 201510836098A CN 105430296 A CN105430296 A CN 105430296A
- Authority
- CN
- China
- Prior art keywords
- circuit
- hdmi
- sdi
- video
- screen display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2628—Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/265—Mixing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The invention discloses a solving method for multi-picture division cracked screen display of a high-definition video. The solving method adopts an SDI interface circuit, an HDMI interface circuit, a matrix chip, an SDI signal decoding circuit, an HDMI signal decoding circuit, an FPGA and a configuration circuit thereof, a DDR2 SDRAM data storage circuit and an HDMI signal coding circuit, wherein after the matrix chip receives SDI/HDMI signals from the SDI interface circuit and the HDMI interface circuit, the SDI signal decoding circuit and the HDMI signal decoding circuit decode the signals and convert into parallel digital signals; and then the parallel digital signals enter the FPGA and the configuration circuit thereof to extract, store and compound nine-channel video signals, and the processed data is converted into HDMI video signals by the HDMI signal coding circuit. The solving method provided by the invention can effectively solve the problem about multi-picture division cracked screen display of the high-definition video, and delay during display can be controlled within a frame by using the method.
Description
Technical field
The present invention relates to field of video processing, particularly relate to the many picture segmentation of a kind of HD video and split the solution that screen display shows.
Background technology
Along with the development of the technology such as computer, DSP, very lagre scale integrated circuit (VLSIC), image splitter starts to adopt hardware designs.First, each road vision signal is converted to digital video signal; Then, in digital field, each road vision signal is processed.Make the design of circuit, debugging be greatly improved.But the independently logical circuit used in design is more, the special dsp chip that even uses had goes the segmentation of large area flicker reduction of video pictures.Although can meet the requirement to vedio data processing speed, also need additional CPU to go coherent system work, whole system is still seemed, and volume is comparatively large, and system cost is higher.Along with the development of semiconducter process, FPGA has made significant headway at structure, speed, technique, integrated level and aspect of performance and has improved.
Multi-image divider is in the market uneven, have DSP processing scheme, has ARM control program, has fpga logic processing scheme etc., its stability and transmission delay different.
Summary of the invention
The object of this invention is to provide the many picture segmentation of a kind of HD video and split the solution that screen display shows, solve the problem mentioned in above-mentioned background.
For achieving the above object, the invention provides following technical scheme:
The many picture segmentation of a kind of HD video split the solution that screen display is shown, comprise SDI interface circuit, HDMI circuit, chip matrix, sdi signal decoding circuit, HDMI signal decoding circuit, FPGA and configuration circuit thereof, DDR2SDRAM data storage circuitry and HDMI Signal coding circuit, chip matrix is decoded by sdi signal decoding circuit and HDMI signal decoding circuit after SDI interface circuit and HDMI circuit receive SDI/HDMI signal, convert parallel digital signal to, then FPGA is entered and configuration circuit extracts nine tunnel vision signals, store, the functions such as synthesis, data after process are converted to HDMI video signal again by HDMI Signal coding circuit.
As preferred version of the present invention: the model of described sdi signal decoding circuit is GS2970.
As preferred version of the present invention: the model of described HDMI signal decoding circuit is ADV7611.
As preferred version of the present invention: the model of described HDMI Signal coding circuit is SiL9136.
Compared with prior art, the invention has the beneficial effects as follows: the present invention, by adopting the mode freezed, effectively can solve the many picture segmentation of HD video and split the problem that screen display shows, and its time delay can control within a frame.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the many picture segmentation of HD video split the solution that screen display is shown;
Fig. 2 is system realizing function block diagram;
Fig. 3 is the graph of a relation of YCBCR digital signal and H, V, DE signal;
Fig. 4 is the arrangement mode figure of 9 road video composite picture;
Fig. 5 is sequential chart of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Refer to Fig. 1 ~ 5, the many picture segmentation of a kind of HD video split the solution that screen display is shown, comprise SDI interface circuit, HDMI circuit, chip matrix, sdi signal decoding circuit, HDMI signal decoding circuit, FPGA and configuration circuit thereof, DDR2SDRAM data storage circuitry and HDMI Signal coding circuit, chip matrix is decoded by sdi signal decoding circuit and HDMI signal decoding circuit after SDI interface circuit and HDMI circuit receive SDI/HDMI signal, convert parallel digital signal to, then FPGA is entered and configuration circuit extracts nine tunnel vision signals, store, the functions such as synthesis, data after process are converted to HDMI video signal again by HDMI Signal coding circuit.
The model of sdi signal decoding circuit is GS2970.The model of HDMI signal decoding circuit is ADV7611.The model of HDMI Signal coding circuit is SiL9136.
The software section of system also comprises multiple effective video extraction module, multiple effective video reduces module, DDR2 image storage module, read-write control signal module, read/write address generation module and video image synthesis module,
Operation principle of the present invention is: although video pictures looks like motion continuously; that is a series of static images in fact; these images switch enough fast; make picture appear to continuous motion, one be called the specific time sequence information of field synchronization (verticalsync) when be used to specify new images from display; Often open rest image to be made up of scan line (scanline), namely along display from top to bottom, a line then a line carry out the data wire that shows, another kind is called that the time sequence information of row synchronous (horizontalsync) is used to specify new scan line and when starts display.
Synchronously capable and field synchronization information is transmitted by one of following 3 kinds of modes usually:
1. the synchronous and field sync signal of independent row;
2. independent composite synchronizing signal;
3. the composite synchronizing signal of vision signal is embedded.
Native system adopt be digital video, employing be technology 1..
The input resolution that the design adopts is 19200 × 1080/60Hz, and pixel clock is 148.5MHz.SDI/HDMI signal obtains YCBCR digital signal and H, V, DE signal of the 16 parallel-by-bit 4:2:2 being with pixel clock after decoding, and the correlation between them as shown in Figure 3.
Wherein, when DE is 1, process effective video, when DE is 0, process HSYNC and VSYNC signal.Digital video signal one frame that SDI/HDMI exports is made up of 1125 row video datas, each effective video behavior 1080 row, every a line has again 2200 pixels, wherein valid pixel has 1920, these are the data will used in video image building-up process, and each pixel comprises Y and CB/CR two kinds of signals.
In the continuous presence of pixel domain, first, original image is according to pixels extracted, respectively by multiway images according to certain scale smaller.Then, arranged by multiway images according to certain rule, the image after arrangement is the image of multichannel synthesis.Finally, the Image Coding of synthesis is exported, at the multiple picture of same screen display, the synthesis to multiway images can be completed.
Video image after synthesis shows line by line, and for by image in a row by row fashion " drafting " to the equipment on screen, often opening image is all from the upper left corner of display, move right always, until arrive the right hand edge of display, then scan a line downwards, repeatedly from left to right scan, till this process is continued until that whole screen is all refreshed once, as shown in Figure 4.
For 9 tunnels, first, 1/9 scale smaller to be carried out to original image respectively.Then to extract effective video capable in interlacing in vertical direction, makes vertical direction be reduced into original 1/3.
In the horizontal direction, horizontal direction is made to be reduced into original 1/3.The image down that the extraction that is vertical and horizontal direction of such process obtains is 1/9 of original image.
Then, arrange according to the pixel of array format to each road image extracted of a frame image data.The row and the 2nd of the 1st road image, row composition one full line of 3 road images that extract, row composition one full line of the row of the 4th road image and the 5th, 6 road images, row composition one full line of the row of the 7th road image and the 8th, 9 road images.The row of 9 road images forms the view data of a new two field picture.
Finally, 9 road composograph data being exported through SiI9136 coding, on a display, showing 9 road images by lining by line scan, namely complete 9 road video images synthesis.
The implementation method of video image picture synthesis is mainly divided into two large classes: pixel domain synthesis and compression domain synthesis.View data based on system is 16 Y, Cb/Cr video formats, so adopt the method for continuous presence in pixel domain in video image picture synthesis.The implementation procedure of 9 road video image synthesis is as follows:
First, extract effective video data in the vertical direction and the horizontal direction respectively, 9 road images are respectively reduced into 1/9 of original image.This part function is realized by effective video data extraction module, and this module had been done above and introduced in detail.Then each road view data extracted being arranged by looking for a definite sequence, being namely stored in DDR2SDRAM according to certain rule.The address of each road view data realizes according to address generating method presented hereinbefore, has the memory space of each self-retaining.
Complete the extraction of each road video image, after storage, will to extract each road video image carry out 9 picture synthesis.According to the data format of 1080P system digits signal, effective video data employing order from memory is read out, in the position of corresponding H, V, DE signal, send Video coding to export, complete the synthesis of 9 road video images.In the process of synthesis, H, V, DE signal and clock signal are all counted by output clock and produce, and the arrangement mode of 9 road video composite picture as shown in Figure 4.
When carrying out the debugging of many picture segmentation, often can find that showing of single sprite splits screen phenomenon, sequential chart shown in analysis chart 5 can find, due to each input and output video not homology, the synchronous width of corresponding frame synchronizing signal VS can be different, with the synchronous VS rising edge of output frame for reference, can find that input locking phase has situation before it and thereafter to the synchronous edge of output, reason is each not homology clock generating synchronizing signal separately, the time that electrifying startup configures each chip is also inconsistent, so want the data syn-chronization in each input different clocks must solve by frame buffer in output clock territory.
Produce that to split screen phenomenon be because the read/write address of frame buffer creates staggered collision, across two frame address buffer areas when one of them is exactly frame display, cause part display present frame, part display is previous frame in addition.
The present invention adopts the mode freezed to avoid above-mentionedly splitting screen problem, freezes by the speed detecting read-write direction frame synchronization address one frame time reading or write direction in real time.
Freezing method realize principle: the frame synchronizing signal not homology produced due to each passage, so be both the vision signal of 1080P60, its clock exist each other frequency difference and or frequency deviation, the time interval between the synchronous rising edge of each passage VS will be caused so different, and this output clock that can be produced by FPGA by counting statistics out.Longer when its time of running through a frame of passage that counting statistics value is larger, on the contrary slower.
Illustrate: 10 people race around playground, with the speed of one of them people as a reference, other 9 people follow this reference man to compare, the fleet-footed propelling along with the time can be enclosed than the many race one of this reference man, the meeting pulled up lame to be jogged a circle than this reference man, in order to ensure that everyone follows this reference man synchronous, the time that fleet-footed rest one of must stopping after a while is enclosed runs again, pull up lame reference man must be allowed to stop time that rest one encloses runs again.
In like manner the output VS of this system is exactly reference man, and other input VS and with reference to VS compares.Everyone running speed is the time difference (being counted by output clock) between respective frame synchronization rising edge, running how many frame needs the difference freezing to be counted by incoming frame and output frame to add up, when accumulated value is close to the time difference equaling a frame, just need the time freezing to input or export fast side one frame, namely read/write address needs stop one frame time.
Thoroughly solve after carrying out the debugging of FPGA on logic coding, emulation and plate by the method occur above split screen phenomenon, and delays time to control is within a frame.
Claims (4)
1. many picture segmentation of HD video split the solution that screen display is shown, it is characterized in that, comprise SDI interface circuit, HDMI circuit, chip matrix, sdi signal decoding circuit, HDMI signal decoding circuit, FPGA and configuration circuit thereof, DDR2SDRAM data storage circuitry and HDMI Signal coding circuit, chip matrix is decoded by sdi signal decoding circuit and HDMI signal decoding circuit after SDI interface circuit and HDMI circuit receive SDI/HDMI signal, convert parallel digital signal to, then FPGA is entered and configuration circuit extracts nine tunnel vision signals, store, the functions such as synthesis, data after process are converted to HDMI video signal again by HDMI Signal coding circuit.
2. the many picture segmentation of a kind of HD video according to claim 1 split the solution that screen display is shown, it is characterized in that, the model of described sdi signal decoding circuit is GS2970.
3. the many picture segmentation of a kind of HD video according to claim 1 split the solution that screen display is shown, it is characterized in that, the model of described HDMI signal decoding circuit is ADV7611.
4. the many picture segmentation of a kind of HD video according to claim 1 split the solution that screen display is shown, it is characterized in that, the model of described HDMI Signal coding circuit is SiL9136.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510836098.9A CN105430296A (en) | 2015-11-26 | 2015-11-26 | Solving method for multi-picture division cracked screen display of high-definition video |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510836098.9A CN105430296A (en) | 2015-11-26 | 2015-11-26 | Solving method for multi-picture division cracked screen display of high-definition video |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105430296A true CN105430296A (en) | 2016-03-23 |
Family
ID=55508197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510836098.9A Pending CN105430296A (en) | 2015-11-26 | 2015-11-26 | Solving method for multi-picture division cracked screen display of high-definition video |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105430296A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106371790A (en) * | 2016-10-12 | 2017-02-01 | 深圳市捷视飞通科技股份有限公司 | FPGA-based double-channel video multi-image segmentation display method and device |
| CN107027066A (en) * | 2017-03-24 | 2017-08-08 | 深圳市环球数码科技有限公司 | A kind of high-resolution digital cinema player method and system |
| CN110312158A (en) * | 2018-03-27 | 2019-10-08 | 北京市博汇科技股份有限公司 | A kind of monitoring method and device of embedded more pictures |
| CN110881092A (en) * | 2019-12-18 | 2020-03-13 | 广东高云半导体科技股份有限公司 | Image output method and system based on FPGA |
| US10628110B2 (en) | 2016-10-26 | 2020-04-21 | Boe Technology Group Co., Ltd. | Multi-screen display management system, display driving method and screen switching method |
| CN113114967A (en) * | 2018-01-22 | 2021-07-13 | 美国莱迪思半导体公司 | Multimedia communication bridge |
| CN113140173A (en) * | 2020-01-17 | 2021-07-20 | 华为技术有限公司 | Display driver, display control circuit system, electronic device, display driver control method, and display control circuit system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202160225U (en) * | 2011-06-03 | 2012-03-07 | 北京彩讯科技股份有限公司 | Digitized network video image synthesizer |
| CN203072086U (en) * | 2013-01-30 | 2013-07-17 | 西安科技大学 | FPGA-based multi-channel video capturing and displaying system |
| CN103813107A (en) * | 2014-03-05 | 2014-05-21 | 湖南兴天电子科技有限公司 | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) |
| CN103986960A (en) * | 2014-06-03 | 2014-08-13 | 王军明 | Method for single-video picture division route teletransmission precise synchronization tiled display |
| CN204231526U (en) * | 2014-12-13 | 2015-03-25 | 深圳新太开发科技有限公司 | A kind of high definition multiple images dispenser |
| CN204408493U (en) * | 2015-01-26 | 2015-06-17 | 广州海昇计算机科技有限公司 | A kind of four full HD video processing circuitss in tunnel based on FPGA |
-
2015
- 2015-11-26 CN CN201510836098.9A patent/CN105430296A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202160225U (en) * | 2011-06-03 | 2012-03-07 | 北京彩讯科技股份有限公司 | Digitized network video image synthesizer |
| CN203072086U (en) * | 2013-01-30 | 2013-07-17 | 西安科技大学 | FPGA-based multi-channel video capturing and displaying system |
| CN103813107A (en) * | 2014-03-05 | 2014-05-21 | 湖南兴天电子科技有限公司 | Multichannel high-definition video overlapping method based on FPGA (field programmable gata array) |
| CN103986960A (en) * | 2014-06-03 | 2014-08-13 | 王军明 | Method for single-video picture division route teletransmission precise synchronization tiled display |
| CN204231526U (en) * | 2014-12-13 | 2015-03-25 | 深圳新太开发科技有限公司 | A kind of high definition multiple images dispenser |
| CN204408493U (en) * | 2015-01-26 | 2015-06-17 | 广州海昇计算机科技有限公司 | A kind of four full HD video processing circuitss in tunnel based on FPGA |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106371790A (en) * | 2016-10-12 | 2017-02-01 | 深圳市捷视飞通科技股份有限公司 | FPGA-based double-channel video multi-image segmentation display method and device |
| US10628110B2 (en) | 2016-10-26 | 2020-04-21 | Boe Technology Group Co., Ltd. | Multi-screen display management system, display driving method and screen switching method |
| CN107027066A (en) * | 2017-03-24 | 2017-08-08 | 深圳市环球数码科技有限公司 | A kind of high-resolution digital cinema player method and system |
| CN113114967A (en) * | 2018-01-22 | 2021-07-13 | 美国莱迪思半导体公司 | Multimedia communication bridge |
| CN113114967B (en) * | 2018-01-22 | 2024-01-02 | 美国莱迪思半导体公司 | Multimedia communication bridge |
| CN110312158A (en) * | 2018-03-27 | 2019-10-08 | 北京市博汇科技股份有限公司 | A kind of monitoring method and device of embedded more pictures |
| CN110881092A (en) * | 2019-12-18 | 2020-03-13 | 广东高云半导体科技股份有限公司 | Image output method and system based on FPGA |
| CN110881092B (en) * | 2019-12-18 | 2021-03-26 | 广东高云半导体科技股份有限公司 | Image output method and system based on FPGA |
| CN113140173A (en) * | 2020-01-17 | 2021-07-20 | 华为技术有限公司 | Display driver, display control circuit system, electronic device, display driver control method, and display control circuit system |
| US11935489B2 (en) | 2020-01-17 | 2024-03-19 | Huawei Technologies Co., Ltd. | Display driver and control method, display control circuit system, and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105430296A (en) | Solving method for multi-picture division cracked screen display of high-definition video | |
| CN104917990B (en) | Video frame rate compensation is carried out by adjusting vertical blanking | |
| CN103021378B (en) | A kind of device for multi-screen mosaic display and method | |
| CN101000755B (en) | Multi-screen display splicing controller | |
| KR100830286B1 (en) | System and method for processing video data | |
| US9762814B2 (en) | Data processing method and device for LED televison, and LED television | |
| WO2017118078A1 (en) | Image processing method, playing method and related device and system | |
| KR102362054B1 (en) | Display apparatus consisting a multi display system and control method thereof | |
| CN105554416A (en) | FPGA (Field Programmable Gate Array)-based high-definition video fade-in and fade-out processing system and method | |
| US7405738B2 (en) | System and method for generating and processing a stream of video data having multiple data streams | |
| US11830413B2 (en) | Method, device for processing image, and system | |
| WO2017185761A1 (en) | Method and device for playing back 2d video | |
| CN104243964A (en) | Stereoscopic LED display control system and method and display control card | |
| CN105072353A (en) | Image decoding mosaic control algorism based on multiple GPUs | |
| US9239697B2 (en) | Display multiplier providing independent pixel resolutions | |
| CN103065349B (en) | A kind of data rendering method and device | |
| CN105472203A (en) | Genlock system and method | |
| CN103037169A (en) | Picture split joint combination method of embedded hard disk video | |
| CN104602095A (en) | Acquiring and synchronous display method and system for combined desktop | |
| CN110213640A (en) | Generation method, device and the equipment of virtual objects | |
| CN212137804U (en) | Point-to-point video splicing system | |
| CN103019639A (en) | Multiprocessor spliced synchronous display system | |
| CN102769732A (en) | Method for converting video fields | |
| CN102158655B (en) | Jitter-free post-correction system for digital video interface (DVI)/high definition multimedia interface (HDMI)/display port (DP)/video graphics array (VGA) signals | |
| CN108924261B (en) | High-speed frame accurate content feed display system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160323 |
|
| RJ01 | Rejection of invention patent application after publication |