CN106209292A - Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method - Google Patents
Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method Download PDFInfo
- Publication number
- CN106209292A CN106209292A CN201610541821.5A CN201610541821A CN106209292A CN 106209292 A CN106209292 A CN 106209292A CN 201610541821 A CN201610541821 A CN 201610541821A CN 106209292 A CN106209292 A CN 106209292A
- Authority
- CN
- China
- Prior art keywords
- clock
- stm
- bit
- data
- optical interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
Abstract
A method for implementing an SDH optical interface of STM-1 using an oversampling method, the method comprising the steps of: (1) a transmission path: the STM-1 transceiver generates an STM-1 data frame under 19.44M clock, the data frame is converted from 19.44M to 38.88M clock domain through a transmission clock domain converter, and each 1-bit data is copied into 4-bit data through a transmission data bit width converter under 38.88M clock rate, and the 4-bit data is transmitted to the STM-4 optical interface module for transmission. (2) A receiving path: receiving STM-1 signal from STM-4 optical interface, oversampling for 4 times per level at clock rate of 38.88M, finding STM-1 frame header, converting data from 4-bit to 1-bit, converting data into signal at 19.44M via receiving clock domain converter, and finally transmitting to STM-1 transceiver for deframing.
Description
Technical field
The invention belongs to the wire transmission communications field, the optical interface design being specifically related in SDH under STM-1 speed, permissible
It is applied to SDH transmission equipment, it is also possible to be applied to the design of SDH test instrunment.
Background technology
SDH technology is the most widely used in transmission system, provides multiple many for highly developed information-intensive society
The telecommunication service of sample.All it is proposed the optical interface chip supporting SDH technology based on these a lot of companies, wherein pushes away such as Maxim company
A series of Ethernet-over-SONET/SDH chip such as the DS33M30/DS33M31/DS33M33 gone out, can support STM-1
The transmitting-receiving of signal；The OC-48Transceiver chip that Cypress company releases, can support the transmitting-receiving of STM-16 signal.With
The maturation of SDH technology, its optical interface module the most gradually develops to miniaturization, normalization, Embedded direction, Xilinx company
The internal SerDes IP kernel provided of FPGA, be just built-in with the Transceiver option supporting STM-16 speed, by exchanging
SerDes module simply configure, it is possible to complete the receipts to tri-kinds of rate signals of STM-4, STM-16, STM-64
Send out.
But, inside Xilinx, the sample frequency of SerDes module common port is between 0.5G～12.5G, STM-1's
Signal rate not in the acceptable sample range of SerDes, therefore to the process of STM-1 signal can not with under other speed
Signal identical.This just makes the signal of four kinds of conventional for SDH speed that same interface can not be used to be transmitted.If used
The special Transceiver chip of STM-1 solves this problem, not only can take placement-and-routing's area of hardware circuit board, also
To arrange special STM-1 transceiver interface module inside FPGA, the complexity that will also result in FPGA internal code framework increases.
Summary of the invention
It is an object of the invention to overcome deficiencies of the prior art, it is provided that one utilizes oversampler method to realize
The method and apparatus of the SDH optical interface of STM-1.By realizing the over-sampling to STM-4 signal data stream, therefrom extract STM-
1 signal so that four kinds of conventional speed STM-1 of SDH, STM-4, STM-16, STM-64 can use unified optical interface to carry out
Data transmit-receive, saves hardware circuit board resource and simplifies the programming complexity of FPGA internal code.
Present invention firstly provides a kind of SDH optical interface device utilizing oversampler method to realize STM-1, this device includes
STM-1 frame receiver/transmitter, sending clock-domain changer, send data bit width changer, STM-4 optical interface module, Clock dividers,
Receive oversampler and receiving clock-domain changer；
The output signal of described STM-1 frame receiver/transmitter is successively through sending clock-domain changer and transmission data bit width conversion
STM-4 optical interface module input is connected after device；The signal that STM-4 optical interface module receives is received oversampler successively
The input entering STM-1 frame receiver/transmitter is connected with receiving clock-domain changer；The tranmitting data register of STM-4 optical interface module locking
Being connected with transmission data bit width changer and sending clock-domain changer, simultaneously through Clock dividers, output is to sending respectively
Clock zone changer and STM-1 frame receiver/transmitter；The reception clock of STM-4 optical interface module recovery and reception oversampler and reception
Clock zone changer is connected, and exports to receiving clock-domain changer and STM-1 frame receiver/transmitter through Clock dividers simultaneously.
Described Clock dividers includes tranmitting data register frequency divider and receives Clock dividers；Described reception oversampler
Including receiving bit parser, receiving delimiter resolver and receive over-sampling resolver.
The present invention, on the basis of above-mentioned SDH optical interface device, provides one simultaneously and is applicable to SDH STM-1 optical interface
Implementation method in Xilinx FPGA, comprises the steps of
1st, on transmission path, based on STM-1 frame receiver/transmitter, under 19.44M clock frequency, STM-1 frame, Mei Geshi are generated
Clock is along producing 8-bit data.
The method obtaining 19.44M clock is as follows: utilize the Transceiver IP kernel provided in Xilinx FPGA
The external local reference clock of SerDes module, and to configure this module be OC-48 pattern, then may utilize the phaselocked loop of this inside modules
Obtain 19.44M clock frequency and export.
2nd, on transmission path, based on sending clock-domain changer, STM-1 frame is transformed under 38.88M clock rate,
Each two clock is along corresponding 8-bit data.The 38.88M clock obtained is and the clock of the 19.44M clock homology in the 1st step.
Wherein, the method obtaining data under 38.88M clock frequency is as follows: using asynchronous FIFO, write clock is
19.44M, each clock is along corresponding 8-bit data, and readout clock is 38.88M, and each two clock is along reading 8-bit data.
3rd, on transmission path, in order to meet STM-4 interface rate, by every 1-bit in sending data bit width changer
Data copy as identical 4-bit data, deliver to STM-4 optical interface module.
The method wherein obtaining STM-4 signal is as follows: obtained STM-1 frame, each two 38.88M clock correspondence 8-bit
Data.Under 38.88M frequency, each clock is along every for 4-bit data bit is replicated four parts successively, and the most each clock is along the most right
Answer 16-bit data, generate STM-4 signal.
4th, STM-4 optical interface module is operated under 38.88M clock frequency with the transmission path of internal module, Mei Geshi
Clock is operated under 38.88M clock frequency along corresponding 16-bit data, STM-4 optical interface module with the receiving path of internal module,
Each clock is along corresponding 16-bit data.
5th, in receiving path, the STM-that optical interface is exported by the reception oversampler being operated under 38.88M clock frequency
4 signals carry out over-sampling parsing, obtain STM-1 signal, and each clock is along corresponding 4-bit data.Reception oversampler includes: connect
Receive bit parser, receive delimiter resolver and receive over-sampling resolver.
The method that signal carries out over-sampling parsing is as follows: the reception clock of STM-4 optical interface is 38.88M, each clock
Along corresponding 16-bit sampled data.Therefore, for STM-1 signal, every 1-bit data have all been sampled 4 times.STM-4 optical interface
The data received, should be 4 " 0 ", 4 " 1 " is one group, the random data occurred.Receive bit parser and carry out identical
The alignment of 4-bit data, receives delimiter resolver and is used for determining the frame header position of STM-1, receive over-sampling resolver by phase
Same 4-bit data carry out the conversion of 4-bit to 1-bit.
When data are alignd by reception bit parser, can be tolerated in and every 1-bit STM-1 data were adopted
The boundary of sample, has certain error code to occur.Receive bit parser error code to be repaired and export.
6th, in receiving path, based on receiving clock-domain changer, STM-1 signal is transformed into 19.44M clock frequency
Under, each clock enters STM-1 frame receiver/transmitter along corresponding 8-bit data, output signal.
The method of the STM-1 signal obtaining 19.44M is: using asynchronous FIFO, write clock is 38.88M, each clock
Along corresponding 4-bit data, readout clock is 19.44M, and each clock is along reading 8-bit data.
7th, based on Clock dividers, the 38.88M tranmitting data register that STM-4 optical interface is exported and recovery from circuit
38.88M receives clock and carries out two divided-frequency, meets the use requirement of STM-1 frame receiver/transmitter.
Advantages of the present invention and beneficial effect:
(1) use the mode that STM-4 rate signal carries out over-sampling to extract STM-1 signal, make the STM-1 signal can also
Obtained by the serdes IP kernel in example FPGA.Thus four kinds of conventional speed STM-1, STM-4, STM-16, STM-of SDH
64 can use unified optical interface to carry out data transmit-receive, save hardware circuit board resource and simplify the programming of FPGA internal code
Complexity.
(2) when extracting STM-1 data, for consecutive identical 4bit " 1 ", " 0 " data, can there is certain fault-tolerant energy
Power, the process making over-sampling is more stable.
Accompanying drawing illustrates:
Fig. 1 is system block diagram.
Fig. 2 is the input and output sequential chart of sending clock-domain changer.
Fig. 3 is the input and output sequential chart sending data bit width changer.
Fig. 4 is the input and output sequential chart receiving over-sampling resolver.
Fig. 5 is the input and output sequential chart of receiving clock-domain changer.
Detailed description of the invention
Below in conjunction with the accompanying drawings and example, technical scheme is described in detail.
Embodiment 1, oversampler method is utilized to realize the SDH optical interface device of STM-1
As it is shown in figure 1, this device includes STM-1 frame receiver/transmitter, sending clock-domain changer, sends data bit width conversion
Device, STM-4 optical interface module, Clock dividers, reception oversampler and receiving clock-domain changer；
The output signal of described STM-1 frame receiver/transmitter is successively through sending clock-domain changer and transmission data bit width conversion
The input of STM-4 optical interface module is connected after device；The signal that STM-4 optical interface module receives be received successively oversampler and
Receiving clock-domain changer connects entrance STM-1 frame receiver/transmitter；The tranmitting data register of STM-4 optical interface module locking and transmission data
Bit wide changer is connected with sending clock-domain changer, exports to STM-1 frame receiver/transmitter through Clock dividers simultaneously；STM-4
The reception clock of optical interface module recovery is connected, simultaneously through clock division with reception oversampler and receiving clock-domain changer
Device exports to STM-1 frame receiver/transmitter.
Described Clock dividers includes tranmitting data register frequency divider and receives Clock dividers；Described reception oversampler
Including receiving bit parser, receiving delimiter resolver and receive over-sampling resolver.
Embodiment 2, the method realizing the SDH optical interface of STM-1
The all schemes of the present invention all realize in Xilinx FPGA.
1st, refer to Fig. 1, FPGA completes coding and the emulation of STM-1 frame receiver/transmitter.This module includes STM-1 frame
Transmitting portion and resolve part.Transmitting portion with extraneous interface is: (1) tranmitting data register 19.44M, will by Clock dividers
The transmission 38.88M clock division of optical interface output；(2) the STM-1 frame that output sends, each clock is along corresponding 8-bit number
According to.Receiving portion with extraneous interface is: (1) receives clock 19.44M, the Clock dividers reception exported by optical interface
38.88M clock division；(2) the STM-1 frame that input receives, each clock is along corresponding 8-bit data.
2nd, Fig. 1 is referred to, the STM-4 optical interface module in example SerDes IP kernel in FPGA, i.e. figure.Made
Xilinx FPGA in, the input signal speed of SerDes core allows at 0.5G～12.5Gbps, can meet STM-4/
The speed of STM-16/STM-64, and the speed of STM-1 is 155.52Mbps, not in the range of this.If still to use
SerDes, then must try to be loaded on the signal of higher frequency STM-1.
Therefore, when carrying out the transmitting-receiving of STM-1, SerDes example can be turned to STM-4 pattern, i.e. select OC-48 pattern.
On transmission path, by each bit of STM-1, all replicate four parts and send, in receiving path, by receive
STM-1 carries out over-sampling, and i.e. every level signal is sampled four times, only takes sampled result once and exports.
The SerDes core of institute's example, arranges the data bit width sent and receive and is the frequency of 16-bit, STM-4 and be
622.08Mbps, then tranmitting data register and the reception clock of SerDes core output are 38.88M.
3rd, referring to Fig. 1, two divided-frequency distinguished by transmission and reception clock that SerDes is exported by Clock dividers, obtains
19.44M clock.The data-interface of STM-1 frame receiver/transmitter is 8-bit bit wide, therefore coordinates 19.44M clock, can meet
The speed of the 155.52Mbps of STM-1.
4th, Fig. 2 is referred to, for the input and output sequential chart of sending clock-domain changer.Sent by STM-1 frame receiver/transmitter
STM-1 frame be under 19.44M clock, therefore to be transformed under 38.88M clock.In sending clock-domain changer,
Using asynchronous FIFO, write clock is 19.44M, and each clock is along write 8-bit data, and readout clock is 38.88M, each two
Clock, along reading once, reads 8-bit data every time.
5th, Fig. 3 is referred to, for sending the input and output sequential chart of data bit width changer.For meeting STM-4 optical interface
The interface rate of module, needs every bit of STM-1 signal is replicated four parts.Under the clock of 38.88M, each clock is along multiple
4-bit processed, forms the data of 16-bit, sends into STM-4 optical interface.
6th, refer to Fig. 1, receiving side, the reception data of output in STM-4 optical interface initially enter to receive and adopt
Sample device, data stream passes sequentially through reception bit parser, receives delimiter resolver, reception over-sampling resolver.
Receive bit parser and the over-sampling data that reception comes are carried out the alignment of every identical 4-bit, i.e. this module output
Data, should be 16 ' h0000,16 ' h000f, 16 ' h00f0,16 ' h00ff, 16 ' h0f00,16 ' h0f0f, 16 ' h0ff0,16 '
H0fff, 16 ' hf000,16 ' hf00f, 16 ' hf0f0,16 ' hf0ff, 16 ' hff00,16 ' hff0f, 16 ' hfff0,16 ' hffff
Deng the one in 16 kinds of combinations.Now, it is contemplated that at the sample border of low and high level change, there may be certain error code and go out
Existing, therefore in the present invention, by 4 ' b0001 in sampled result, 4 ' b1000, the situation of 4 ' b1001, it is considered as 4 ' b0000；
By 4 ' b1110 in sampled result, 4 ' b0111, the situation of 4 ' b0110, it is considered as 4 ' b1111.Introduce this mechanism so that
The over-sampling of STM-4 signal there is is certain fault tolerance, has improve the stability of over-sampling.
Receive delimiter resolver and be used for finding the frame head of STM-1 frame, i.e. A1, A2 byte.If able to find continuous print 3
Individual " 16 ' hffff+16 ' h0ff0 " combines, and continuous print 3 " 16 ' h00f0+16 ' hf000 " combination, i.e. thinks and finds one
STM-1 frame head.By such data with clock along aliging output, it is achieved that STM-1 frame is synchronization with clock.
7th, Fig. 4 is referred to, for receiving the input and output sequential chart of over-sampling resolver.This module works in 38.88M and connects
Under time receiving clock, every identical 4-bit data taking 1-bit output, carries out the conversion of 16-bit to 4-bit, the most each clock is along defeated
Go out 4-bit data.
8th, Fig. 5 is referred to, for the input and output sequential chart of receiving clock-domain changer.This module by STM-1 signal by
38.88M clock zone is transformed into 19.44M clock zone.The method of conversion is, uses asynchronous FIFO, and write clock is 38.88M, often
Individual clock is along write 4-bit data；Readout clock is 19.44M, and each clock is along reading 8-bit data.These data are sent into
STM-1 frame receiver/transmitter, carries out follow-up frame and resolves.
Present invention achieves following function: the present invention is capable of following function: (1) this optical interface device can be independent from
Become module.By the process to STM-4 signal, complete the sampling of STM-1 signal.Overcome the sampling frequency of Transceiver
Rate does not support the shortcoming of STM-1, by the optical interface normalization of many for SDH kinds of speed.(2) this device has certain fault-tolerant ability.
During STM-4 is sampled, it is possible to the error code overcoming border shake to produce, strengthen the stability of sampling.
In view of all of the above, it is evident that, the practitioner of this area can be modified the present invention and modification is without deviating from this
Bright spirit and scope.All creation based on above-mentioned thinking and design, all should belong to scope disclosed in this invention.
Claims (10)
1. the SDH optical interface device that a kind utilizes oversampler method to realize STM-1, it is characterised in that this device includes STM-1 frame
Transceiver, sending clock-domain changer, send data bit width changer, STM-4 optical interface module, Clock dividers, received
Sampler and receiving clock-domain changer；
The output signal of described STM-1 frame receiver/transmitter is successively after sending clock-domain changer and transmission data bit width changer
Connect STM-4 optical interface module input；The signal that STM-4 optical interface module receives is received oversampler successively and connects
Receive clock zone changer and connect the input entering STM-1 frame receiver/transmitter；STM-4 optical interface module locking tranmitting data register with send out
Send data bit width changer to be connected with sending clock-domain changer, simultaneously through Clock dividers, export respectively to tranmitting data register
Territory changer and STM-1 frame receiver/transmitter；The reception clock of STM-4 optical interface module recovery and reception oversampler and reception clock
Territory changer is connected, and exports to receiving clock-domain changer and STM-1 frame receiver/transmitter through Clock dividers simultaneously.
2. device as claimed in claim 1, it is characterised in that described Clock dividers includes tranmitting data register frequency divider and connects
Receive Clock dividers；Described reception oversampler includes receiving bit parser, receives delimiter resolver and receiving and adopt
Sample resolver.
3. utilizing device described in claim 1 to realize the method for SDH optical interface of STM-1, described method includes walking as follows
Rapid:
1st, based on STM-1 frame receiver/transmitter, generating STM-1 frame under 19.44M clock frequency, each clock is along producing 8-bit number
According to；
2nd, based on sending clock-domain changer, being transformed under 38.88M clock rate by STM-1 frame, each two clock is along corresponding
8-bit data；
3rd, in order to meet STM-4 interface rate, in sending data bit width changer, every 1-bit data are copied as identical 4-
Bit data, deliver to STM-4 optical interface module；
4th, STM-4 optical interface module is operated under 38.88M clock frequency with the transmission path of internal module, each clock edge
Corresponding 16-bit data, STM-4 optical interface module is operated under 38.88M clock frequency with the receiving path of internal module, each
Clock is along corresponding 16-bit data；
5th, based on receiving oversampler, it is operated under 38.88M clock frequency, the STM-4 signal of optical interface output was carried out
Sampling resolves, and obtains STM-1 signal, and each clock is along corresponding 4-bit data；
6th, based on receiving clock-domain changer, being transformed under 19.44M clock frequency by STM-1 signal, each clock is along corresponding
8-bit data, output signal enters STM-1 frame receiver/transmitter；
7th, based on Clock dividers, the 38.88M tranmitting data register that STM-4 optical interface is exported and recovery from circuit
38.88M receives clock and carries out two divided-frequency, meets the use requirement of STM-1 frame receiver/transmitter.
4. method as claimed in claim 3, it is characterised in that the method obtaining 19.44M clock in the 1st step is as follows: utilize
The external local reference clock of Transceiver IP kernel SerDes module provided in Xilinx FPGA, and configure this module and be
OC-48 pattern, then the phaselocked loop that may utilize this inside modules obtains 19.44M clock frequency and exports.
5. method as claimed in claim 3, it is characterised in that the 38.88M clock obtained in the 2nd step be with in the 1st step
The clock of 19.44M clock homology.
6. method as claimed in claim 3, it is characterised in that the method obtaining data under 38.88M clock frequency in the 2nd step
As follows: using asynchronous FIFO, write clock is 19.44M, each clock is along corresponding 8-bit data, and readout clock is 38.88M,
Each two clock is along reading 8-bit data.
7. method as claimed in claim 3, it is characterised in that the method obtaining STM-4 signal in the 3rd step is as follows: in the 2nd step
The STM-1 frame obtained, each two 38.88M clock correspondence 8-bit data；This module is operated under 38.88M frequency, each clock
Along the every bit data in 4-bit data are replicated four parts successively, the most each clock, along final corresponding 16-bit data, generates
STM-4 signal.
8. method as claimed in claim 3, it is characterised in that the method that signal carries out in the 5th step over-sampling parsing is as follows:
The reception clock of STM-4 optical interface is 38.88M, and each clock is along corresponding 16-bit sampled data, therefore to STM-1 signal
Speech, every 1-bit data have all been sampled 4 times；The data that STM-4 optical interface receives, should be 4 " 0 ", 4 " 1 " go out at random
Existing data；Receive the reception bit parser in oversampler and carry out the alignment of identical 4-bit data, receive delimiter and resolve
Device is used for determining the frame header position of STM-1, receives over-sampling resolver and identical 4-bit data are carried out 4-bit to 1-bit's
Conversion.
9. method as claimed in claim 8, it is characterised in that when data are alignd by described reception bit parser, can
Be tolerated in the boundary that every 1-bit STM-1 data are carried out over-sampling, the 1st, the 4th " 0 " in the most identical 4 " 0 " and
, there is sampling error code at the 1st, the 4th " 1 " place in the most identical 4 " 1 "；Receive bit parser can error code be repaired also
Output.
10. method as claimed in claim 3, it is characterised in that the method obtaining the STM-1 signal of 19.44M described in the 6th step
For: using asynchronous FIFO, write clock is 38.88M, and each clock is along corresponding 4-bit data, and readout clock is 19.44M, often
Individual clock is along reading 8-bit data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610541821.5A CN106209292B (en) | 2016-07-11 | 2016-07-11 | Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610541821.5A CN106209292B (en) | 2016-07-11 | 2016-07-11 | Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106209292A true CN106209292A (en) | 2016-12-07 |
| CN106209292B CN106209292B (en) | 2018-05-11 |
Family
ID=57476225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610541821.5A Active CN106209292B (en) | 2016-07-11 | 2016-07-11 | Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106209292B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108121675A (en) * | 2017-12-04 | 2018-06-05 | 北京信而泰科技股份有限公司 | Timestamp synchronous method and device between different clock-domains |
| CN109120369A (en) * | 2018-11-23 | 2019-01-01 | 湖南有马信息技术有限公司 | A kind of SDH data processing method, system and relevant apparatus |
| CN111385065A (en) * | 2020-05-29 | 2020-07-07 | 湖南戎腾网络科技有限公司 | Interface rate self-adaption device and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1968063A (en) * | 2006-10-26 | 2007-05-23 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101330328A (en) * | 2008-07-24 | 2008-12-24 | 中兴通讯股份有限公司 | Method and apparatus for implementing multi-speed optical interface |
| WO2011134498A1 (en) * | 2010-04-27 | 2011-11-03 | Transmode Systems Ab | Data transmission involving multiplexing and demultiplexing of embedded clock signals |
-
2016
- 2016-07-11 CN CN201610541821.5A patent/CN106209292B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1968063A (en) * | 2006-10-26 | 2007-05-23 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101330328A (en) * | 2008-07-24 | 2008-12-24 | 中兴通讯股份有限公司 | Method and apparatus for implementing multi-speed optical interface |
| WO2011134498A1 (en) * | 2010-04-27 | 2011-11-03 | Transmode Systems Ab | Data transmission involving multiplexing and demultiplexing of embedded clock signals |
Non-Patent Citations (1)
| Title |
|---|
| 王晓晖等: "支持EOS的SDH通道交叉芯片的设计", 《光通信技术》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108121675A (en) * | 2017-12-04 | 2018-06-05 | 北京信而泰科技股份有限公司 | Timestamp synchronous method and device between different clock-domains |
| CN109120369A (en) * | 2018-11-23 | 2019-01-01 | 湖南有马信息技术有限公司 | A kind of SDH data processing method, system and relevant apparatus |
| CN109120369B (en) * | 2018-11-23 | 2019-03-05 | 湖南有马信息技术有限公司 | A kind of SDH data processing method, system and relevant apparatus |
| CN111385065A (en) * | 2020-05-29 | 2020-07-07 | 湖南戎腾网络科技有限公司 | Interface rate self-adaption device and method |
| CN111385065B (en) * | 2020-05-29 | 2020-09-11 | 湖南戎腾网络科技有限公司 | Interface rate self-adaption device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106209292B (en) | 2018-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7317733B1 (en) | Apparatus, system, and method for protocol conversion in transceiver modules | |
| CN101394678B (en) | Serialization/de-serialization interface module generally used in GEPON/GPON | |
| CN107465965B (en) | Optical port implementation method and device and field programmable gate array device | |
| US8446978B2 (en) | Communication system | |
| CN111193891A (en) | FPGA-based Camera Link data receiving system and transmission method | |
| CN103841009A (en) | FPGA method for achieving conversion and cascading between Ethernet data and E1 data | |
| CN106209292A (en) | Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method | |
| US20090251190A1 (en) | System and method for generating two effective frequencies using a single clock | |
| JP2004500740A (en) | HFC return path system using digital conversion and transmission | |
| CN103138866B (en) | A kind of SFP electricity mouth Apparatus and system of clock synchronous | |
| CN107171728A (en) | 1B4B and the forward direction of Manchester's code, reverse transfer method and device, system | |
| CN108322483A (en) | A kind of implementation method of the receiving terminal circuit based on JESD204B agreements | |
| US7652598B2 (en) | Serial data analysis improvement | |
| US8032916B2 (en) | Single master clock control of Ethernet data transfer over both a cable TV return path and an Ethernet forward path | |
| US7415089B2 (en) | High-speed serial link clock and data recovery | |
| CN201910048U (en) | LVDS (Low Voltage Differential Signaling) node module | |
| CN2751314Y (en) | Digital video-audio optical fiber transmission system | |
| CN101026448A (en) | Synchronous communication system clock regenerating method and system | |
| CN112865886B (en) | Method for realizing FC communication rate detection based on FPGA | |
| CN115278143A (en) | Method for realizing CML digital video interface based on FPGA | |
| US4782484A (en) | Encoding and decoding signals for transmission over a multi-access medium | |
| US20040177291A1 (en) | Simplifying verification of an SFI converter by data format adjustment | |
| CN206379950U (en) | A kind of error code instrument system | |
| EP0124576B1 (en) | Apparatus for receiving high-speed data in packet form | |
| CN110995390B (en) | Method for transparent transmission of SDH bus data based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 300392 Tianjin city Xiqing Binhai New District Huayuan Industrial Zone (outer ring) three Hai Tai Road No. 8 innovation Patentee after: Tianjin Deli Instrument Equipment Co., Ltd. Address before: 300392 Tianjin city Xiqing Binhai New District Huayuan Industrial Zone (outer ring) three Hai Tai Road No. 8 innovation Patentee before: Deli Electronic Instrument Co., Ltd., Tianjin City |