CN113852733A - Multi-source image low-delay parallel transmission circuit and method based on single-path coaxiality - Google Patents
Multi-source image low-delay parallel transmission circuit and method based on single-path coaxiality Download PDFInfo
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- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
- H04N5/067—Arrangements or circuits at the transmitter end
- H04N5/073—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
- H04N5/0733—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations for distributing synchronisation pulses to different TV cameras
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Abstract
The invention belongs to the technical field of image transmission processing, and particularly relates to a multi-source image low-delay parallel transmission circuit and a multi-source image low-delay parallel transmission method based on single-path coaxiality, wherein the multi-source image low-delay parallel transmission circuit based on the single-path coaxiality comprises the following steps: the system comprises a camera synchronization module, a data processing module, a parallel output synchronization module, a parallel-serial conversion module, an instruction communication module, a serial-parallel conversion module, a time sequence recovery module and a video separation module; the invention realizes the synthesis of three-channel video data by using the FPGA, and the video output is lossless, real-time and smooth.
Description
Technical Field
The invention belongs to the technical field of image transmission processing, and particularly relates to a multi-source image low-delay parallel transmission circuit and method based on single-path coaxiality.
Background
At present, as the image sensor is widely applied in the fields of automobile electronics and the like, the remote parallel transmission of multi-path images is mainly realized by adding physical connection. With the popularization of high-definition video, high-bandwidth data transmission solutions generally adopt ways such as ethernet, Camerlink, optical fiber, and coaxial. Compared with Ethernet, Camerlink and optical fiber, coaxial transmission has the characteristics of simple connection, high reliability, low cost and the like, and gradually becomes a mainstream transmission medium in the industry. For multi-source video transmission, one physical medium is generally adopted to transmit one channel, and the transmission architecture has obvious disadvantages: the system link is complex, and the link cost and maintenance are high; and, if applied to a centralized acquisition scenario, acquisition conversion costs are high.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide a multi-source image low-delay and wide-clock-range parallel transmission circuit and method based on single-channel coaxiality, which are used for solving the problem that more physical transmission media are needed in the existing multi-source video transmission.
(II) technical scheme
In order to solve the technical problem, the invention provides a multi-source image low-delay parallel transmission circuit based on single-path coaxiality, which comprises: the system comprises a camera synchronization module, a data processing module, a parallel output synchronization module, a parallel-serial conversion module, an instruction communication module, a serial-parallel conversion module, a time sequence recovery module and a video separation module;
the camera synchronization module is used for generating a video output time sequence of the three-way camera according to the pixel same-frequency clock CLK0, outputting the video output time sequence to an external synchronization interface circuit of the three-way camera, and realizing the video output synchronization of the three-way camera; the same-frequency clock CLK0 and a first input clock CLK1, a second input clock CLK2 and a third input clock CLK3 of the three-way camera are same-frequency and different-phase;
the data acquisition module is used for acquiring videos of the three-path camera, generating write enable for the acquired three-path video data according to respective self-motion and field synchronization respectively, and writing the write enable into three lines of cache dual-port RAMs respectively and correspondingly according to respective input clock sequences; that is, the first video Data1, the second video Data2, and the third video Data3 respectively generate write enable in accordance with the sequence of the first input clock CLK1, the second input clock CLK2, and the third input clock CLK3, respectively, in accordance with the respective self-line and field synchronization, and respectively write into the first line cache dual-port RAM1, the second line cache dual-port RAM2, and the third line cache dual-port RAM 3; the three paths of video data have the same resolution and the same clock frequency, but the clock phases are different because the three paths of video data are generated by different crystal oscillators, namely, different sources with the same frequency;
the parallel output synchronization module is used for generating a synchronous clock signal CLK4 according to the video output time sequence of the camera synchronization module, generating a read enable signal and an output synchronization time sequence of the three line buffer double-port RAMs by the synchronous clock signal CLK4 across a time domain, reading out video data pre-stored in the line buffer double-port RAMs, and outputting the video data to the parallel-serial conversion module in parallel with the synchronous clock signal CLK4 and the output synchronization time sequence; the parallel output synchronization module reads three line buffer double-port RAMs by adopting a synchronization clock signal CLK4 to obtain first video Data1, second video Data2 and third video Data 3; the first video Data1, the second video Data2 and the third video Data3 form new video Data and are input to the parallel-serial conversion module; the video data output by the three-way camera is cached in three line cache double-port RAM, and is read by adopting a synchronous clock signal CLK4 of a higher clock; since only line buffering is performed, the synchronous clock signal CLK4 should be at least higher than the camera video frequency to ensure smooth output video;
the parallel-serial conversion module comprises three parallel-serial conversion data input ends, a parallel-serial conversion clock input end and a parallel-serial conversion synchronous input end; the three parallel-serial conversion Data input ends, namely a parallel-serial conversion A, B, C Data input end, are respectively input by the first video Data1, the second video Data2 and the third video Data 3; the synchronous clock signal CLK4 is input to a parallel-serial conversion clock input end; line synchronization, field synchronization and data effective synchronization are output to a parallel-serial conversion synchronization input end; therefore, the parallel-serial conversion module realizes serial coding of three paths of parallel video data and outputs serial data; the serial data is transmitted to a serial-parallel conversion module through a coaxial line in a serial mode; the time sequence instruction information of the three cameras, including the clock frequency, the synchronous parameters and the frame frequency information of the cameras, is transmitted to the instruction communication module;
the instruction communication module is used for realizing the coaxial bidirectional communication of the time sequence instruction information of the parallel-serial conversion module and the serial-parallel conversion module through videos, and the time sequence instruction information comprises camera clock frequency, synchronous parameters and frame frequency information;
the serial-parallel conversion module is used for performing serial-parallel conversion on the serial Data and demodulating a synchronous clock signal CLK4, a first video Data1, a second video Data2 and a third video Data3 which are line synchronous, field synchronous and Data effective synchronous and parallel;
the time sequence recovery module is used for generating line synchronization, field synchronization, effective data synchronization and double-port RAM read enable which are the same as those of an original camera through phase-locked loops and camera video resolution, frame frequency and clock frequency information and outputting the line synchronization, the field synchronization, the effective data synchronization and the double-port RAM read enable to the video separation module;
the video separation module is used for generating double-port RAM write enable synchronously by demodulating lines, writing parallel first video Data1, second video Data2 and third video Data3 into a fourth line cache double-port RAM4, and synchronously separating separated video Data with the same frequency and time sequence as the three cameras from parallel video Data of the fourth line cache double-port RAM4 according to the double-port RAM read enable.
The data acquisition module performs clock domain crossing and time sequence processing on the acquired three paths of video data through RAM resources inside the FPGA, generates write enable according to the acquired three paths of video data respectively according to self-motion and field synchronization, and writes the respective input clocks into the 3-block line cache dual-port RAM in parallel.
The parallel output synchronization module generates a synchronous clock signal CLK4 according to a video output time sequence of the camera synchronization module, the synchronous clock signal CLK4 is the highest clock frequency of the parallel-serial conversion module, and is combined with a camera synchronization module output line synchronization trigger counter, a field synchronization trigger field counter and a data effective synchronization trigger data effective counter to delay 1 line time, so that a synchronous clock signal CLK4 is used for generating a time sequence for reading three double-port RAMs and an output synchronization time sequence, video data prestored in three-block line buffer double-port RAMs are read out, and the video data, the synchronous clock signal CLK4 and the output synchronization time sequence are output to the parallel-serial conversion module in parallel.
The parallel-serial conversion module respectively inputs the video data read out by the three double-port RAMs to a data input end of parallel-serial conversion A, B, C; and the synchronous clock signal CLK4, the line synchronization, the field synchronization and the data effective synchronization are output to the parallel-serial conversion clock input end and the parallel-serial conversion synchronous input end, so that the serial encoding output of the parallel data is realized.
The time sequence recovery module obtains the video resolution, the frame frequency and the clock frequency of the original camera according to the instruction communication module, generates a clock frequency CLK5 with the same frequency as a pixel common-frequency clock CLK0 through a local phase-locked loop, and generates a line synchronization, field synchronization, data effective synchronization and double-port RAM read enable which are the same as the original camera by combining a line synchronization trigger line counter, a field synchronization trigger field counter and a data effective synchronization trigger data effective counter output by the serial-parallel conversion module through the clock frequency CLK5 and delaying 1 line time, and outputs the line synchronization, the field synchronization, the data effective synchronization and the double-port RAM read enable to the video separation module.
The video separation module synchronously generates double-port RAM write-enable through demodulation lines, parallel data output by the serial-parallel conversion module are written into a 24-bit double-port RAM, read-enable and clock frequency CLK5 output by the timing recovery module are connected to the double-port RAM, and three paths of separated video data with the same frequency and the same timing sequence as the three cameras are synchronously separated from the parallel video data of the 24-bit double-port RAM according to the video resolution, the clock frequency and the frame frequency of the original cameras.
Wherein, the first video Data1, the second video Data2 and the third video Data3 are all 8bit Data.
In the process of the parallel output synchronization module, the new video Data formed by the first video Data1, the second video Data2 and the third video Data3 is 24-bit Data.
Wherein the fourth cache dual port RAM4 is a 24-bit dual port RAM.
In addition, the invention also provides a multi-source image low-delay parallel transmission method based on single-path coaxiality, wherein the parallel transmission method is implemented based on the parallel transmission circuit, and the method comprises the following steps:
step 1: the camera synchronization module generates a video output time sequence of the three-way camera according to the pixel same-frequency clock CLK0, and outputs the video output time sequence to an external synchronous interface circuit of the three-way camera to realize the video output synchronization of the three-way camera; the same-frequency clock CLK0 and a first input clock CLK1, a second input clock CLK2 and a third input clock CLK3 of the three-way camera are same-frequency and different-phase;
step 2: the data acquisition module acquires videos of the three cameras, generates write enable according to self-motion and field synchronization of the acquired video data of the three cameras respectively, and writes the write enable into three lines of cache dual-port RAMs respectively according to respective input clock sequences; that is, the first video Data1, the second video Data2, and the third video Data3 respectively generate write enable in accordance with the sequence of the first input clock CLK1, the second input clock CLK2, and the third input clock CLK3, respectively, in accordance with the respective self-line and field synchronization, and respectively write into the first line cache dual-port RAM1, the second line cache dual-port RAM2, and the third line cache dual-port RAM 3; the three paths of video data have the same resolution and the same clock frequency, but the clock phases are different because the three paths of video data are generated by different crystal oscillators, namely, different sources with the same frequency;
and step 3: the parallel output synchronization module generates a synchronous clock signal CLK4 according to the video output time sequence of the camera synchronization module, generates a read enable signal and an output synchronization time sequence of three line buffer double-port RAMs by crossing a time domain by the synchronous clock signal CLK4, reads out video data pre-stored in the line buffer double-port RAMs, and outputs the video data to the parallel-serial conversion module together with the synchronous clock signal CLK4 and the output synchronization time sequence in parallel; the parallel output synchronization module reads three line buffer double-port RAMs by adopting a synchronization clock signal CLK4 to obtain first video Data1, second video Data2 and third video Data 3; the first video Data1, the second video Data2 and the third video Data3 form new video Data and are input to the parallel-serial conversion module; the video data output by the three-way camera is cached in three line cache double-port RAM, and is read by adopting a synchronous clock signal CLK4 of a higher clock; since only line buffering is performed, the synchronous clock signal CLK4 should be at least higher than the camera video frequency to ensure smooth output video;
and 4, step 4: the parallel-serial conversion module comprises three parallel-serial conversion data input ends, a parallel-serial conversion clock input end and a parallel-serial conversion synchronous input end; the three parallel-serial conversion Data input ends, namely a parallel-serial conversion A, B, C Data input end, are respectively input by the first video Data1, the second video Data2 and the third video Data 3; the synchronous clock signal CLK4 is input to a parallel-serial conversion clock input end; line synchronization, field synchronization and data effective synchronization are output to a parallel-serial conversion synchronization input end; therefore, the parallel-serial conversion module realizes serial coding of three paths of parallel video data and outputs serial data; the serial data is transmitted to a serial-parallel conversion module through a coaxial line in a serial mode; the time sequence instruction information of the three cameras, including the clock frequency, the synchronous parameters and the frame frequency information of the cameras, is transmitted to the instruction communication module;
the instruction communication module realizes the coaxial bidirectional communication of the time sequence instruction information of the parallel-serial conversion module and the serial-parallel conversion module through video, and the time sequence instruction information comprises camera clock frequency, synchronous parameters and frame frequency information;
and 5: the serial-parallel conversion module carries out serial-parallel conversion on the serial Data and demodulates a synchronous clock signal CLK4, a first video Data1, a second video Data2 and a third video Data3 which are synchronous in line, field and Data valid synchronization and are parallel;
step 6: the time sequence recovery module generates line synchronization, field synchronization, effective data synchronization and double-port RAM read enable which are the same as those of an original camera through phase-locked loops and camera video resolution, frame frequency and clock frequency information, and outputs the line synchronization, the field synchronization, the effective data synchronization and the double-port RAM read enable to the video separation module;
and 7: the video separation module is used for generating double-port RAM write enable synchronously by demodulating lines, writing parallel first video Data1, second video Data2 and third video Data3 into a fourth line cache double-port RAM4, and synchronously separating separated video Data with the same frequency and time sequence as the three cameras from parallel video Data of the fourth line cache double-port RAM4 according to the double-port RAM read enable.
(III) advantageous effects
Compared with the prior art, the invention provides a multi-source image low-delay parallel transmission circuit and method based on single-path coaxiality, which are used for solving the problem that more physical transmission media are needed in the existing multi-source video transmission. The multi-source image low-delay parallel transmission circuit based on single-path coaxiality comprises: the system comprises a camera synchronization module, a data processing module, a parallel output synchronization module, a parallel-serial conversion module, an instruction communication module, a serial-parallel conversion module, a time sequence recovery module and a video separation module; the invention can solve the problem that the parallel-serial conversion circuit can not transmit three paths of video with the clock frequency lower than the lowest clock frequency of the parallel-serial conversion module clock in real time.
Drawings
FIG. 1 is a block diagram of the system shown in FIG. 1
FIG. 2 is a schematic diagram of a serial-to-parallel conversion information transmission process
FIG. 3 is a data conversion process
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the technical problems, the invention provides a multi-source image low-delay parallel transmission circuit based on single-path coaxiality, which is used for solving the problem that a parallel-serial conversion circuit cannot transmit three paths of videos with clock frequency lower than the lowest clock frequency of a parallel-serial conversion module clock in real time;
as shown in fig. 1, the multi-source image low-delay parallel transmission circuit based on single-channel coaxiality includes: the system comprises a camera synchronization module, a data processing module, a parallel output synchronization module, a parallel-serial conversion module, an instruction communication module, a serial-parallel conversion module, a time sequence recovery module and a video separation module;
the camera synchronization module is used for generating a video output time sequence of the three-way camera according to the pixel same-frequency clock CLK0, outputting the video output time sequence to an external synchronization interface circuit of the three-way camera, and realizing the video output synchronization of the three-way camera; the same-frequency clock CLK0 and a first input clock CLK1, a second input clock CLK2 and a third input clock CLK3 of the three-way camera are same-frequency and different-phase;
the data acquisition module is used for acquiring videos of the three-path camera, generating write enable for the acquired three-path video data according to respective self-motion and field synchronization respectively, and writing the write enable into three lines of cache dual-port RAMs respectively and correspondingly according to respective input clock sequences; that is, the first video Data1, the second video Data2, and the third video Data3 respectively generate write enable in accordance with the sequence of the first input clock CLK1, the second input clock CLK2, and the third input clock CLK3, respectively, in accordance with the respective self-line and field synchronization, and respectively write into the first line cache dual-port RAM1, the second line cache dual-port RAM2, and the third line cache dual-port RAM 3; the three paths of video data have the same resolution and the same clock frequency, but the clock phases are different because the three paths of video data are generated by different crystal oscillators, namely, different sources with the same frequency;
the parallel output synchronization module is used for generating a synchronous clock signal CLK4 according to the video output time sequence of the camera synchronization module, generating a read enable signal and an output synchronization time sequence of the three line buffer double-port RAMs by the synchronous clock signal CLK4 across a time domain, reading out video data pre-stored in the line buffer double-port RAMs, and outputting the video data to the parallel-serial conversion module in parallel with the synchronous clock signal CLK4 and the output synchronization time sequence; the parallel output synchronization module reads three line buffer double-port RAMs by adopting a synchronization clock signal CLK4 to obtain first video Data1, second video Data2 and third video Data 3; the first video Data1, the second video Data2 and the third video Data3 form new video Data and are input to the parallel-serial conversion module; the video data output by the three-way camera is cached in three line cache double-port RAM, and is read by adopting a synchronous clock signal CLK4 of a higher clock; since only line buffering is performed, the synchronous clock signal CLK4 should be at least higher than the camera video frequency to ensure smooth output video;
as shown in fig. 2, the parallel-to-serial conversion module includes three parallel-to-serial conversion data input terminals, a parallel-to-serial conversion clock input terminal, and a parallel-to-serial conversion synchronization input terminal; the three parallel-serial conversion Data input ends, namely a (8bit), a B (8bit) and a C (8bit) Data input end are respectively input by the first video Data1, the second video Data2 and the third video Data 3; the synchronous clock signal CLK4 is input to a parallel-serial conversion clock input end; line synchronization, field synchronization and data effective synchronization are output to a parallel-serial conversion synchronization input end; therefore, the parallel-serial conversion module realizes serial coding of three paths of parallel video data and outputs serial data; the serial data is transmitted to a serial-parallel conversion module through a coaxial line in a serial mode; the time sequence instruction information of the three cameras, including the clock frequency, the synchronous parameters and the frame frequency information of the cameras, is transmitted to the instruction communication module;
the instruction communication module is used for realizing the coaxial bidirectional communication of the time sequence instruction information of the parallel-serial conversion module and the serial-parallel conversion module through videos, and the time sequence instruction information comprises camera clock frequency, synchronous parameters and frame frequency information;
the serial-parallel conversion module is used for performing serial-parallel conversion on the serial Data and demodulating a synchronous clock signal CLK4, a first video Data1, a second video Data2 and a third video Data3 which are line synchronous, field synchronous and Data effective synchronous and parallel;
the time sequence recovery module is used for generating line synchronization, field synchronization, effective data synchronization and double-port RAM read enable which are the same as those of an original camera through phase-locked loops and camera video resolution, frame frequency and clock frequency information and outputting the line synchronization, the field synchronization, the effective data synchronization and the double-port RAM read enable to the video separation module;
the video separation module is used for generating double-port RAM write enable synchronously by demodulating lines, writing parallel first video Data1, second video Data2 and third video Data3 into a fourth line cache double-port RAM4, and synchronously separating separated video Data with the same frequency and time sequence as the three cameras from parallel video Data of the fourth line cache double-port RAM4 according to the double-port RAM read enable.
The data acquisition module performs clock domain crossing and time sequence processing on the acquired three paths of video data through RAM resources inside the FPGA, generates write enable according to the acquired three paths of video data respectively according to self-motion and field synchronization, and writes the respective input clocks into the 3-block line cache dual-port RAM in parallel.
The parallel output synchronization module generates a synchronous clock signal CLK4 according to a video output time sequence of the camera synchronization module, the synchronous clock signal CLK4 is the highest clock frequency of the parallel-serial conversion module, and is combined with a camera synchronization module output line synchronization trigger counter, a field synchronization trigger field counter and a data effective synchronization trigger data effective counter to delay 1 line time, so that a synchronous clock signal CLK4 is used for generating a time sequence for reading three double-port RAMs and an output synchronization time sequence, video data prestored in three-block line buffer double-port RAMs are read out, and the video data, the synchronous clock signal CLK4 and the output synchronization time sequence are output to the parallel-serial conversion module in parallel.
The parallel-serial conversion module respectively inputs video data read out by the three double-port RAMs to data input ends of parallel-serial conversion A (8bit), B (8bit) and C (8 bit); and the synchronous clock signal CLK4, the line synchronization, the field synchronization and the data effective synchronization are output to the parallel-serial conversion clock input end and the parallel-serial conversion synchronous input end, so that the serial encoding output of the parallel data is realized.
The time sequence recovery module obtains the video resolution, the frame frequency and the clock frequency of the original camera according to the instruction communication module, generates a clock frequency CLK5 with the same frequency as a pixel common-frequency clock CLK0 through a local phase-locked loop, and generates a line synchronization, field synchronization, data effective synchronization and double-port RAM read enable which are the same as the original camera by combining a line synchronization trigger line counter, a field synchronization trigger field counter and a data effective synchronization trigger data effective counter output by the serial-parallel conversion module through the clock frequency CLK5 and delaying 1 line time, and outputs the line synchronization, the field synchronization, the data effective synchronization and the double-port RAM read enable to the video separation module.
The video separation module synchronously generates double-port RAM write-enable through demodulation lines, parallel data output by the serial-parallel conversion module are written into a 24-bit double-port RAM, read-enable and clock frequency CLK5 output by the timing recovery module are connected to the double-port RAM, and three paths of separated video data with the same frequency and the same timing sequence as the three cameras are synchronously separated from the parallel video data of the 24-bit double-port RAM according to the video resolution, the clock frequency and the frame frequency of the original cameras.
Wherein, the first video Data1, the second video Data2 and the third video Data3 are all 8bit Data.
In the process of the parallel output synchronization module, the new video Data formed by the first video Data1, the second video Data2 and the third video Data3 is 24-bit Data.
Wherein the fourth cache dual port RAM4 is a 24-bit dual port RAM.
In addition, the present invention also provides a multi-source image low-delay parallel transmission method based on single-channel coaxiality, wherein the parallel transmission method is implemented based on the parallel transmission circuit, as shown in fig. 3, the method includes:
step 1: the camera synchronization module generates a video output time sequence of the three-way camera according to the pixel same-frequency clock CLK0, and outputs the video output time sequence to an external synchronous interface circuit of the three-way camera to realize the video output synchronization of the three-way camera; the same-frequency clock CLK0 and a first input clock CLK1, a second input clock CLK2 and a third input clock CLK3 of the three-way camera are same-frequency and different-phase;
step 2: the data acquisition module acquires videos of the three cameras, generates write enable according to self-motion and field synchronization of the acquired video data of the three cameras respectively, and writes the write enable into three lines of cache dual-port RAMs respectively according to respective input clock sequences; that is, the first video Data1, the second video Data2, and the third video Data3 respectively generate write enable in accordance with the sequence of the first input clock CLK1, the second input clock CLK2, and the third input clock CLK3, respectively, in accordance with the respective self-line and field synchronization, and respectively write into the first line cache dual-port RAM1, the second line cache dual-port RAM2, and the third line cache dual-port RAM 3; the three paths of video data have the same resolution and the same clock frequency, but the clock phases are different because the three paths of video data are generated by different crystal oscillators, namely, different sources with the same frequency;
and step 3: the parallel output synchronization module generates a synchronous clock signal CLK4 according to the video output time sequence of the camera synchronization module, generates a read enable signal and an output synchronization time sequence of three line buffer double-port RAMs by crossing a time domain by the synchronous clock signal CLK4, reads out video data pre-stored in the line buffer double-port RAMs, and outputs the video data to the parallel-serial conversion module together with the synchronous clock signal CLK4 and the output synchronization time sequence in parallel; the parallel output synchronization module reads three line buffer double-port RAMs by adopting a synchronization clock signal CLK4 to obtain first video Data1, second video Data2 and third video Data 3; the first video Data1, the second video Data2 and the third video Data3 form new video Data and are input to the parallel-serial conversion module; the video data output by the three-way camera is cached in three line cache double-port RAM, and is read by adopting a synchronous clock signal CLK4 of a higher clock; since only line buffering is performed, the synchronous clock signal CLK4 should be at least higher than the camera video frequency to ensure smooth output video;
and 4, step 4: the parallel-serial conversion module comprises three parallel-serial conversion data input ends, a parallel-serial conversion clock input end and a parallel-serial conversion synchronous input end; the three parallel-serial conversion Data input ends, namely a (8bit), a B (8bit) and a C (8bit) Data input end are respectively input by the first video Data1, the second video Data2 and the third video Data 3; the synchronous clock signal CLK4 is input to a parallel-serial conversion clock input end; line synchronization, field synchronization and data effective synchronization are output to a parallel-serial conversion synchronization input end; therefore, the parallel-serial conversion module realizes serial coding of three paths of parallel video data and outputs serial data; the serial data is transmitted to a serial-parallel conversion module through a coaxial line in a serial mode; the time sequence instruction information of the three cameras, including the clock frequency, the synchronous parameters and the frame frequency information of the cameras, is transmitted to the instruction communication module;
the instruction communication module realizes the coaxial bidirectional communication of the time sequence instruction information of the parallel-serial conversion module and the serial-parallel conversion module through video, and the time sequence instruction information comprises camera clock frequency, synchronous parameters and frame frequency information;
and 5: the serial-parallel conversion module carries out serial-parallel conversion on the serial Data and demodulates a synchronous clock signal CLK4, a first video Data1, a second video Data2 and a third video Data3 which are synchronous in line, field and Data valid synchronization and are parallel;
step 6: the time sequence recovery module generates line synchronization, field synchronization, effective data synchronization and double-port RAM read enable which are the same as those of an original camera through phase-locked loops and camera video resolution, frame frequency and clock frequency information, and outputs the line synchronization, the field synchronization, the effective data synchronization and the double-port RAM read enable to the video separation module;
and 7: the video separation module is used for generating double-port RAM write enable synchronously by demodulating lines, writing parallel first video Data1, second video Data2 and third video Data3 into a fourth line cache double-port RAM4, and synchronously separating separated video Data with the same frequency and time sequence as the three cameras from parallel video Data of the fourth line cache double-port RAM4 according to the double-port RAM read enable.
Example 1
In this embodiment, the resolution clock frequencies of the three cameras are the same, but the clock frequencies are the same, but the phases are different, because the crystal oscillators for generating the clocks are different, i.e., the same frequency and the same source are different.
In this embodiment, the camera synchronization module provides a synchronization timing sequence for the three cameras, and the synchronization timing sequence has the function of synchronizing signals such as line fields and the like of the three cameras, so that subsequent frame buffering can be avoided.
In this embodiment, the video data output by the camera is buffered in the dual port RAM, and is read with a higher clock CLK 4. Since only line buffering is performed, CLK4 should be at least higher than the camera video frequency to ensure smooth output video.
In this embodiment, three dual-port RAMs have a certain error due to the fact that the input video clocks have the same frequency but different phases, but the error generally does not exceed one clock, and the deviation caused between the three dual-port RAMs is eliminated by the dual-port RAM.
In this embodiment, the formed new 24-bit data passes through the parallel-to-serial conversion module, is serially transmitted through the coaxial line, and then passes through the serial-to-parallel conversion module. Meanwhile, timing information of the camera, such as synchronization information, frame frequency and the like, is transmitted through the command communication module to recover the timing.
In this embodiment, the parallel-to-serial conversion transmission is the prior art. The decoded 24-bit data is input to the dual port RAM and line buffered. And when reading, the time sequence recovery module generates a clock signal and a synchronous signal which are the same as those of the original camera through phase locking and information such as camera resolution, line frequency, frame frequency, clock frequency and the like, and recovers the time sequence of the original camera.
In this embodiment, after reading out the 24-bit data, each camera takes its respective 8 bits to form its own video data, and outputs the video data in combination with the time sequence to obtain its own video.
Example 2
The system comprises a camera synchronization module, a data processing module, a parallel output synchronization module, a parallel-serial conversion module, an instruction communication module, a serial-parallel conversion module, a time sequence recovery module and a video separation module;
the camera synchronization module is used for realizing video output synchronization of the 3-path camera;
the data acquisition module is used for generating write enable according to respective input clock (CLK1, CLK2 and CLK3) sequence and field synchronization respectively for the acquired 3 paths of video data, and respectively writing the write enable into 3 blocks of line cache dual-port RAMs, wherein the 3 paths of cameras have the same resolution and the same clock frequency, but have different clock phases due to different crystal oscillators;
the parallel output synchronization module generates three double-port RAM read enabling time sequences and output synchronization time sequences in a cross-time domain mode according to the output time sequences of the camera synchronization module, reads out the data of the double-port RAM pre-stored in the line cache, and outputs the data of the double-port RAM pre-stored in the line cache and the synchronization time sequences to the parallel-serial conversion module in parallel;
the parallel-serial conversion module is used for respectively outputting 3 line cache double-port RAM read data to parallel-serial conversion A (8bit), B (8bit) and C (8bit) data input ends, and outputting a pixel clock CLK4, line synchronization, field synchronization and data effective synchronization to the parallel-serial conversion clock input end and the synchronization input end to realize parallel data serial coding output;
the instruction communication module is used for realizing the video coaxial bidirectional communication of the parallel-serial conversion module and the serial-parallel conversion module, and comprises a camera clock frequency, a synchronous parameter, a frame frequency and the like;
and the serial-parallel conversion module is used for demodulating a pixel clock CLK4, line synchronization, field synchronization, data effective synchronization and parallel data A (8bit), B (8bit) and C (8bit) by serial data.
And the time sequence recovery module is used for generating line synchronization, field synchronization, effective data synchronization, double-port RAM read enable and the like which are the same as those of the original camera and outputting the line synchronization, the field synchronization, the effective data synchronization, the double-port RAM read enable and the like to the video separation module.
And the video separation module is used for synchronously separating the demodulated data into separated video data with the same time sequence as that of the 3 cameras through a 24-bit double-port RAM and a clock domain crossing mode.
Further, the camera synchronization module generates a video reading timing sequence for synchronizing the 3 cameras by using a clock CLK0 (having the same frequency and different phases with CLK1, CLK2 and CLK3) which is the same as the camera pixels, and outputs the video reading timing sequence to the external synchronization interface circuit of the 3 cameras;
further, the data acquisition module performs clock domain crossing and time sequence processing on the acquired 3 paths of video data through RAM resources inside the FPGA, and generates write enable and respective input clocks (CLK1, CLK2 and CLK3) for the acquired 3 paths of video data according to respective self and field synchronization respectively and writes the write enable and the respective input clocks into the 3 blocks of line cache dual-port RAMs in parallel.
Further, the parallel output synchronization module generates CLK4 (the highest clock frequency of the parallel-serial conversion module) by a phase-locked loop according to the output time sequence of the camera synchronization module, and delays 1 line time by combining a line synchronization trigger counter, a field synchronization trigger field counter and a data effective synchronization trigger data effective counter output by the camera synchronization module, generates a read three-dual-port RAM time sequence and an output synchronization time sequence by a clock CLK4, reads out prestored three-line cache dual-port RAM data, and outputs the data to the parallel-serial conversion module in parallel with the synchronization time sequence;
further, the parallel-serial conversion module outputs the read data of the three double-port RAMs to the data input ends of parallel-serial conversion A (8bit), B (8bit) and C (8bit), and the pixel clock CLK4, line synchronization, field synchronization and data effective synchronization are output to the input ends of the parallel-serial conversion clock and the synchronous input ends, so that serial encoding output of parallel data is realized;
the instruction communication module is used for realizing the bidirectional communication of the instructions of the parallel-serial conversion module and the serial-parallel conversion module, and comprises camera frequency, synchronous parameters and the like;
further, the serial-parallel conversion module demodulates the pixel clock CLK4, line synchronization, field synchronization, data effective synchronization and parallel data A (8bit), B (8bit) and C (8bit) from the serial data.
And the timing recovery module is used for obtaining the video resolution, the clock frequency and the frame frequency of the original camera according to the instruction communication module, generating a clock frequency CLK5 with the same frequency as that of CLK0 through a local phase-locked loop, outputting a line synchronization trigger counter, a field synchronization trigger field counter and a data effective synchronization trigger data effective counter by the CLK5 in combination with the serial-parallel conversion module, delaying 1 line time, generating the line synchronization, the field synchronization, the data effective synchronization, the double-port RAM read enable and the like which are the same as those of the original camera, and outputting the line synchronization, the field synchronization, the data effective synchronization, the double-port RAM read enable and the like to the video separation module.
And further, the video separation module synchronously generates a dual-port RAM write enable according to a demodulation line, writes parallel data output by the serial-parallel conversion module into a 24-bit RAM, connects a read enable and a CLK5 output by the time sequence recovery module to a dual-port RAM B end to obtain the video resolution, clock frequency and frame frequency of the original camera, and recovers the video into 3 paths of separated videos which have the same frequency and sequence as the camera.
Example 3
The embodiment provides a multi-source image low-delay, wide-clock and parallel transmission circuit and method based on single-path coaxiality. The camera external synchronization interface circuit comprises a camera external synchronization interface circuit, a programmable logic sending processing circuit, a parallel-serial conversion interface circuit, a serial-parallel conversion interface circuit and a programmable logic receiving processing circuit. The camera interface circuit is connected with the programmable logic sending processing circuit, the programmable logic sending processing circuit is connected with the parallel-serial conversion interface circuit, the parallel-serial conversion interface circuit is connected with the serial-parallel conversion interface circuit, and the serial-parallel conversion interface circuit is connected with the programmable logic sending processing circuit.
The circuit and the method for the multi-source image low-delay, wide-clock and parallel transmission based on the single-path coaxiality generate the same external synchronous time sequence signals through the unified time sequence circuit, and externally synchronize the three cameras to enable the cameras to have the same line field reading time sequence signals.
According to the multi-source image low-delay, wide-clock and parallel transmission circuit and method based on single-path coaxiality, data of three cameras are respectively written into the dual-port RAM in the FPGA, time sequence recombination is carried out through low-delay line and field synchronization and clock frequency raising, and the problems that multiple cameras span different clock domains and the cameras are not matched with parallel-serial conversion clocks are solved.
The multi-source image low-delay, wide-clock and parallel transmission circuit and method based on single-path coaxiality are characterized in that an instruction communication module transmits camera time sequence information to a time sequence recovery module through a coaxial cable, the time sequence recovery module utilizes a phase-locked loop PLL and a counter in a field programmable gate array FPGA to generate 3 paths of separated videos which are recovered from the time sequence with the same resolution, clock frequency and frame frequency as a camera, and video data transmission of the 3 paths of cameras is achieved;
according to the multi-source image low-delay, wide-clock and parallel transmission circuit and method based on single-path coaxiality, data of three cameras are respectively written into a double-port RAM used for line caching in an FPGA, then parallel data output by a serial-parallel conversion module are written into a 24-bit RAM used for line caching, data delay is controlled to be two lines of maximum duration, caching of a whole frame image is not carried out, video transmission delay is reduced, and real-time transmission is achieved.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The multi-source image low-delay parallel transmission circuit based on single-path coaxiality is characterized by comprising the following components: the system comprises a camera synchronization module, a data processing module, a parallel output synchronization module, a parallel-serial conversion module, an instruction communication module, a serial-parallel conversion module, a time sequence recovery module and a video separation module;
the camera synchronization module is used for generating a video output time sequence of the three-way camera according to the pixel same-frequency clock CLK0, outputting the video output time sequence to an external synchronization interface circuit of the three-way camera, and realizing the video output synchronization of the three-way camera; the same-frequency clock CLK0 and a first input clock CLK1, a second input clock CLK2 and a third input clock CLK3 of the three-way camera are same-frequency and different-phase;
the data acquisition module is used for acquiring videos of the three-path camera, generating write enable for the acquired three-path video data according to respective self-motion and field synchronization respectively, and writing the write enable into three lines of cache dual-port RAMs respectively and correspondingly according to respective input clock sequences; that is, the first video Data1, the second video Data2, and the third video Data3 respectively generate write enable in accordance with the sequence of the first input clock CLK1, the second input clock CLK2, and the third input clock CLK3, respectively, in accordance with the respective self-line and field synchronization, and respectively write into the first line cache dual-port RAM1, the second line cache dual-port RAM2, and the third line cache dual-port RAM 3; the three paths of video data have the same resolution and the same clock frequency, but the clock phases are different because the three paths of video data are generated by different crystal oscillators, namely, different sources with the same frequency;
the parallel output synchronization module is used for generating a synchronous clock signal CLK4 according to the video output time sequence of the camera synchronization module, generating a read enable signal and an output synchronization time sequence of the three line buffer double-port RAMs by the synchronous clock signal CLK4 across a time domain, reading out video data pre-stored in the line buffer double-port RAMs, and outputting the video data to the parallel-serial conversion module in parallel with the synchronous clock signal CLK4 and the output synchronization time sequence; the parallel output synchronization module reads three line buffer double-port RAMs by adopting a synchronization clock signal CLK4 to obtain first video Data1, second video Data2 and third video Data 3; the first video Data1, the second video Data2 and the third video Data3 form new video Data and are input to the parallel-serial conversion module; the video data output by the three-way camera is cached in three line cache double-port RAM, and is read by adopting a synchronous clock signal CLK4 of a higher clock; since only line buffering is performed, the synchronous clock signal CLK4 should be at least higher than the camera video frequency to ensure smooth output video;
the parallel-serial conversion module comprises three parallel-serial conversion data input ends, a parallel-serial conversion clock input end and a parallel-serial conversion synchronous input end; the three parallel-serial conversion Data input ends, namely a parallel-serial conversion A, B, C Data input end, are respectively input by the first video Data1, the second video Data2 and the third video Data 3; the synchronous clock signal CLK4 is input to a parallel-serial conversion clock input end; line synchronization, field synchronization and data effective synchronization are output to a parallel-serial conversion synchronization input end; therefore, the parallel-serial conversion module realizes serial coding of three paths of parallel video data and outputs serial data; the serial data is transmitted to a serial-parallel conversion module through a coaxial line in a serial mode; the time sequence instruction information of the three cameras, including the clock frequency, the synchronous parameters and the frame frequency information of the cameras, is transmitted to the instruction communication module;
the instruction communication module is used for realizing the coaxial bidirectional communication of the time sequence instruction information of the parallel-serial conversion module and the serial-parallel conversion module through videos, and the time sequence instruction information comprises camera clock frequency, synchronous parameters and frame frequency information;
the serial-parallel conversion module is used for performing serial-parallel conversion on the serial Data and demodulating a synchronous clock signal CLK4, a first video Data1, a second video Data2 and a third video Data3 which are line synchronous, field synchronous and Data effective synchronous and parallel;
the time sequence recovery module is used for generating line synchronization, field synchronization, effective data synchronization and double-port RAM read enable which are the same as those of an original camera through phase-locked loops and camera video resolution, frame frequency and clock frequency information and outputting the line synchronization, the field synchronization, the effective data synchronization and the double-port RAM read enable to the video separation module;
the video separation module is used for generating double-port RAM write enable synchronously by demodulating lines, writing parallel first video Data1, second video Data2 and third video Data3 into a fourth line cache double-port RAM4, and synchronously separating separated video Data with the same frequency and time sequence as the three cameras from parallel video Data of the fourth line cache double-port RAM4 according to the double-port RAM read enable.
2. The single-channel coaxial multi-source image low-delay parallel transmission circuit based on claim 1, wherein the data acquisition module performs clock domain crossing and time sequence processing on the acquired three-channel video data through an internal RAM resource of the FPGA, and generates write enable according to the self-motion and field synchronization of the acquired three-channel video data respectively, and writes the respective input clocks into 3 blocks of line cache dual-port RAMs in parallel.
3. The single-channel coaxial based multi-source image low-delay parallel transmission circuit as claimed in claim 1, wherein the parallel output synchronization module generates a synchronous clock signal CLK4 according to the video output timing of the camera synchronization module, the phase-locked loop generates the synchronous clock signal CLK4 being the highest clock frequency of the parallel-to-serial conversion module, and the synchronous clock signal CLK4 is used to generate the read three dual-port RAM timing and the output synchronization timing by combining the output line synchronization trigger counter, the field synchronization trigger field counter, the data valid synchronization trigger data valid counter of the camera synchronization module and delaying 1 line time by the synchronous clock signal CLK4, read the video data pre-stored in the three line buffer dual-port RAMs, and output the video data to the parallel-to-serial conversion module in parallel with the synchronous clock signal CLK4 and the output synchronization timing.
4. The single-channel coaxial-based multi-source image low-delay parallel transmission circuit as claimed in claim 1, wherein the parallel-serial conversion module respectively inputs video data read out by three dual-port RAMs to a data input end of parallel-serial conversion A, B, C; and the synchronous clock signal CLK4, the line synchronization, the field synchronization and the data effective synchronization are output to the parallel-serial conversion clock input end and the parallel-serial conversion synchronous input end, so that the serial encoding output of the parallel data is realized.
5. The single-channel coaxial multi-source image low-delay parallel transmission circuit based on claim 1 is characterized in that the timing recovery module obtains video resolution, frame frequency and clock frequency of an original camera according to the instruction communication module, generates a clock frequency CLK5 with the same frequency as a pixel common-frequency clock CLK0 through a local phase-locked loop, and generates line synchronization, field synchronization, data valid synchronization and dual-port RAM read enable which are the same as the original camera by combining a line synchronization trigger line counter, a field synchronization trigger field counter and a data valid synchronization trigger data valid counter output by the serial-parallel conversion module through the clock frequency CLK5 and delaying 1 line time, and outputs the line synchronization, the field synchronization, the data valid synchronization and the dual-port RAM read enable to the video separation module.
6. The single-channel coaxial multi-source image low-delay parallel transmission circuit based on claim 5 is characterized in that the video separation module synchronously generates double-port RAM write enable through demodulation, parallel data output by the serial-parallel conversion module are written into a 24-bit double-port RAM, the read enable and clock frequency CLK5 output by the timing recovery module are connected to the double-port RAM, and three paths of separated video data with the same frequency and the same timing as three cameras are synchronously separated from the parallel video data of the 24-bit double-port RAM according to the video resolution, the clock frequency and the frame frequency of the original camera.
7. The single-channel coaxial based multi-source image low-latency parallel transmission circuit as claimed in claim 1, wherein the first video Data1, the second video Data2 and the third video Data3 are all 8bit Data.
8. The single-channel coaxial-based multi-source image low-latency parallel transmission circuit as claimed in claim 1, wherein during operation of the parallel output synchronization module, new video Data formed by the first video Data1, the second video Data2 and the third video Data3 are 24-bit Data.
9. The single-channel coaxial based multi-source image low-delay parallel transmission circuit as claimed in claim 1, wherein the fourth row buffer dual-port RAM4 is a 24-bit dual-port RAM.
10. A multi-source image low-delay parallel transmission method based on one-way coaxiality, wherein the parallel transmission method is implemented based on the parallel transmission circuit of any one of claims 1 to 9, and the method comprises the following steps:
step 1: the camera synchronization module generates a video output time sequence of the three-way camera according to the pixel same-frequency clock CLK0, and outputs the video output time sequence to an external synchronous interface circuit of the three-way camera to realize the video output synchronization of the three-way camera; the same-frequency clock CLK0 and a first input clock CLK1, a second input clock CLK2 and a third input clock CLK3 of the three-way camera are same-frequency and different-phase;
step 2: the data acquisition module acquires videos of the three cameras, generates write enable according to self-motion and field synchronization of the acquired video data of the three cameras respectively, and writes the write enable into three lines of cache dual-port RAMs respectively according to respective input clock sequences; that is, the first video Data1, the second video Data2, and the third video Data3 respectively generate write enable in accordance with the sequence of the first input clock CLK1, the second input clock CLK2, and the third input clock CLK3, respectively, in accordance with the respective self-line and field synchronization, and respectively write into the first line cache dual-port RAM1, the second line cache dual-port RAM2, and the third line cache dual-port RAM 3; the three paths of video data have the same resolution and the same clock frequency, but the clock phases are different because the three paths of video data are generated by different crystal oscillators, namely, different sources with the same frequency;
and step 3: the parallel output synchronization module generates a synchronous clock signal CLK4 according to the video output time sequence of the camera synchronization module, generates a read enable signal and an output synchronization time sequence of three line buffer double-port RAMs by crossing a time domain by the synchronous clock signal CLK4, reads out video data pre-stored in the line buffer double-port RAMs, and outputs the video data to the parallel-serial conversion module together with the synchronous clock signal CLK4 and the output synchronization time sequence in parallel; the parallel output synchronization module reads three line buffer double-port RAMs by adopting a synchronization clock signal CLK4 to obtain first video Data1, second video Data2 and third video Data 3; the first video Data1, the second video Data2 and the third video Data3 form new video Data and are input to the parallel-serial conversion module; the video data output by the three-way camera is cached in three line cache double-port RAM, and is read by adopting a synchronous clock signal CLK4 of a higher clock; since only line buffering is performed, the synchronous clock signal CLK4 should be at least higher than the camera video frequency to ensure smooth output video;
and 4, step 4: the parallel-serial conversion module comprises three parallel-serial conversion data input ends, a parallel-serial conversion clock input end and a parallel-serial conversion synchronous input end; the three parallel-serial conversion Data input ends, namely a parallel-serial conversion A, B, C Data input end, are respectively input by the first video Data1, the second video Data2 and the third video Data 3; the synchronous clock signal CLK4 is input to a parallel-serial conversion clock input end; line synchronization, field synchronization and data effective synchronization are output to a parallel-serial conversion synchronization input end; therefore, the parallel-serial conversion module realizes serial coding of three paths of parallel video data and outputs serial data; the serial data is transmitted to a serial-parallel conversion module through a coaxial line in a serial mode; the time sequence instruction information of the three cameras, including the clock frequency, the synchronous parameters and the frame frequency information of the cameras, is transmitted to the instruction communication module;
the instruction communication module realizes the coaxial bidirectional communication of the time sequence instruction information of the parallel-serial conversion module and the serial-parallel conversion module through video, and the time sequence instruction information comprises camera clock frequency, synchronous parameters and frame frequency information;
and 5: the serial-parallel conversion module carries out serial-parallel conversion on the serial Data and demodulates a synchronous clock signal CLK4, a first video Data1, a second video Data2 and a third video Data3 which are synchronous in line, field and Data valid synchronization and are parallel;
step 6: the time sequence recovery module generates line synchronization, field synchronization, effective data synchronization and double-port RAM read enable which are the same as those of an original camera through phase-locked loops and camera video resolution, frame frequency and clock frequency information, and outputs the line synchronization, the field synchronization, the effective data synchronization and the double-port RAM read enable to the video separation module;
and 7: the video separation module is used for generating double-port RAM write enable synchronously by demodulating lines, writing parallel first video Data1, second video Data2 and third video Data3 into a fourth line cache double-port RAM4, and synchronously separating separated video Data with the same frequency and time sequence as the three cameras from parallel video Data of the fourth line cache double-port RAM4 according to the double-port RAM read enable.
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| CN115061967A (en) * | 2022-06-30 | 2022-09-16 | 重庆秦嵩科技有限公司 | Method for reducing interface clock by using homemade FPGA (field programmable Gate array) based camera link image compression |
| CN115061967B (en) * | 2022-06-30 | 2023-06-23 | 重庆秦嵩科技有限公司 | Method for reducing interface clock by adopting camera link image compression based on domestic FPGA |
| CN115514952A (en) * | 2022-09-02 | 2022-12-23 | 海南视联通信技术有限公司 | Synchronous detection method and device for multi-channel image data |
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