JP2009267969A - Imaging device and method for processing signal therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To concurrently process a plurality of pixel signals output from an image sensor in parallel. <P>SOLUTION: A synchronization code that synchronizes with a horizontal synchronization signal is added to a pixel signal input to each of a plurality of parallel-serial converters 109, 110 that are provided so as to correspond to each of the plurality of pixel signals and a parallel pixel signal is converted into a serial pixel signal by these plurality of parallel-serial converters in synchronization with a first clock signal. The synchronization code is detected from the converted serial pixel signal and the plurality of serial pixel signals are converted into the parallel pixel signal by a plurality of serial-parallel converters 112, 114. The synchronization between the plurality of parallel pixel signals output by the plurality of serial-parallel converters 112, 114 is adjusted (116) and multi-level image data corresponding to the plurality of pixel signals are output. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for processing a plurality of pixel signals output in parallel from an image sensor in parallel.

  In recent years, the resolution of an image taken with a digital still camera has rapidly increased, and accordingly, high-speed reading of pixel data from an image sensor (image sensor) has been demanded. An image sensor that can output a plurality of analog data in parallel is used as a sensor that can cope with such high-speed pixel data reading.

  Further, as a method of transferring digital data obtained by A / D converting analog data, a method of serializing data by parallel serial conversion and transmitting the data at high speed is known. By adopting such a data transfer method, it is possible to A / D convert each of a plurality of analog data output from the above-described image sensor, and to convert the digital data into parallel serial data and transmit it as a plurality of serial data. Conceivable. In this case, since a plurality of serial data are transmitted in parallel, it is important to synchronize each serial data.

A method related to this synchronization is described in Patent Document 1. According to Document 1, a synchronization code is added to serial data output from a parallel-serial converter and transferred. The receiving side detects the synchronization code and synchronizes each serial data based on the detection timing of the synchronization code detected between different systems.
Japanese Patent Laid-Open No. 10-112706

  In the conventional method described above, serial data converted by the parallel-serial converter is temporarily stored in a buffer, and is read and transmitted in synchronization between the two systems. However, in the parallel-serial converter, a PLL circuit is used to stabilize the frequency of the serial clock so that the serial clock frequency used in each parallel-serial converter is the same. Therefore, when a plurality of parallel-serial converters are used, the PLL circuits are different, so that the serial clocks have the same frequency even if they have the same frequency. On the time axis, there is a possibility that the frequency is not exactly the same locally due to the influence of the jitter of the PLL circuit. In the case of a configuration in which a single PLL is shared by a plurality of parallel-serial converters, when the frequency of the output clock of the PLL circuit increases, the timing of the clock signal when the plurality of parallel-serial converters are physically different chips It becomes difficult to satisfy the restrictions, and restrictions such as arrangement of a plurality of chips on the substrate become severe.

  An object of the present invention is to solve such conventional problems.

  According to the imaging apparatus according to an aspect of the present invention, it is possible to provide a technique that can reliably synchronize multi-value data obtained by receiving each output of a plurality of parallel-serial converters and performing serial-parallel conversion.

In order to achieve the above object, an imaging apparatus according to one embodiment of the present invention includes the following arrangement. That is,
An oscillator that generates a reference clock; and
Synchronization signal generating means for generating horizontal and vertical synchronization signals in synchronization with the reference clock;
Timing signal generating means for generating a timing signal including a first clock signal and a driving signal in synchronization with the reference clock and the horizontal and vertical synchronization signals;
An image sensor that is driven by the drive signal and outputs an image signal representing a captured image as a plurality of pixel signals;
A plurality of parallel-serial conversion means provided corresponding to each of the plurality of pixel signals and converting a parallel pixel signal into a serial pixel signal in synchronization with the first clock signal;
Synchronization code adding means for adding a synchronization code synchronized with the horizontal synchronization signal to the pixel signal input to each of the plurality of parallel serial conversion means;
A plurality of detection means for detecting the synchronization code from the serial pixel signal output from each of the plurality of parallel-serial conversion means;
A plurality of serial / parallel conversion means provided corresponding to each of the plurality of parallel / serial conversion means, for converting the serial pixel signals of the plurality of parallel / serial conversion means into parallel pixel signals;
Adjusting means for adjusting the synchronization of the plurality of parallel pixel signals output from the plurality of serial-parallel conversion means, and outputting multi-value image data corresponding to the plurality of pixel signals, To do.

In order to achieve the above object, a signal processing method in an imaging apparatus according to an aspect of the present invention includes the following steps. That is,
An oscillator that generates a reference clock; a synchronization signal generator that generates horizontal and vertical synchronization signals in synchronization with the reference clock; and a first clock signal that is driven in synchronization with the reference clock and horizontal and vertical synchronization signals A signal processing method in an imaging apparatus, comprising: a timing signal generator that generates a timing signal including a signal; and an imaging element that is driven by the driving signal and outputs an image signal representing a captured image as a plurality of pixel signals. And
A step of converting a parallel pixel signal into a serial pixel signal in synchronization with the first clock signal by a plurality of parallel-serial converters provided corresponding to each of the plurality of pixel signals;
Adding a synchronization code synchronized with the horizontal synchronization signal to the pixel signal input to each of the plurality of parallel-serial converters;
Detecting the synchronization code from the serial pixel signal output from each of the plurality of parallel-serial converters;
Converting each of the serial pixel signals of the plurality of parallel serial converters into parallel pixel signals by a plurality of serial / parallel converters provided corresponding to each of the plurality of parallel serial converters;
An adjustment step of adjusting the synchronization of the plurality of parallel pixel signals output from the plurality of serial-parallel converters, and outputting multi-value image data corresponding to the plurality of pixel signals;
It is characterized by having.

  According to the present invention, there is an effect that multi-value data obtained by receiving each output of a plurality of parallel-serial converters and performing serial-parallel conversion can be reliably synchronized.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the present embodiments are essential to the solution means of the present invention. Not exclusively.

[Embodiment 1]
FIG. 1 is a block diagram illustrating a configuration of a data transfer circuit that transfers image data output from an image sensor in synchronization in the image pickup apparatus according to the embodiment of the present invention.

  In FIG. 1, an oscillator 101 outputs a reference clock serving as a reference for operation. Based on the reference clock output from the oscillator 101, each unit described later operates. A synchronization signal generator (SSG) 108 outputs a horizontal synchronization signal HD and a vertical synchronization signal VD in synchronization with the reference clock. The timing signal generator (TG) 102 generates a driving pulse signal for driving the sensor (imaging device) 103 based on the synchronization signals HD and VD supplied from the SSG 108. The TG 102 also outputs a clock signal (first clock signal) for operating the A / D converters (ADC) 104 and 105, the synchronization code adders 106 and 107, and the parallel-serial converters 109 and 110. This clock signal is a clock obtained by delaying the reference clock output from the oscillator 101. This delay is performed in order to obtain a good sampling timing when the output of the sensor 103 is converted into a digital signal by the A / D converters 104 and 105.

  The sensor 103 is an image sensor composed of, for example, a CCD or a CMOS. The sensor 103 includes therein a light receiving element such as a photodiode that performs photoelectric conversion, a transfer path that sequentially outputs pixel signals obtained by the light receiving element in accordance with a drive pulse (drive signal) supplied from the TG 102, An amplifier for amplifying the pixel signal is included.

  The sensor 103 according to the present embodiment includes a plurality of systems that output captured image information as analog signals. In FIG. 1, two analog signals are output, and the analog signals are output. The number of systems is not limited to two.

  Each of the A / D converters 104 and 105 samples the analog signal output from the sensor 103 in accordance with the sample hold timing signal supplied from the TG 102, converts it to a digital signal, and outputs it. Here, each of the A / D converters 104 and 105 converts it into a 14-bit digital signal.

  The synchronization code adders 106 and 107 add synchronization codes to the digital signals output from the corresponding A / D converters 104 and 105, respectively. This synchronization code is added every time the horizontal synchronization signal HD is output. The parallel / serial converters 109 and 110 respectively convert parallel data output from the corresponding synchronization code adders 106 and 107 into serial data. The outputs of the parallel / serial converters 109 and 110 are supplied to the synchronization code detectors 111 and 113 and the serial / parallel converters 112 and 114 via a substrate and a cable. Here, the serial data output from the parallel / serial converter 109 is supplied to the synchronization code detector 111 and the serial / parallel converter 112. The serial data output from the parallel / serial converter 110 is supplied to the synchronization code detector 113 and the serial / parallel converter 114.

  The synchronization code detectors 111 and 113 each detect a synchronization code included in the input serial data. When the synchronization code is detected, a timing signal is output to inform the corresponding serial / parallel converters 112 and 114 of the timing for outputting the parallel / parallel converted data. Each of the serial / parallel converters 112 and 114 receives serial data and stores it in an internal shift register. The serial data thus stored is output as parallel data for each predetermined word length in accordance with the timing signals supplied from the corresponding synchronous code detectors 111 and 113. The data output from the serial / parallel converter 112 is indicated by data A, and the data output from the serial / parallel converter 114 is indicated by data B. At this time, when data corresponding to the synchronization code is output, a synchronization flag (synchronization flags A and B) indicating that the output data is a synchronization code is also output. Further, clocks (clocks A and B) restored from the serial data are also output.

  The clock transfer unit 115 transfers the data B and the synchronization flag B output from the serial / parallel converter 114 to the clock A output from the serial / parallel converter 112 and outputs them as the data C and the synchronization flag C, respectively. Here, the clock transfer unit 115 is based on the clock A, but the present invention is not limited to this. For example, when there are more than two signal systems, a predetermined clock among them may be used as a reference. The delay adjuster 116 adjusts the phase in units of clocks between the two systems of data based on the synchronization flag A output from the serial / parallel converter 112 and the synchronization flag C output from the clock transfer unit 115. In this way, the phase of the two systems of data A and C is adjusted by the delay adjuster 116 and output to the trimming circuit 117 together with the synchronization flag D as synchronized data D (multi-valued image data). The trimming circuit 117 receives the horizontal synchronization signal VD and the synchronization flag D output from the SSG 108, and specifies the position of data with respect to the horizontal synchronization signal HD and the vertical synchronization signal VD. Then, a necessary image area is extracted from the subsequent image signal processing unit (not shown), and data E and an effective flag indicating the effective area are output.

  Based on the configuration of FIG. 1 described above, an operation when acquiring one frame of image data will be described.

  The two analog signals output from the sensor 103 are converted into digital signals by the A / D converters 104 and 105, respectively. Next, the synchronization code adders 106 and 107 add a synchronization code to the digital signal for each horizontal synchronization signal HD. The parallel-serial converters 109 and 110 perform parallel-serial conversion on the data thus added with the synchronization code and output the data. The synchronization code detectors 111 and 113 generate a timing signal for detecting the synchronization code included in the serial data output from the corresponding parallel / serial converters 109 and 110 and performing serial / parallel conversion. As a result, the serial / parallel converters 112 and 114 receive the serial data output from the corresponding parallel / serial converters 109 and 110, perform serial / parallel conversion, and output a synchronization flag and a clock restored from the serial data. The clock transfer unit 115 outputs the serial data output from the serial / parallel converter 114 to the delay adjuster 116 as data C transferred to the output clock of the serial / parallel converter 112. Thereby, the input signal of the delay adjuster 116 becomes a signal synchronized with a single clock. The delay adjuster 116 adjusts the delay amount of the output data based on the shift of the synchronization flag between the two systems. Thus, in the data D output from the delay adjuster 116, the synchronization relationship in the digital data output from the A / D converters 104 and 105 is restored. The trimming circuit 117 restores the positional relationship of the data with respect to the horizontal and vertical synchronization signals HD and VD based on the vertical synchronization signal VD and the synchronization flag output from the delay adjuster 116, and is necessary for subsequent processing. A valid flag is attached to each part and output.

  Through the above operation, one frame of image data synchronized with the horizontal and vertical synchronization signals HD and VD output from the SSG 108 can be extracted.

  Next, the details of the operation of each unit unique to this embodiment will be described.

[Synchronization code adders 106 and 107]
FIG. 2 is a diagram for explaining the synchronization code provision timing in the synchronization code adder according to the present embodiment. In FIG. 2, the clock is a clock signal that defines the sampling timing of the A / D converters 104 and 105.

  FIG. 2A shows an example of adding a synchronization code when the horizontal synchronization signal HD output from the SSG 108 indicates the horizontal synchronization timing at the falling edge. When the falling edge of the HD signal is detected, addition of a synchronization code is started, and at other timings, input data is delayed by one cycle and output as output data. Here, the synchronization code is composed of synchronization codes 1 to 3. This will be described in detail later.

  FIG. 2B shows the synchronization code at a timing different from that in FIG. 2A when a valid video signal (Xc in FIG. 2B) is output at the falling timing of the HD synchronization signal. An additional example is shown. In FIG. 2B, the addition of the synchronization code is started with a delay of one cycle from the falling edge of the HD synchronization signal. Note that the input data is delayed by one cycle and output as output data at other timings as in FIG. 2A. Note that the delay amount in FIG. 2B may be for a plurality of cycles so that the effective video signal (Xc) and the synchronization code do not overlap.

  What is important here is that there is a fixed delay relationship between the fall of the horizontal synchronization signal HD and the timing of adding the synchronization code. The video signal cannot be sent at the timing of adding the synchronization code. For this reason, the synchronization code is added at a timing delayed for a fixed period from the falling edge of the HD synchronization signal in a timely manner so that the video signal is added during the horizontal blanking period or the like.

  In FIG. 2, the synchronization code is given in three cycles. This is because the phase of data at the time of serial / parallel conversion can be detected by the synchronization code.

  Next, the synchronization code will be described.

  For example, when parallel-serial conversion of 16-bit parallel data is performed, data “0x0000” and “0xFFFF” are prohibited in the effective image signal area. “0x0000” indicates 16-bit data of all “0” in hexadecimal code, and “0xFFFF” indicates 16-bit data of all “1” in hexadecimal code. Then, {synchronization code 1, synchronization code 2, synchronization code 3} is a code composed of a sequence of data such as {0x0000, 0x0000, 0xFFFF}. Thereby, in the effective image signal area, 32 bits “0” does not continue like “0x0000, 0x0000”, so that the synchronization code can be detected by “0x0000, 0x0000”. The phase of the synchronization code in the serial data can be detected by the subsequent “0xFFFF”.

  When the A / D converters 104 and 105 generate 12-bit digital data, the synchronization code adders 106 and 107 add 4-bit data to the 12-bit digital data and perform serial / parallel conversion. Extends to 16-bit word length.

  FIG. 3A to FIG. 3C are diagrams for explaining the arrangement of the valid data portion included in the serial-parallel converted data.

  FIG. 3A shows an example in which 12-bit data is output from the A / D converters 104 and 105 when the word length for serial / parallel conversion is 16 bits. In FIG. 3A, “0” is added to the lower 4 bits.

  FIG. 3B shows a case where the word length for serial / parallel conversion is 16 bits and the word length of data output from the A / D converters 104 and 105 is 14 bits. In this case, “0” is added to the lower 2 bits.

  FIG. 3C shows a case where the word length for serial / parallel conversion is 16 bits and the word length of data output from the A / D converters 104 and 105 is 10 bits. In this case, “0” is added to the lower 6 bits.

  In this way, when serial / parallel conversion is performed, even if the bit length of data input from the A / D converter is different from the bit length for serial / parallel conversion, the difference between them can be adjusted.

[Parallel-serial converter 109, 110]
The parallel-serial converters 109 and 110 according to the present embodiment input, for example, 16-bit parallel data, convert it into serial data, and output it.

  FIG. 4 is a timing chart for explaining the timing of parallel-serial conversion by the parallel-serial converters 109 and 110 according to the embodiment.

  Here, the serial clock has a period that is 1/16 times the period P of one clock (parallel clock) of parallel data. That is, the serial clock has a frequency 16 times that of the parallel clock. Here, after inputting 16-bit parallel data X, the parallel data X is converted into 16-bit serial data (X [0], X [1],. X [14], X [15]).

  A PLL (Phase Locked Loop) circuit included in each of the parallel-serial converters 109 and 110 receives this parallel clock and multiplies it by 16 to generate this serial clock. Here, a serial clock is generated by two different PLL circuits. Therefore, the serial clocks used in the parallel-serial conversion of the parallel-serial converter 109 and the parallel-serial converter 110 have the same frequency, but the synchronization relationship is lost. On the time axis, there is a possibility that the frequency is not exactly the same locally due to the influence of the jitter of the PLL circuit. Therefore, the parallel-serial converters 109 and 110 output the serial data and the serial clock as a pair.

[Synchronization code detectors 111 and 113]
The synchronization code detectors 111 and 113 operate based on the serial clocks output from the corresponding parallel-serial converters 109 and 110, respectively, and detect the aforementioned synchronization code. The synchronization code detected here is, for example, a sequence of data such as {synchronization code 1, synchronization code 2, synchronization code 3} = {0x0000, 0x0000, 0xFFFF}. Therefore, when it is detected that “0” is consecutive 32 bits such as “0x0000, 0x0000” and subsequently “0xFFFF” is confirmed, the synchronization code and its phase included in the serial data can be detected. When the synchronization code is detected in this way, the synchronization code detectors 111 and 113 notify the corresponding serial / parallel converters 112 and 114, respectively.

[Serial parallel converter 112, 114]
The serial / parallel converters 112 and 114 receive the serial clock and serial data output from the corresponding parallel / serial converters 109 and 110, respectively. Then, the serial data is stored in a shift register (not shown) of each serial-parallel converter 112, 114. And the phase which takes out parallel data from a shift register is determined according to the timing which notified that the corresponding synchronous code detectors 111 and 113 detected the synchronous code. The parallel data is extracted every 16 cycles of the serial clock. For this reason, a clock obtained by dividing the serial clock by 16 can be used as a clock for parallel data (parallel clock), and parallel data obtained by serial-parallel conversion is latched and output by this parallel clock.

  The word length output by these serial / parallel converters 112 and 114 is an effective word length. For example, when 12-bit valid image data is included in 16-bit data, only the 12-bit portion is output. That is, in the case of FIG. 3A described above, the process of removing the lower 4 bits “0” is performed. In the case of FIG. 3B, processing such as removing the lower 2 bits is executed.

  The serial / parallel converters 112 and 114 notify that the corresponding synchronization code detectors 111 and 113 detect the synchronization code, and then set “1” as the synchronization flag in synchronization with the parallel data that is output first. Output. In other cases, “0” is output as the synchronization flag. The output data of the serial / parallel converter 112 is shown in FIG. 1 as data A, the synchronization flag as the synchronization flag A, and the output parallel clock as the clock A. Further, FIG. 1 shows the output parallel data of the serial-parallel converter 114 as data B, the output synchronization flag as the synchronization flag B, and the output parallel clock as the clock B.

[Clock transfer device 115]
Clocks A and B output from the serial / parallel converters 112 and 114 are parallel clocks corresponding to 16 cycles of the serial clock input from the corresponding parallel / serial converters 109 and 110, respectively. As described above, each of the parallel-serial converters 109 and 110 generates a serial clock in each PLL circuit. Therefore, the clock A and the clock B have the same frequency but are not synchronized. On the time axis, there is a possibility that the frequency is not exactly the same locally due to the influence of the jitter of the PLL circuit. Therefore, the clock changer 115 absorbs the difference between these two parallel clocks.

  The configuration of the clock transfer unit 115 is composed of, for example, a FIFO in which a write clock and a read clock are input separately, and uses a dual port memory as disclosed in FIG. 2 of Japanese Patent Laid-Open No. 2001-222407. It is possible to configure. Therefore, the clock transfer unit 115 inputs the data B and the synchronization flag B in synchronization with the clock B, and outputs the data C and the synchronization flag C in synchronization with the clock A input from the serial / parallel converter 112.

  Note that the data input to or output from the clock changer 115 is indicated by data and a synchronization flag, but these are input / output as connected data without distinction. That is, in this embodiment, the data is handled as 17-bit data in which one bit of the synchronization flag is added to 16 bits of data.

[Delay adjuster 116]
Data (data A, synchronization flag A, data C, synchronization flag C) input to the delay adjuster 116 according to the present embodiment are all input in synchronization with the clock A.

  FIG. 5 is a block diagram showing the structure of delay adjuster 116 according to the present embodiment.

  In FIG. 5, reference numerals 501 to 504 denote delay elements for delaying input data A. Reference numerals 505 to 508 denote delay elements for delaying the input synchronization flag A. Reference numerals 509 to 516 denote delay elements for delaying the input data C. Reference numerals 517 to 524 denote delay elements for delaying the synchronization flag C. Here, these delay elements are composed of flip-flops, and each shifts input data in the right (output) direction in synchronization with the parallel clock.

  The decoder 525 inputs the outputs from the delay elements 517 to 524 and decodes them. The DFF with load (D type flip-flop) 526 latches the output (3-bit data) of the decoder 525 when the output of the delay element 508 becomes high level. The selector 527 selects one of the outputs of the delay elements 509 to 516 according to the 3-bit data output from the DFF 526 with load. Thus, the data C output from the selector 527 and the data A output from the delay element 504 are connected to form 32-bit data D, and the output of the delay element 508 becomes the output of the synchronization flag D.

  FIG. 6 is a diagram for explaining an example of decoding by the decoder 525 according to the present embodiment.

  In FIG. 6, dlyF1 to dlyF8 indicate the outputs of the delay elements 517 to 524, respectively. This decoding condition is based on the premise that the synchronization flag is not detected twice in 8 cycles of the parallel clock. Actually, as described with reference to FIG. 2, since the synchronization flag is added for each horizontal synchronization signal HD, the condition is sufficiently satisfied when the number of pixels of the image sensor 103 is considered.

  In other words, the decoding condition is that the synchronization flag C is valid, that is, the selector 527 selects one of the outputs of the delay elements 509 to 516 holding the data C input simultaneously with the synchronization flag “1”. is there. In FIG. 6, “-” indicates that the data is meaningless.

  As an example of the operation of the delay adjuster 116, consider a case where a valid synchronization flag C is input after three clocks of the parallel clock behind the valid synchronization flag A. In this case, when the valid flag is shifted and stored in the delay element 508, the DFF 526 with load latches the output of the decoder 525. At this time, since the output (dlyF1) of the delay element 517 is high level “1”, the output (dec-dly) of the decoder 525 is “0” from the logic table of FIG. As a result, the selector 527 selects the data latched by the delay element 509 that delayed the data C. The 16-bit data selected and output from the selector 527 and the 16-bit data output from the delay element 504 are concatenated and output as data D.

[Trimming circuit 117]
FIG. 7 is a block diagram showing an internal configuration of the trimming circuit 117 according to the present embodiment. It is assumed that area information REG_RH, REG_SH, REG_RV, and REG_SV indicating an effective image area is stored in a register or a memory.

  The trimming circuit 117 has an H counter 701 and a V counter 702, and takes out the area shown in FIG. 8 as an effective image area 801 by decoding the outputs of the counters 701 and 702. The effective image area 801 is extracted by attaching an effective flag to the data.

  Decoding of the output of the H counter 701 is performed by the comparators 703 and 704 and the reset priority set / reset DFF 707. The output of the V counter 702 is decoded by the comparators 705 and 706 and the reset priority set / reset DFF 708.

  A valid flag is obtained by ANDing the decoding result of the output of the H counter 701 and the decoding result of the output of the V counter 702 by an AND gate 709. The relationship between the region information REG_RH, REG_SH, REG_RV, REG_SV and the effective image region 801 in FIG. 7 is as shown in FIG.

  FIG. 8 is a diagram for explaining an effective image area in an image.

  In the figure, REG_SH indicates the value of the H counter 701 corresponding to the left end of the effective image area 801 and REG_RH corresponds to the right end of the effective image area 801. REG_SV indicates the value of the V counter 702 corresponding to the upper end of the effective image area 801, and REG_RV indicates the value of the V counter 702 corresponding to the lower end of the effective image area 801.

  The H counter 701 counts up every time the clock A is input, and is reset to “0” every time the synchronization flag D is input as “1”. The V counter 702 is driven by the clock A and counts up in a cycle in which the synchronization flag D is “1”. When the synchronization flag D becomes “1” at the falling edge of the vertical synchronization signal VD, it is reset to “0”. Here, the vertical synchronization signal VD is asynchronous with the clock A. For this reason, the reset priority set / reset DFF 712 is set by the output pulse of the falling edge detection circuit 711 of the output of the synchronizer 710 through the synchronizer 710 in which two DFFs of the clock A are connected. The V counter 702 is reset to “0” by a signal obtained by ANDing the output of the DFF 712 and the synchronization flag D by the AND gate 713. The DFF 712 is cleared by the output of the AND gate 713.

  By such an operation, as shown in FIG. 9, the V counter 702 increases by 1 every time the horizontal synchronizing signal HD is inputted in synchronization with the falling of the vertical synchronizing signal VD.

  FIG. 9 is a timing chart for explaining the operation of the V counter according to the present embodiment.

  Although the above description has been made on the case where the output of the sensor 103 is an analog signal of two systems, it can be similarly applied to the case of an imaging sensor having three or more output systems.

  As described above, according to the first embodiment, it is possible to reliably synchronize a plurality of image signals output from the image sensor.

  In addition, even when a plurality of image signals output from the image sensor are output as serial data, it is possible to provide an imaging apparatus capable of establishing synchronization of the image signals of the plurality of systems.

[Embodiment 2]
FIG. 10 is a block diagram showing a signal processing circuit of the image pickup apparatus according to Embodiment 2 of the present invention. Portions that are the same as those in FIG.

  In the second embodiment, a clock changer 901 is provided between the serial-parallel converter 112 and the delay adjuster 116, and an oscillator 902 and a clock selection circuit 903 are provided. It is different from 1).

  The clock selection circuit 903 selects any one of the clock A, the clock B, and the clock output from the oscillator 902. When the clock A is selected by the clock selection circuit 903, the clock changer 901 changes from the clock A to the clock A, and the clock changer 115 changes from the clock B to the clock A. Accordingly, the same operation as in the first embodiment is performed.

  Next, when the clock B is selected by the clock selection circuit 903, the clock changer 901 changes from clock A to clock B, and the clock changer 115 changes from clock B to clock B. Therefore, in the first embodiment, the upper and lower signal systems are merely replaced. In other words, the system from the A / D converter 104 to the serial / parallel converter 112 and the system from the A / D converter 105 to the serial / parallel converter 114 are merely interchanged. The same operation as in the first embodiment is performed.

  Next, when the clock signal (second clock signal) of the oscillator (clock generator) 902 is selected by the clock selection circuit 903, the clock changer 901 and the clock changer 115 change to the output clock of the oscillator 902. I do. Therefore, the signal processing circuit that operates in response to the outputs of the delay adjuster 116, the trimming circuit 117, and the trimming circuit 117, which are subsequent circuits, operates in synchronization with the output clock of the oscillator 902. Therefore, by setting the frequency of the oscillator 902 to a frequency more than twice the frequency of the reference clock, the image data in which two pixels are simultaneously input is serialized into one pixel in one cycle after the trimming circuit 117. Signal processing can be performed.

  As described above, by providing the two clock changers 901 and 115, the frequency of the clock processed in the trimming circuit 117 and later can be set to an arbitrary frequency. Then, by setting the arbitrary frequency to an integer multiple of the frequency of the reference clock, for example, the pixel data of the integral multiple can be processed in one cycle, so that the circuit scale can be reduced.

  Further, according to the second embodiment, since it is possible to absorb a shift due to clock skew or jitter between a plurality of parallel-serial converters, there is no need to share a PLL between the plurality of parallel-serial converters. The number of vessels can be easily increased.

  Further, according to the second embodiment, the clock frequency of the processing circuit subsequent to the delay adjuster can be set to an arbitrary frequency. Thereby, for example, when there are two systems of signals output from the image sensor, one cycle of the arbitrary frequency is obtained by setting the arbitrary frequency to twice the frequency of the reference clock so far. Thus, two pixel data can be processed. As a result, a plurality of pixel data can be output as multi-value data in parallel in one signal processing system, so that the circuit scale can be reduced.

(Other embodiments)
Although the embodiments of the present invention have been described in detail above, the present invention may be applied to a system constituted by a plurality of devices or may be applied to an apparatus constituted by one device.

  In the present invention, a software program for realizing the signal processing method according to the above-described embodiment is directly or remotely supplied to the system or apparatus, and the computer of the system or apparatus reads out and executes the supplied program. Can also be achieved. In that case, as long as it has the function of a program, the form does not need to be a program.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. That is, the claims of the present invention include the computer program itself for realizing the functional processing of the present invention. In this case, the program may be in any form as long as it has a program function, such as an object code, a program executed by an interpreter, or script data supplied to the OS.

  Various recording media for supplying the program can be used. For example, floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD- R).

  As another program supply method, the program can be supplied by connecting to a home page on the Internet using a browser of a client computer and downloading the program from the home page to a recording medium such as a hard disk. In this case, the computer program itself of the present invention or a compressed file including an automatic installation function may be downloaded. It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the claims of the present invention.

  Further, the program of the present invention may be encrypted, stored in a storage medium such as a CD-ROM, and distributed to users. In that case, a user who has cleared a predetermined condition is allowed to download key information to be decrypted from a homepage via the Internet, and using the key information, the encrypted program can be executed on a computer in a format that can be executed. To be installed.

  Further, the present invention can be realized in a form other than the form in which the functions of the above-described embodiments are realized by the computer executing the read program. For example, based on the instructions of the program, an OS or the like running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments can also be realized by the processing.

  Furthermore, the program read from the recording medium may be written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. In this case, thereafter, based on the instructions of the program, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing. .

FIG. 3 is a block diagram illustrating a configuration of a data transfer circuit that transfers image data output from an image sensor in synchronization with each other in the imaging apparatus according to the embodiment of the present invention. It is a figure explaining the provision timing of the synchronous code in the synchronous code adder which concerns on this Embodiment. It is a figure explaining arrangement | positioning of the effective data part contained in the data by which the serial / parallel conversion was carried out. It is a timing diagram explaining the timing of the parallel serial conversion by the parallel serial converter which concerns on embodiment. It is a block diagram which shows the structure of the delay adjuster which concerns on this Embodiment. It is a figure explaining the example of decoding by the decoder which concerns on this Embodiment. It is a block diagram which shows the internal structure of the trimming circuit which concerns on this Embodiment. It is a figure explaining the effective area | region in an image. It is a timing diagram explaining operation | movement of the V counter which concerns on this Embodiment. It is the block diagram which showed the signal processing circuit of the imaging device which concerns on Embodiment 2 of this invention.

Claims (10)

An oscillator that generates a reference clock; and
Synchronization signal generating means for generating horizontal and vertical synchronization signals in synchronization with the reference clock;
Timing signal generating means for generating a timing signal including a first clock signal and a driving signal in synchronization with the reference clock and the horizontal and vertical synchronization signals;
An image sensor that is driven by the drive signal and outputs an image signal representing a captured image as a plurality of pixel signals;
A plurality of parallel-serial conversion means provided corresponding to each of the plurality of pixel signals and converting a parallel pixel signal into a serial pixel signal in synchronization with the first clock signal;
Synchronization code adding means for adding a synchronization code synchronized with the horizontal synchronization signal to the pixel signal input to each of the plurality of parallel serial conversion means;
A plurality of detection means for detecting the synchronization code from the serial pixel signal output from each of the plurality of parallel-serial conversion means;
A plurality of serial / parallel conversion means provided corresponding to each of the plurality of parallel / serial conversion means, for converting the serial pixel signals of the plurality of parallel / serial conversion means into parallel pixel signals;
Adjusting means for adjusting the synchronization of the plurality of parallel pixel signals output from the plurality of serial-parallel conversion means, and outputting multi-value image data corresponding to the plurality of pixel signals, An imaging device.   Each of the plurality of pixel signals is an analog signal, provided corresponding to each of the plurality of pixel signals, and a plurality of A / D conversion means for converting the analog signal into a digital signal in synchronization with the timing signal The imaging apparatus according to claim 1, further comprising: Each of the plurality of serial / parallel conversion means outputs a synchronization flag in synchronization with the first parallel pixel signal after the corresponding detection means detects the synchronization code,
The adjusting unit includes a plurality of parallel pixels output from the plurality of serial / parallel conversion units in accordance with a timing of the synchronization flag output from a predetermined serial / parallel conversion unit among the plurality of serial / parallel conversion units. The imaging apparatus according to claim 1, wherein signals are synchronized. Storage means for storing area information indicating an effective image area;
Trimming means for cutting out multivalued data of an effective image area from multivalued image data corresponding to the plurality of pixel signals output from the adjusting means according to the area information stored in the storage means. The imaging apparatus according to any one of claims 1 to 3, wherein the imaging apparatus is characterized. A clock generator for generating a second clock signal having a frequency higher than the frequency of the reference clock;
The adjustment unit adjusts synchronization of the plurality of parallel pixel signals output from the plurality of serial-parallel conversion units in synchronization with the second clock signal, and multi-value images corresponding to the plurality of pixel signals The imaging apparatus according to claim 1, wherein data is output. An oscillator that generates a reference clock; a synchronization signal generator that generates horizontal and vertical synchronization signals in synchronization with the reference clock; and a first clock signal that is driven in synchronization with the reference clock and horizontal and vertical synchronization signals A signal processing method in an imaging apparatus, comprising: a timing signal generator that generates a timing signal including a signal; and an imaging element that is driven by the driving signal and outputs an image signal representing a captured image as a plurality of pixel signals. And
A step of converting a parallel pixel signal into a serial pixel signal in synchronization with the first clock signal by a plurality of parallel-serial converters provided corresponding to each of the plurality of pixel signals;
Adding a synchronization code synchronized with the horizontal synchronization signal to the pixel signal input to each of the plurality of parallel-serial converters;
Detecting the synchronization code from the serial pixel signal output from each of the plurality of parallel-serial converters;
Converting the serial pixel signal from each of the plurality of parallel serial converters into parallel pixel signals by a plurality of serial / parallel converters provided corresponding to each of the plurality of parallel / serial converters; ,
An adjustment step of adjusting the synchronization of the plurality of parallel pixel signals output from the plurality of serial-parallel converters, and outputting multi-value image data corresponding to the plurality of pixel signals;
A signal processing method in an imaging apparatus, comprising: Each of the plurality of pixel signals is an analog signal,
The analog signal is further converted into a digital signal in synchronization with the timing signal by a plurality of A / D converters provided corresponding to each of the plurality of pixel signals. 7. A signal processing method in the imaging apparatus according to 6. Each of the plurality of serial-parallel converters outputs a synchronization flag in synchronization with the first parallel pixel signal after detecting the corresponding synchronization code,
The adjusting step includes a plurality of parallel pixels output from the plurality of serial parallel converters in accordance with a timing of the synchronization flag output from a predetermined serial parallel converter among the plurality of serial parallel converters. 8. A signal processing method in an imaging apparatus according to claim 6, wherein the signals are synchronized.   The method further includes a trimming step of cutting out the multi-value data of the effective image region from the multi-value image data corresponding to the plurality of pixel signals output in the adjustment step according to the region information indicating the effective image region. The signal processing method in the imaging device of any one of Claims 6 thru | or 8. A second clock signal having a frequency higher than the frequency of the reference clock is generated by a clock generator;
The adjustment step adjusts synchronization of the plurality of parallel pixel signals output from the plurality of serial-parallel converters in synchronization with the second clock signal, and multi-value images corresponding to the plurality of pixel signals The signal processing method in the imaging apparatus according to claim 6, wherein data is output.

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