JP2005303673A - Image photographing processing system and control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image photographing processing system by which a body and an image pickup can be surely synchronized and a high-pixel still image can be photographed, and to provide a control program. <P>SOLUTION: The image photographing processing system is provided with the image pickup (a camera 100) which has an image pickup device and its peripheral circuits, and the body (120). The body 120 outputs the control signal of an operation clock with a speed lower than that of the frequency of the reference clock of the image pickup device and its peripheral circuits to the image pickup device and its peripheral circuits, restores an image data transfer clock outputted from the image pickup device and its peripheral circuits, and inputs the restored image data transfer clock to a digital camera function IC 121. While the image pickup (the camera part 100) makes the low-speed operation clock of the control signal into the same frequency as the reference clock by multiplying it at an arbitrary magnification, outputs the control signal of the operation clock at the same frequency to the image pickup device and its peripheral circuits, and also outputs to the body 120 the image data transfer clock and the image data which are outputted from the image pickup device and its peripheral circuits. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image photographing processing system having a structure in which a camera unit and a main body unit are separated, and a control program executed by the system.

  2. Description of the Related Art Conventionally, there has been known an image photographing processing system in which a camera unit including a CCD and a main body unit that performs AD conversion on an output signal from the camera unit are separated. In this image capturing processing system, the camera unit and the main unit are connected by a cable, and an output signal from the CCD of the camera unit is transmitted to the main unit via the cable, and the output signal is AD converted by the main unit ( For example, see Patent Document 1).

  There is also known an image photographing processing system that uses a method called differential serial (LVDS (Low Voltage Differential Signaling), IEEE 1394, etc.) when it is desired to extend the separation distance between the camera unit and the main body. For example, see Patent Document 2).

  An image photographing processing system that transfers digital data after AD conversion to a personal computer or the like by a differential serial method is also known (see, for example, Patent Document 3).

  Furthermore, SMPTE292M / 259M and TIA / EIA-644 are serial output standards (international standards) for digital video data, and are used for image transfer such as surveillance cameras and PC cameras.

  FIG. 10 is a block diagram showing a schematic configuration of a digital camera as an image photographing processing system having a structure in which a conventional camera unit and main body unit are separated.

  In the figure, reference numeral 900 denotes a camera unit. Reference numeral 901 denotes a lens group that inputs an image to the CCD 902. Reference numeral 902 denotes a CCD equivalent to 300 to 330,000 pixels that converts an image input from the lens group 901 into an electrical signal. Reference numeral 903 denotes a CDS / AGC (correlated double sampling circuit / automatic gain controller) that performs gain adjustment of an analog signal output from the CCD 902. A timing generator 904 outputs a timing signal for driving the CCD 902. Reference numeral 905 denotes an AD conversion unit that converts an output signal from the CDS / AGC 903 into parallel 12-bit digital data at a timing output from the timing generator 904. Reference numeral 906 denotes an oscillator that supplies a reference clock for driving the CCD 902 to the timing generator 904 and a clock that is a source of an image data sampling signal for sampling the 12-bit digital data output from the AD 905 by the LVDS 907 to the PLL 908. is there. Reference numeral 907 denotes a digital data converted by the AD conversion unit 905 and a VD (vertical synchronization) signal or an HD (horizontal synchronization) signal generated by the timing generator 904 in the main body unit by an image data sampling signal supplied from the PLL 908. This is an LVDS (low voltage differential signal data transfer) chip that is serialized and output. Reference numeral 908 denotes PLL (Phase Lock Loops) for creating an image data sampling signal based on a clock output from the oscillator 906. A cable 909 connects the LVDS 907 on the camera unit 900 side and the LVDS 927 on the main body 920 side. A main body 920 executes a series of operations as a digital camera that displays image data sent from the camera unit 900 and stores the image data as a still image in a CF card 925 that is an external storage unit by JPEG compression. Part. Reference numeral 921 denotes a digital camera function IC that executes the processing of the main body 920. Reference numeral 922 denotes a work memory that is a work area for the digital camera function IC 921 to perform image data expansion and compression. Reference numeral 923 denotes a program memory in which a program for operating the digital camera function IC 921 is stored. Reference numeral 924 denotes a liquid crystal display unit used for displaying a finder image and confirming a captured image. Reference numeral 925 denotes a CF card used for storing JPEG images compressed by the digital camera function IC 921. Reference numeral 925 denotes a key SW unit serving as an interface for an operator to perform various operations of the digital camera. 927 converts the differential serial signal output from the LVDS 907 of the camera unit 900 into an image data sampling signal based on the original parallel 12-bit digital data, the VD / HD signal, and the clock recovery function in the LVDS ( LVDS chip to be restored). A power supply unit 928 executes power supply for the entire system.

In the digital camera of FIG. 10, the camera unit 900 transmits image data of about 640 × 480 pixels (VGA size) or 720 × 480 pixels to the main unit 920 about 30 times per second. The received image data is output to the liquid crystal display unit 924.
Japanese Patent Laid-Open No. 10-42176 Japanese Patent Laid-Open No. 9-181936 JP 2000-333081 A

  However, in the conventional image capturing processing system in which the camera unit and the main unit are separated and the camera unit and the main unit are connected using a serial signal, the image data output from the camera unit is simply displayed. Or only a part or all of the image to be output to the display unit is JPEG-compressed.

  Since the reference clock of the camera unit and the reference clock of the main unit are not synchronized, when displaying the image of the camera unit on the liquid crystal display unit, the synchronization process of these reference clocks by software or hardware There was a problem that it was necessary to run.

  Even if the camera unit and the main unit are controlled by attaching a transmitter to each so that the camera unit and the main unit operate at the same frequency, the two transmitters can hardly have the same frequency. As a result, it is necessary to perform synchronization processing.

  The present invention has been made in view of the above-described conventional problems, and provides an image photographing processing system and a control program capable of reliably synchronizing the main body and the imaging unit and capable of photographing a high pixel still image. Objective.

  In order to achieve the above object, an image photographing processing system according to claim 1 is an image photographing processing system including an image pickup unit having an image pickup element and its peripheral circuit and a main body part, and the main body part includes the image pickup element and its peripheral part. A low-speed clock supply means for outputting a control signal of an operation clock slower than the frequency of a reference clock of the circuit to the image sensor and its peripheral circuits, and an image data transfer clock output from the image sensor and its peripheral circuits. And an input means for inputting the restored image data transfer clock to the low-speed clock supply means, and the imaging unit multiplies the low-speed operation clock of the control signal by an arbitrary magnification, and Synchronization means for outputting the control signal of the operation clock of the same frequency to the imaging device and its peripheral circuits, Characterized in that it comprises an image data output means for outputting the image data transfer clock and the image data output from the imaging device and its peripheral circuit in the main body portion.

  The image photographing processing system according to claim 7 is an image photographing processing system including an imaging unit having an imaging element and its peripheral circuit and a main body, and the main body is parallelized to be output to the imaging element and its peripheral circuit. A first parallel / serial means for serially converting the control signal, a first output means for outputting the control signal serially converted by the first parallel / serial means to the image sensor and its peripheral circuit, and the imaging unit. First serial / parallel conversion means for generating parallel image data from the input serial signal, image data clock recovery means for recovering an image data clock from the serial signal, and image data clock recovery means Generated by the first serial / parallel converter at the timing of the image data clock A sampling means for sampling the image data, and the image pickup section, the second serial / parallel conversion means for converting the serially converted control signal output from the first output means into parallel, and the serial converted data. A reference clock generating means for generating a reference clock for the image sensor and its peripheral circuit from the control signal, and serializing the parallelized image data at a frequency obtained by multiplying an image data clock generated based on the reference clock. The second parallel serial means for converting and the second output means for outputting the image data serialized by the second parallel serial means to the main body as the serial signal.

  The image photographing processing system according to claim 8 is an image photographing processing system including an imaging unit having a timing generator, an imaging element and its peripheral circuit, and a main body having a digital camera function IC, wherein the main body includes the timing generator. The reference clock signal supplied to the signal is divided by a predetermined value, and this signal is used as a transfer clock to serialize a vertical synchronizing signal, a horizontal synchronizing signal, and a control signal for a peripheral circuit of the image sensor, and Means for outputting to the image processing unit, receiving serialized image data from the imaging unit, parallelizing the image data, and outputting an image data timing signal restored based on the received image data Means for inputting to a digital camera function IC, and the imaging unit receives the input from the main body unit A signal obtained by dividing the quasi-clock signal is restored, and the restored signal is multiplied by a predetermined value to create a synchronized clock signal synchronized with the reference clock signal, and the synchronized clock signal and the vertical synchronization are generated. Means for synchronizing the signal and the horizontal synchronizing signal and supplying the synchronized signal to the timing generator, and using the image data timing signal output by the timing generator as a transfer clock to the main body And means for serializing the image data and outputting it to the main body.

  The control program according to claim 9 is a control program executed in an image photographing processing system including an image pickup unit having an image pickup element and its peripheral circuit, and a main body unit having a control unit for controlling the image pickup element and its peripheral circuit. A low-speed clock module that outputs a control signal of an operation clock slower than the frequency of the reference clock of the image sensor and its peripheral circuit to the image sensor and its peripheral circuit, and image data output from the image sensor and its peripheral circuit By restoring the transfer clock, causing the main body to execute the input module that inputs the restored image data transfer clock to the control means, and multiplying the low-speed operation clock of the control signal by an arbitrary magnification The same frequency as the reference clock is set, and the control signal of the operation clock having the same frequency is sent to the image sensor and the image pickup device. A synchronization module that outputs to a peripheral circuit; and an image data output module that outputs an image data transfer clock and image data output from the imaging device and the peripheral circuit to the main body, and causes the imaging unit to execute the synchronization module. To do.

  The control program according to claim 10 is a control program executed in an image photographing processing system including an image pickup unit having an image pickup device and its peripheral circuit and a main body, and is parallelized to be output to the image pickup device and its peripheral circuit. A first parallel / serial module for serially converting a control signal, a first output module for outputting a control signal serially converted by the first parallel / serial module to the imaging device and its peripheral circuit, and an input from the imaging unit A first serial-to-parallel conversion module for generating parallel image data from the serial signal, an image data clock recovery module for recovering an image data clock from the serial signal, and an image recovered by the image data clock recovery module At the timing of the data clock, A second serial for causing the main body to execute a sampling module for sampling image data generated by the first serial / parallel conversion module, and for parallel converting the serially converted control signal output by the first output module A parallel conversion module, a reference clock generation module that generates a reference clock for the image sensor and its peripheral circuits from the serially converted control signal, and a frequency obtained by multiplying an image data clock generated based on the reference clock A second parallel-serial module for serially converting the parallelized image data; and a second output module for outputting the image data serialized by the second parallel-serial module to the main body as the serial signal; To the imaging unit Characterized in that to the row.

  The control program according to claim 11 is a control program executed in an image photographing processing system including a timing generator, an imaging unit having an imaging element and its peripheral circuit, and a main body unit having a digital camera function IC. A reference clock signal to be supplied is divided by a predetermined value, and this signal is used as a transfer clock to serialize a vertical synchronization signal, a horizontal synchronization signal, and a control signal for a peripheral circuit of the image sensor, and And the image data serialized from the imaging unit, and parallelizing the image data, and the image data timing signal restored based on the received image data A module that inputs a camera function IC to the main body unit, A signal obtained by dividing the reference clock signal input from the unit is restored, and the restored signal is multiplied by a predetermined value to create a synchronized clock signal synchronized with the reference clock signal, and the synchronization A module that synchronizes the clock signal with the vertical synchronization signal and the horizontal synchronization signal and supplies these synchronized signals to the timing generator, and an image data timing signal output by the timing generator And a module for serializing image data and outputting the same to a main body unit.

  As described above, according to the first and ninth aspects of the present invention, even when a control signal is output from the main body with an operation clock slower than the frequency of the reference clock of the image sensor and its peripheral circuits, the main body and the image are captured. It is possible to perform a shooting operation in which the units are synchronized.

  According to the invention of claim 2, it is possible to reduce the speed of the serialized signal, and it is possible to reduce the current consumption, the EMI level, and the cost of the cable to be used.

  According to the fifth aspect of the present invention, the same effect can be obtained also by making the serial communication of the control signal and the serial communication of the image data wireless.

  According to the invention of claim 6, a connector is used to connect the main body unit and the imaging unit, a plurality of imaging units can be exchanged with respect to the main body unit, and an imaging unit having a synchronization circuit is mounted on the main body unit. In this case, a low-speed control signal is output, and when an imaging unit having no synchronization circuit is mounted on the main body unit, a high-speed control signal is output. Since the speed of the operation clock of the supplied control signal is switched, it is possible to use an imaging unit equipped with a different lens, and to improve the degree of freedom of imaging. In addition, it is possible to construct a system with low power consumption.

  According to the seventh, eighth, tenth, and eleventh aspects of the present invention, even if the control signal is output from the main body with an operation clock slower than the frequency of the reference clock of the image sensor and its peripheral circuits, Synchronized shooting operations can be performed, serialized signals can be slowed down, current consumption can be reduced, EMI levels can be reduced, and the cost of cables used can be reduced. Become.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a schematic configuration of a digital camera as an image photographing processing system according to the first embodiment of the present invention.

  In the figure, reference numeral 100 denotes a camera unit separated from the main body unit. Reference numeral 101 denotes a lens unit for inputting an image to the CCD 102, and a shutter mechanism for executing open / close control by a solenoid is incorporated therein. Reference numeral 102 denotes a CCD that converts an image input from the lens group 101 into an electrical signal.

  Reference numeral 103 denotes a CDS / AGC & AD (correlated double sampling circuit / automatic gain controller & analog-to-digital converter) that adjusts the gain of the analog signal output from the CCD 102 and converts it into a digital signal. A timing generator 104 outputs a timing signal for driving the CCD 102 and the CDS / AGC & AD 103. The timing generator 104 receives the timing generator reference clock (CLK signal) 621 output from the synchronization circuit 111 and supplies a signal obtained by dividing this signal by 1/2 to the CCD 102 and the CDS / AGC & AD 103 as a digital signal. The image data timing signal (MCLK) 302 is also supplied to the camera function IC 121. A serial signal input from the reception driver unit 106 is converted into parallel, and each signal constituting the converted parallel signal is converted into a predetermined output destination, that is, a timing generator 104, a CDS / AGC & AD 103, a CCD 102, and a lens unit 101. This is a serial / parallel converter that outputs to an internal shutter mechanism.

  A reception driver unit 106 receives a high-speed serial signal output from the transmission driver 128 of the main body unit 120 and outputs the high-speed serial signal to the serial / parallel conversion unit 105. A clock recovery unit 107 determines the latch clock frequency from the serial signal and the number of data bits input to the serial / parallel conversion unit 105 and outputs a low-speed clock to the synchronization circuit 111 based on the latch clock frequency. Reference numeral 108 denotes a 10-bit image data (AD_DATA in the drawing) signal AD-converted from the CDS / AGC & AD 103, which is input in parallel, and a signal obtained by multiplying the image data timing signal (MCLK) 302 input from the PLL unit 109. This is a parallel / serial conversion unit that serializes image data signals input in parallel and outputs them to the transmission driver unit 110.

  An image data timing signal (MCLK) 302 output from the timing generator 104 is input as a latch clock, and 109 is necessary for the parallel / serial conversion unit 108 to perform serial conversion by multiplying the signal. This is a PLL unit that generates the serial transfer clock 301. A transmission driver unit 110 outputs the serial signal output from the parallel / serial conversion unit 108 to the main body unit 120 as a high-speed serial signal. 111 is a timing generator reference clock (CLK signal) 621 that is restored by the clock recovery unit 107 and multiplied by a predetermined magnification (4 times in the present embodiment) based on the low-speed clock 202 that is output. The horizontal synchronization signal (HD) 610 and the vertical synchronization signal (VD) 611 output from the serial / parallel converter 105 are latched at the timing of the timing generator reference clock (CLK signal) 621, and these signals are synchronized. This is a synchronizing circuit that outputs to the timing generator 104.

  Reference numeral 112 denotes a cable that outputs a high-speed serial signal from the main body unit 120 to the camera unit 100, and reference numeral 113 denotes a cable that outputs a high-speed serial signal from the camera unit 100 to the main body unit 120.

  A main body 120 is separated from the camera unit 100. Reference numeral 121 denotes a digital camera function IC that controls the device based on an input from a key switch or digitizer (not shown), and controls the CDS / AGC & AD 103 and the timing generator 104 of the camera unit 100 by synchronous serial communication.

  The digital camera function IC 121 (low speed frequency supply means) generates a digital signal output from the CDS / AGC & AD 103 as image data, and divides the timing generator reference clock (CLK signal) by the PLL unit 129. 202 is supplied.

  Further, the digital camera function IC 121 controls exposure and white balance, and outputs a finder image (640 × 480 dots) to the display 125 and generates a JPEG file of a captured image.

  The digital camera function IC 121 can synchronize the image data of the camera unit 100 and the main body unit 120 by sampling 10-bit image data (AD_DATA signal in the drawing) AD-converted in accordance with the image data timing signal 302. it can.

  In addition to the so-called microprocessor, this digital camera function IC 121 incorporates logic such as YC → RGB conversion logic of finder data, JPEG compression logic, and a memory controller that controls external memory such as program memory 124 and work memory 123. So-called SOC (system on silicon) may be used. Reference numeral 122 denotes an oscillator that generates a clock for operating the digital camera function IC 121. Reference numeral 123 denotes a camera work memory that is connected to the digital camera function IC 121 and is used as a work memory used for JPEG development, image size conversion, and the like, mainly using SDRAM or SRAM.

  A program memory 124 includes a flash memory or a mask memory in which a control program for the digital camera function IC 121 is stored. Reference numeral 125 denotes a display which is a TFT type liquid crystal display, and reference numeral 126 denotes a CF card connected to the digital camera function IC 121 by a connector via a dedicated bus. Reference numeral 127 denotes a horizontal synchronization signal (HD) 610 / vertical synchronization signal (VD) 611 / synchronization serial signal (SSI and TG_CS signal) / reset signal / CSUB signal 502 / shutter control signals 503 and 504 output from the digital camera function IC 121. Are parallel-to-serial conversion units that serialize these parallel-input signals with the serial transfer clock 201 output from the PLL unit 129 and output the serialized signals to the camera unit 100. The horizontal synchronization signal (HD) 610 / vertical synchronization signal (VD) 611 / synchronous serial signal (SSI and TG_CS signal) / reset signal are used to control the timing generator 104, and the synchronous serial signal (SSI and TG_CS signal) is Furthermore, it is used for control of CDS / AGC & AD103. The CSUB signal 502 is used to control the CCD 102, and the shutter control signals 503 and 504 are used to control the shutter mechanism inside the lens unit 101.

  A transmission driver unit 128 outputs the serial signal output from the parallel / serial conversion unit 127 to the camera unit 100 as high-speed serial. 129 receives the low-speed clock 202 output from the digital camera function IC 121 as a latch clock, and multiplies the clock, whereby the serial-transfer clock 201 required for the parallel-serial conversion unit 127 to perform serial conversion is input. This is a PLL section that produces Reference numeral 130 denotes a serial / parallel conversion unit which converts the serial signal input from the reception driver unit 131 into a parallel signal and outputs the converted signal to the digital camera function IC 121. A reception driver unit 131 receives a high-speed serial signal output from the transmission driver 110 of the camera unit 100 and outputs the signal to the serial / parallel conversion unit 130. A clock recovery unit 132 determines the latch clock frequency from the serial signal and the number of data bits input to the serial / parallel conversion unit 130 and outputs an image data timing signal to the digital camera function IC 121 based on the latch clock frequency. is there.

  In FIG. 1, a serial / parallel conversion unit 105, a reception buffer unit 106, and a clock recovery unit 107 constitute a reception LVDS of the camera unit 100, and a parallel / serial conversion unit 108, a transmission driver unit 110, and a PLL unit 109 are cameras. The transmission side LVDS of the unit 100 is configured. In addition, the serial / parallel converter 130, the reception buffer unit 131, and the clock recovery unit 132 constitute a reception side LVDS of the main body unit 120, and the parallel / serial conversion unit 127, the transmission driver unit 128, and the PLL unit 129 are the main body unit 120. The transmission side LVDS is configured.

  FIG. 2 is a waveform diagram of a serial signal output from the parallel / serial conversion unit 127 of FIG.

  In FIG. 2, 201 is a serial transfer clock signal (LVDS_CLK) generated by the PLL unit 129 by multiplying the low-speed clock (CLK) 202 input as a latch clock. Reference numeral 202 denotes a low-speed clock (CLK), which is created by the digital camera function IC 121. In the present embodiment, the timing generator reference clock 621 divided by 4 is handled as the low-speed clock 202. Reference numeral 203 denotes a digital camera function IC 121, which controls the timing generator 104, CDS / AGC & AD 103, CCD 102, and shutter mechanism inside the lens unit 101, horizontal synchronizing signal (HD) 610 / vertical synchronizing signal (VD) 611 / synchronous serial. This is a data configuration (CONT) when signals (SSI and TG_CS signals) / reset signal / CSUB signal 502 / shutter control signals 503 and 504 are serialized.

  The serial transfer clock signal (LVDS_CLK) 201 is 8 bits (horizontal synchronization signal (HD) 610 / vertical synchronization signal (VD) 611 / synchronization serial signal (SSI and TG_CS signal) / reset signal / CSUB signal 502 / Since the total number of bits of 10 bits obtained by adding the start / stop bits to the shutter control signals 503 and 504) is serialized during the period of the low-speed clock 202 (in one cycle), the low-speed clock 202 × the total number of bits (10) = The relationship of serial transfer clock signal (LVDS_CLK) 201 is established.

  The content transmitted from the digital camera function IC 121 to the camera unit 100 includes a vertical synchronization signal (VD), a horizontal synchronization signal (HD), and AE (exposure) for controlling the CCD 102 in a state where the timing generator 104 is synchronized with the digital camera function IC 121. Control) and AWB (automatic white balance control) to control the gain setting, the synchronous serial signal output to the CDS / AGC & AD103, the transfer clock (SCLK), synchronous serial data (SD) and synchronous serial communication Chip select signal (CS) signal for activating, chip select signal (TG_) for activating synchronous serial communication, which is output to timing generator 104 to control electronic shutter settings related to AE and AWB S), reset signal (RESET) for initializing the state of the timing generator 104 at startup, shutter open signal (S_OPN) for controlling the shutter mechanism in the lens module 101, shutter close signal (S_CLS), and still image shooting At this time, it is composed of a substrate bias control signal (CSUB) for controlling the substrate bias level of the CCD 102.

  In the synchronous serial communication to the timing generator 104, only the chip select signal (TG_CS) is output because the transfer clock (SCLK) and synchronous serial data (SD) of the synchronous serial communication output to the CDS / AGC & AD 103 are output. The synchronous serial communication to be activated is determined by which chip select signal is selected.

  In the case of a 2 million pixel CCD, these control signals are 36 MHz for the timing generator reference clock (CLK) 621, about 9 MHz for the low speed clock 202 obtained by dividing the timing generator reference clock (CLK) 621 by four, and the vertical synchronization signal (VD). Is about 30 Hz, horizontal synchronization signal (HD) is about 37 KHz, and synchronous serial transfer clock (SCLK) is 1 MHz. Since each control signal is sufficiently slow with respect to the low-speed clock 202, these signals are output as usual. Even if the parallel-serial conversion unit 127 latches at the timing of the low-speed clock 202, there is no functional problem.

  FIG. 3 is a waveform diagram of a serial signal output from the parallel / serial conversion unit 108 of FIG.

  In FIG. 3, reference numeral 301 denotes a serial transfer clock signal (LVDS_CLK) generated by the PLL unit 109 by multiplying an image data timing signal (MCLK) 302 inputted as a latch clock. Reference numeral 302 denotes an image data timing signal (MCLK) generated by the timing generator 104. Reference numeral 303 denotes a data configuration (CONT) when the AD-converted 10-bit image data (AD_DATA) signal output from the CDS / AGC & AD 103 is serialized.

  The serial transfer clock signal (LVDS_CLK) 301 is a total of 12 bits obtained by adding start / stop bits to 10 bits of the image data (AD_DATA) 303 inputted in parallel during the period of the image data timing signal (MCLK) 302. Since serialization is performed (in one cycle), the relationship of image data timing signal (MCLK) 302 × total number of bits (12) = serial transfer clock signal (LVDS_CLK) 301 is established. Even in this case, since the 10 bits of the signal of the image data timing signal (MCLK) 302 and the image data (AD_DATA) 303 are synchronized, the parallel / serial conversion unit 108 latches at the timing of the image data timing signal (MCLK) 302. But there is no problem.

  FIG. 4 is a diagram illustrating the relationship between the vertical synchronization signal (VD) and the substrate bias control signal (CSUB) and the control signal for the shutter mechanism in still image shooting.

  In FIG. 4, reference numeral 501 denotes a synchronized vertical synchronizing signal (VD2) output from the synchronizing circuit 111 and synchronized with the timing generator reference clock (CLK) 621. Reference numeral 502 denotes a substrate bias control signal (CSUB) output from the digital camera function IC 121. This substrate bias control signal is a signal that is controlled during the still image exposure period and the CCD data reading period. When this control is executed, the amount of charge accumulated in the CCD increases, and an image with a large amount of information can be taken. Become. Reference numeral 503 denotes a shutter close signal in a solenoid type shutter control mechanism in the lens module 101. Reference numeral 504 denotes a shutter open signal in a solenoid type shutter control mechanism in the lens module 101. Reference numeral 505 denotes a block representing a shutter state when control of the shutter close signal 503 and the shutter open signal 504 is executed. In the case of still image shooting using a CCD, it is necessary to close the shutter during the CCD readout period in order to prevent smear and collapse of the color balance. Reference numeral 506 denotes a waveform indicating the timing of synchronous serial communication output from the digital camera function IC 121 to the timing generator 104 in still image shooting. The communication content performed during the exposure period is for instructing to perform the operation for the readout period from the next synchronized vertical synchronization signal (VD2), and the communication content performed during the EVEN readout period is the next synchronized vertical synchronization signal. This is for instructing to perform a normal finder display CCD data output operation from the signal (VD2).

  FIG. 5A is a block diagram illustrating an internal configuration of the synchronization circuit 111, and FIG. 5B is a waveform diagram of each signal input to and output from the synchronization circuit 111.

  In FIG. 5A, reference numeral 601 denotes a multiplier circuit, which receives the low-speed clock 202 output from the digital camera function IC 121 (low-speed frequency supply means), quadruples the low-speed clock 202, and returns to the original timing generator reference. Restore to the clock 621. Reference numeral 602 denotes a latch circuit, which latches the horizontal synchronization signal (HD) 610 and the vertical synchronization signal (VD) 611 at the timing of the timing generator reference clock 621 output from the multiplication circuit 601, and restores the restored timing generator reference clock 621. Output in synchronization. Reference numeral 610 denotes a horizontal synchronization signal (HD) output from the digital camera function IC 121, and reference numeral 611 denotes a vertical synchronization signal (VD) output from the digital camera function IC 121. Reference numeral 620 denotes a synchronized horizontal synchronization signal (HD 2) synchronized with the timing generator reference clock 621 output from the latch circuit 602. A timing generator reference clock 621 is restored from the low-speed clock 202 by the multiplication circuit 601.

  In the waveform diagram of FIG. 5B, the relationship between the horizontal synchronizing signal (HD) 610 and the synchronizing horizontal synchronizing signal (HD2) 620 is shown, but a vertical synchronizing signal (VD) 611 and a synchronizing vertical synchronizing signal (not shown) Similarly, the relationship with VD2) 501 is synchronized with the timing generator reference clock 621.

  FIG. 6 is a flowchart showing a flow of a series of processing of each unit when the camera unit 100 and the main body unit 120 are connected and the power is turned on.

  First, when the operator turns on the power SW of the main body 120 (step S401), the digital camera function IC 121 is activated from the sleep mode, executes the initial process of the main body 120, and simultaneously supplies power to the camera 100. Is started (step S402). After the initial processing of the main body 120 is completed, the digital camera function IC 121 starts supplying the low-speed clock 202, and further outputs display data of the timing generator 104, the CDS / AGC & AD 103, the CCD 102, and the shutter mechanism inside the lens unit 101. Initial control is performed, that is, horizontal sync signal (HD) 610 / vertical sync signal (VD) 611 / synchronous serial signal (SSI and TG_CS signal) / reset signal / CSUB signal 502 / shutter control signals 503 and 504 are output. (Step S403). Note that the low-speed clock 202 is always supplied during the period in which the camera unit 100 is operating. Each of these control signals is serialized as a data structure 203 by a parallel / serial conversion unit 127 that is supplied with a serial transfer clock signal (LVDS_CLK) 201 generated by a PLL unit 129, and is high-speed serialized by a transmission drive unit 128. The signal is output to the cable 112 as a signal. The reception driver unit 106 that has received the high-speed serial signal via the cable 112 inputs the serial signal to the serial / parallel conversion unit 105. Upon receiving the serial signal, the serial / parallel converter 105 converts the serial data of the data structure 203 into the original horizontal synchronization signal (HD) 610 / vertical synchronization signal (VD) 611 / synchronization serial signal (SSI and TG_CS signal) / The reset signal / CSUB signal 502 / shutter control signals 503 and 504 are parallelized and supplied to the synchronization circuit 111, the timing generator 104, the CDS / AGC & AD 103, the CCD 102, and the shutter mechanism inside the lens unit 101.

  Further, the clock recovery unit 107 restores the low-speed clock 202 from the serial signal frequency and the number of bits of the data configuration 203 and supplies the low-speed clock 202 to the synchronization circuit 111. The synchronization circuit 111 that has been supplied with the low-speed clock 202 restores the timing generator reference clock 621 and supplies it to the timing generator 104. The timing generator 104 divides the timing generator reference clock 621 by a half to generate an image data timing signal (MCLK) 302 and supplies the image data timing signal (MCLK) 302 to the PLL unit 109. The timing generator 104 also supplies a drive reference signal to the CCD 102 and the CDS / AGC & AD 103. Start supplying. Each device in the camera unit 100 supplied with these control signals and drive signals performs an initial process for outputting display data based on the contents of the signals (step S404).

  When the initial processing is completed, the image data is output from the CCD 102 to the CDS / AGC & AD 103. The CDS / AGC & AD 103 performs AD conversion on the image data, converts it to 10-bit digital image data, and then outputs it to the parallel / serial conversion unit 108. The 10-bit digital image data is serialized as shown in the data configuration 303 by the parallel-serial conversion unit 108 that has received the serial transfer clock signal (LVDS_CLK) 301 from the PLL unit 109, and is transmitted by the transmission drive unit 110 as a high-speed serial signal. Is output to the cable 113 (step S405). The reception driver unit 131 that has received the high-speed serial signal via the cable 113 inputs the serial signal to the serial / parallel conversion unit 130. Upon receiving the serial signal, the serial / parallel converter 130 parallelizes the serial data of the data structure 303 into the original 10-bit digital image data and supplies it to the digital camera function IC 121. The clock recovery unit 132 restores the image data timing signal (MCLK) 302 from the frequency of the serial signal and the number of bits of the data configuration 303 and supplies the image data timing signal (MCLK) 302 to the digital camera function IC 121. While the operator looks at the image data displayed on the display and performs key operations for still image shooting and function change operations, the digital camera function IC 121 monitors key input as well as display processing during the viewfinder display state. It is always performed and it is determined whether or not a key input has been made (step S406).

  If there is no key input by the operator during the finder display state, the image data output from the CCD 102 is transmitted to the digital camera function IC 121 via the CDS / AGC & AD 103 and the like, and the AE (exposure) is performed by the digital camera function IC 121. Control) processing and image processing such as AWB (automatic white balance control) processing are performed (step S407) and displayed on the display 125. This is the finder display state. In this case, the digital camera function IC 121 determines the brightness level calculated from the image data output from the CDS / AGC & AD 103 and the register value of the electronic shutter inside the timing generator 104 or the inside of the CDS / AGC & AD 103. This is realized by changing the register value of the gain setting by each synchronous serial communication. If there is a key input by the operator during the finder display state, a key type determination process is performed (step S408).

  If it is determined in the key type determination processing in step S408 that the input key is the power OFF key SW, the digital camera function IC 121 stops displaying on the display unit 125 and supplies power to the camera unit 100. The digital camera function IC 121 itself performs an OFF process to enter the sleep mode (step S409), and the process is terminated.

  In the key type determination process in step S408, when it is determined that the input key is the function setting SW, the digital camera function IC 121 determines that there is a function setting change (parameter change) related to the camera unit 100. In this case, the setting content corresponding to the change is output to the timing generator 104 and the CDS / AGC & AD 103 by synchronous serial communication, and control is performed so that each setting is changed (step S410).

  In the key type determination process in step S408, if it is determined that the input key is the shutter SW for instructing still image shooting, the digital camera function IC 121 is for still image shooting such as stop of AE processing / AWB processing. An internal setting is made and the substrate bias control (CSUB) signal 502 for controlling the accumulated charge amount during the exposure period is set to the high level for the camera unit 100 in synchronization with the change of the synchronous vertical synchronization signal (VD2) 501. Next, synchronous serial communication (506) is performed to instruct the timing generator 104 to read out from the next synchronized vertical synchronization signal (VD2) 501, and the next synchronized vertical synchronization signal (VD2) 501 A shutter close signal 503 for closing the shutter is output in synchronization with the change.

  The synchronous vertical synchronizing signal (VD2) 501 output from the digital camera function IC 121 is a data reading period of the CCD 102 after the exposure period ends. In the case of using a 2 million pixel CCD, the ODD frame (EVEN frame depending on the CCD) reading period ends in a time twice as long as the exposure period, and one synchronized vertical synchronizing signal (VD2) 501 is output. Next, an EVEN frame (ODD frame depending on CCD) reading period starts, and after a time twice as long as the exposure period has elapsed, a vertical synchronization signal (VD) 501 is output to return to the normal operation state. During this EVEN frame (ODD frame depending on CCD) readout period, synchronous serial communication (506) for returning the timing generator to normal operation is performed, and the shutter is synchronized with the next synchronous vertical synchronization signal (VD2) 501. The shutter open signal 504 is output so that. Finally, after the digital camera function IC 121 determines that all the CCD data 303 has been read, the substrate bias control (CSUB) signal 502 is set to the low level, and the still image JPEG is based on all the read CCD data 303. By creating an image, the shooting process is completed (step S411). After the creation of the JPEG image is completed, the digital camera function IC 121 returns to the finder display state by changing the internal setting so that the normal finder display can be performed (step S412).

  As described above, according to the present embodiment, an operation clock that is slower than the frequency of the reference clock of the imaging device (CCD) of the camera unit and its peripheral circuit is output from the main unit, and the camera unit performs this operation. By multiplying the clock by an arbitrary magnification, the same frequency as the reference clock is obtained, and the operation clock of the same frequency is output to the image sensor and its peripheral circuit, and the main body is output from the image sensor and its peripheral circuit. Since the image data transfer clock is restored and input to itself and the low-speed operation clock is output, the digital camera function IC of the main unit and the timing generator of the imaging unit can be synchronized.

  Hereinafter, the second embodiment of the present invention will be described in detail with reference to FIG.

  In the first embodiment, the timing generator reference clock is divided by four in order to generate the low-speed clock output from the digital camera function IC (low-speed frequency supply means). However, in the case of a 2 million pixel CCD, the control signal output from the digital camera function IC is about 30 Hz for the vertical synchronization signal (VD), about 37 KHz for the horizontal synchronization signal (HD), and 1 MHz for the synchronous serial transfer clock (SCLK). In addition, the vertical synchronization signal (VD) and the horizontal synchronization signal (HD) are almost constantly output, but the synchronous serial for controlling the CDS / AGC & AD and the timing generator has a timing in accordance with the vertical synchronization signal. In most cases, the output is intermittent. Therefore, the frequency division ratio for generating a low-speed clock output from the digital camera function IC is made variable by the main unit, a relatively high clock is supplied during the period in which the synchronous serial communication is performed, and in other periods, Variable frequency that has an output frequency variable means that controls the division ratio so that a low clock can be supplied, and that allows the change of the division ratio to be transmitted linearly to the synchronization circuit by means of synchronous serial communication or control signals. It is possible to construct a system with lower power consumption by having a transmission means and a variable multiplication means for making the number of multiplication variable according to the change of the clock frequency in the synchronization circuit.

  Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 7 is a block diagram showing a schematic configuration of a digital camera as an image photographing processing system according to the second embodiment of the present invention.

  In FIG. 7, reference numeral 700 denotes a camera unit according to the second embodiment. Reference numeral 705 denotes a serial / parallel conversion unit for the number of bits according to the second embodiment. Reference numeral 711 denotes a variable synchronization circuit including variable multiplication means that can change a multiplication factor by a control signal (CKS) output from the digital camera function IC 721. Reference numeral 720 denotes a main body according to the second embodiment. Reference numeral 721 denotes a digital camera function IC that includes an output frequency variable means that outputs a variable frequency dividing ratio for generating a low-speed clock, and a variable frequency transmission means that transmits a frequency change to the variable synchronization circuit 711. Reference numeral 727 denotes a parallel / serial conversion unit for the number of bits according to the second embodiment.

  At the time of initial operation after power-on and automatic exposure correction processing (AE), initial setting for the CDS / AGC & AD 103 and timing generator 104 and synchronous serial communication for changing the electronic shutter are performed. In such a situation, the latch clock frequency input to the PLL unit 729, which is required for transferring the synchronous serial clock of about 1 MHz by performing parallel-serial conversion, is considered to be 8 MHz or more. .

  In other situations, that is, in the situation where synchronous serial communication is not performed, the earliest signal to the parallel / serial conversion unit 727 is approximately 37 KHz of the horizontal synchronization signal (HD). Therefore, the latch clock frequency input to the PLL unit 729 in this case is considered to be sufficient if it is 500 kHz or more.

  In view of the above situation, the digital camera function IC 721 switches the output of the timing generator reference clock 36 MHz, which is 9 MHz divided by 4, and about 1.125 MHz, which is divided by 32, as output frequency variable means according to the situation. As a variable frequency transmission means, the frequency selection signal (CKS) is switched to the H level when outputting 9 MHz, and the frequency selection signal (CKS) is switched to the L level when outputting about 1.125 MHz. The multiplication circuit of the variable synchronization circuit 711 is provided with a block that performs two multiplication processes of 4 times and 32 times, and the multiplication process is performed in which block depending on the level of the input frequency selection signal (CKS). The decision is made. Therefore, the timing generator reference clock output from the variable synchronization circuit 711 is always stable at 36 MHz.

  As described above, according to the present embodiment, the frequency division ratio for generating the low-speed clock output from the digital camera function IC is variable, and the period during which the synchronous serial communication is performed is relatively high. In other periods, it has output frequency variable means for controlling the frequency division ratio so that a low clock can be supplied. Further, the frequency division ratio is controlled by the synchronous serial communication or control signal. It has a variable frequency transmission means that enables the change to be transmitted linearly, and the camera unit has a variable multiplication means that makes the multiplication number variable according to the change of the clock frequency in the synchronization circuit. There is an effect that it becomes possible to construct a system.

  Hereinafter, the third embodiment of the present invention will be described in detail with reference to FIG.

  In the first embodiment, the timing generator reference clock is divided by four in order to generate the low-speed clock output from the digital camera function IC (low-speed frequency supply means). In the second embodiment, the process of switching the latch clock according to the frequency speed of the control signal is executed. However, by using the synchronous serial transfer clock (SCLK) of approximately 1 MHz, which is used in synchronous serial communication, as the latch clock, the latch clock speed is reduced and the signal input to the parallel / serial converter of the main unit is reduced. And lower speed serial communication can be realized. In addition, since the signal input to the parallel / serial conversion unit of the main body can be reduced, the synchronization circuit can be simplified.

  Hereinafter, the same parts as those in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 8 is a block diagram showing a schematic configuration of a digital camera as an image photographing processing system according to the third embodiment of the present invention.

  In FIG. 8, reference numeral 800 denotes a camera unit. Reference numeral 805 denotes a serial / parallel converter of the camera unit 800. Reference numeral 811 denotes a synchronizing circuit in which the multiplication factor is fixed to 36 times. Reference numeral 820 denotes a main body. A digital camera function IC 821 outputs a synchronous serial transfer clock (SCLK) as a low-speed clock. Reference numeral 827 denotes a parallel / serial conversion unit of the main body unit 820.

  As described above, according to the present embodiment, by using approximately 1 MHz of the synchronous serial transfer clock (SCLK) used in the synchronous serial communication as the latch clock, the latch clock speed is reduced and the main unit is parallelized. -The signal input to the serial converter can be reduced, and slower serial communication can be realized. In addition, since the signal input to the parallel / serial conversion unit of the main body can be reduced, the synchronization circuit can be simplified.

  The fourth embodiment of the present invention will be described below in detail with reference to FIG.

  In the first embodiment, it is assumed that the main unit and the camera unit are connected by a cable and are basically always used in a one-to-one relationship. However, the expandability of the system can be improved by connecting the main body portion and the camera portion to a connector so that the camera portion can be easily separated. Further, the main body has a synchronization circuit detecting means for determining whether or not the synchronization circuit is present in the camera unit that is freely mounted, and when there is a synchronization circuit, the digital clock is transmitted as the transmission clock of the main body. When the clock output from the camera function IC is used and there is no synchronization circuit, the timing generator reference clock is used as the transmission clock of the main unit, so that various camera units can be mounted. Play.

  Hereinafter, the same parts as those in the first to third embodiments are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 9 is a block diagram showing a schematic configuration of a digital camera as an image photographing processing system according to the fourth embodiment of the present invention.

  In FIG. 9, 1000 is a camera unit, and 1020 is a main body unit. Reference numerals 1012 and 1013 denote connectors for connecting the camera unit 1000 and the main body unit 1020.

  Reference numeral 1022 denotes a comparison circuit (synchronization circuit detection means) that compares the image data timing signal (MCLK) output from the clock recovery unit 132 with the timing generator reference clock to determine whether the camera unit 1000 has a synchronization circuit. is there. Reference numeral 1021 denotes a digital camera function IC that can switch the output of the low-speed clock or the output of the timing generator reference clock to the PLL unit 129 according to the detection signal output from the comparison circuit 1022.

  When the camera unit 1000 is mounted on the main body unit 1020 and the power is turned on, the main body unit 1020 serially converts each control signal output from the digital camera function IC 1021 using the low-speed clock output from the digital camera function IC 1021. Output to the unit 1000. When the synchronization circuit 111 is present in the camera unit 1000, an appropriate reference clock is supplied from the synchronization circuit 111 to the timing generator 104, and the image data timing signal (MCLK) output from the timing generator 104 is a timing signal. The frequency is half that of the generator reference clock. The comparison circuit 1022 that receives the image data timing signal (MCLK) restored by the clock recovery unit 132 and the timing generator reference clock output from the digital camera function IC 1021 receives the image data timing signal (MCLK) and the timing generator reference clock. When it is determined that the relationship is 1: 2, it is determined that the synchronization circuit 111 is present in the camera unit 1000, and a detection signal is output to the digital camera function IC 1021. The digital camera function IC 1021 that has received the detection signal continues to output each control signal as it is with the low-speed clock. When the camera unit 1000 does not have the synchronization circuit 111, a clock slower than the reference clock is input to the timing generator 104, and the image data timing signal (MCLK) is a quarter of an appropriate value. It becomes the following. If the comparison circuit 1022 determines that the relationship between the image data timing signal (MCLK) and the timing generator reference clock is slower than 1: 2, the synchronization circuit 111 is not present in the camera unit 1000. Judgment is made and no detection signal is output to the digital camera function IC 1021. The digital camera function IC 1021, which has determined that no detection signal is input, switches to output the timing generator reference clock as the serial conversion clock.

  As described above, according to the present embodiment, when a plurality of camera units can be replaced with respect to the main body unit and a camera unit having a synchronization circuit is mounted, a low-speed control signal output is performed. When a camera unit that does not have a synchronization circuit is installed, it is possible to use a camera unit equipped with different lenses by enabling the output of high-speed control signals, improving the freedom of shooting. It becomes possible to make it.

  An object of the present invention is to supply a storage medium (or recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or apparatus, and a computer (or CPU or MPU) of the system or apparatus. Needless to say, this can also be achieved by reading and executing the program code stored in the storage medium.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code However, it is needless to say that a case where the functions of the above-described embodiment are realized by performing part or all of the actual processing.

  Further, after the program code read from the storage medium is written to a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the card or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

  The above-described program only needs to be able to realize the functions of the above-described embodiments by a computer, and the form includes forms such as object code, a program executed by an interpreter, and script data supplied to the OS. But you can.

  As a recording medium for supplying the program, for example, RAM, NV-RAM, floppy (registered trademark) disk, optical disk, magneto-optical disk, CD-ROM, MO, CD-R, CD-RW, DVD (DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), magnetic tape, non-volatile memory card, other ROM, etc. may be used as long as they can store the above programs. Alternatively, the program is supplied by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

1 is a block diagram showing a schematic configuration of a digital camera as an image photographing processing system according to a first embodiment of the present invention. FIG. 2 is a waveform diagram of a serial signal output from a parallel / serial conversion unit 127 in FIG. 1. FIG. 2 is a waveform diagram of a serial signal output from a parallel / serial conversion unit 108 in FIG. 1. It is a figure showing the relationship between the vertical synchronizing signal (VD) and board | substrate bias control signal (CSUB) in still image photography, and the control signal of a shutter mechanism. (A) is a block diagram showing an internal configuration of the synchronization circuit 111, and (B) is a waveform diagram of each signal input to and output from the synchronization circuit 111. FIG. 3 is a flowchart showing a flow of a series of processes of each unit when the camera unit 100 and the main body unit 120 are connected and turned on. It is a block diagram which shows schematic structure of the digital camera as an image imaging processing system which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows schematic structure of the digital camera as an image imaging processing system which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows schematic structure of the digital camera as an image imaging processing system which concerns on the 4th Embodiment of this invention. It is a block diagram which shows schematic structure of the digital camera as an image pick-up processing system which is the structure which the conventional camera part and main-body part isolate | separate.

Explanation of symbols

100 Camera unit 102 CCD
103 CDS / AGC & AD (correlated double sampling circuit / automatic gain controller & analog-to-digital converter)
104 Timing generator 105, 130 Serial / parallel conversion unit 106, 131 Reception driver unit 107, 132 Clock recovery unit 108, 127 Parallel / serial conversion unit 109, 129 PLL unit 110, 128 Transmission driver unit 111 Synchronization circuit 112, 113 Cable 120 Main unit 121 Digital camera function IC
202 Low speed clock

Claims (11)

In an image photographing processing system including an image pickup unit and an image pickup unit having a peripheral circuit thereof and a main body unit,
The main body includes a low-speed clock supply unit that outputs an operation clock control signal slower than a frequency of a reference clock of the image sensor and its peripheral circuit to the image sensor and its peripheral circuit, and the image sensor and its peripheral circuit. An image data transfer clock output from the image data transfer clock, and input means for inputting the restored image data transfer clock to the low-speed clock supply means,
The imaging unit multiplies the low-speed operation clock of the control signal by an arbitrary magnification to make the same frequency as the reference clock, and outputs the control signal of the operation clock of the same frequency to the imaging device and its peripheral circuit An image photographing processing system comprising: synchronization means; and image data transfer clock and image data output means for outputting image data transfer clocks and image data output from the imaging device and its peripheral circuits.   The control signal and the image data are each composed of parallel data, the main body unit includes first parallel / serial conversion means for converting the control signal into serial data, and the imaging unit converts the image data into serial data. A second parallel / serial conversion means for converting the control signal and the image data to be executed between the main body section and the imaging section, the first and second parallel / serial conversion means The image photographing processing system according to claim 1, wherein serial communication is executed by the method.   3. The image photographing processing system according to claim 2, wherein a motor control signal is inputted to the parallel input of the first parallel / serial conversion means. The main body section includes first serial / parallel conversion means for parallelizing a serial signal input from the imaging section, and the imaging section performs second serial / parallel conversion for parallelizing serial data input from the main body section. With means,
The first parallel / serial conversion means is connected to the second serial / parallel conversion means via a connector, and the second parallel / serial conversion means is connected to the second serial / parallel conversion means via another connector. 4. The image photographing processing system according to claim 2, wherein the image photographing processing system is used. The main body section includes first serial / parallel conversion means for parallelizing a serial signal input from the imaging section, and the imaging section performs second serial / parallel conversion for parallelizing serial data input from the main body section. With means,
The first parallel / serial conversion means is connected to the second serial / parallel conversion means by wireless communication, and the second parallel / serial conversion means is connected to the second serial / parallel conversion means by wireless communication. The image photographing processing system according to claim 2 or 3,   The main body includes a detection unit that detects whether the imaging unit has the synchronization unit, and an operation clock switching unit that switches a speed of an operation clock of a control signal supplied to the imaging unit based on a detection result of the detection unit. The image photographing processing system according to claim 1, further comprising: In an image photographing processing system including an image pickup unit and an image pickup unit having a peripheral circuit thereof and a main body unit,
The main body includes a first parallel / serial means for serially converting parallelized control signals output to the image sensor and its peripheral circuits, and a control signal serially converted by the first parallel / serial means. First output means for outputting to the element and its peripheral circuit, first serial / parallel conversion means for generating parallel image data from the serial signal input from the imaging unit, and restoring the image data clock from the serial signal Image data clock restoring means, and sampling means for sampling the image data generated by the first serial / parallel conversion means at the timing of the image data clock restored by the image data clock restoring means,
The imaging unit includes second serial / parallel conversion means for converting the serially converted control signal output by the first output means, and a reference for the imaging element and its peripheral circuit from the serially converted control signal. Reference clock generating means for generating a clock; second parallel serial means for serially converting parallelized image data at a frequency obtained by multiplying an image data clock generated based on the reference clock; and the second An image photographing processing system comprising: second output means for outputting image data serialized by parallel-serial means to the main body as the serial signal. In an image capturing processing system comprising a timing generator, an image sensor having an image sensor and its peripheral circuit, and a main body having a digital camera function IC,
The main body is
A reference clock signal supplied to the timing generator is divided by a predetermined value, and this signal is used as a transfer clock to serialize a vertical synchronization signal, a horizontal synchronization signal, and a control signal for the peripheral circuit of the image sensor. Means for outputting to the imaging unit;
Means for receiving serialized image data from the imaging unit, parallelizing the image data, and inputting an image data timing signal restored based on the received image data to the digital camera function IC; With
The imaging unit
A signal obtained by dividing the reference clock signal input from the main body is restored, and the restored signal is multiplied by a predetermined value to create a synchronized clock signal synchronized with the reference clock signal, Means for synchronizing the synchronizing clock signal with the vertical synchronizing signal and the horizontal synchronizing signal and supplying these synchronized signals to the timing generator;
An image photographing processing system comprising: means for using the image data timing signal output by the timing generator as a transfer clock to the main body, serializing the image data, and outputting the serial data to the main body. In a control program executed in an image photographing processing system including an image pickup unit having an image pickup element and its peripheral circuit and a main body unit having a control means for controlling the image pickup element and its peripheral circuit
A low-speed clock module that outputs a control signal of an operation clock slower than the frequency of the reference clock of the image sensor and its peripheral circuit to the image sensor and its peripheral circuit, and image data output from the image sensor and its peripheral circuit Restoring the transfer clock, causing the main body to execute the input module that inputs the restored image data transfer clock to the control means;
A synchronization module that multiplies the low-speed operation clock of the control signal by an arbitrary magnification to make the same frequency as the reference clock, and outputs the control signal of the operation clock of the same frequency to the image sensor and its peripheral circuit, An image data transfer clock and image data output module for outputting image data output from an image pickup device and its peripheral circuit to the main body unit, and a control program for causing the image pickup unit to execute. In a control program executed by an image capturing processing system including an image capturing unit and an image capturing unit having a peripheral circuit and a main body unit,
A first parallel / serial module for serially converting a parallelized control signal output to the image sensor and its peripheral circuit, and a control signal serially converted by the first parallel / serial module to the image sensor and its peripheral circuit A first output module for outputting to the first image, a first serial / parallel conversion module for generating parallel image data from the serial signal input from the imaging unit, and an image data clock recovery for recovering an image data clock from the serial signal A module and a sampling module that samples the image data generated by the first serial / parallel conversion module at the timing of the image data clock recovered by the image data clock recovery module;
A second serial-to-parallel conversion module that converts the serially converted control signal output from the first output module into parallel, and a reference that generates a reference clock for the image sensor and its peripheral circuits from the serially converted control signal A clock generation module, a second parallel serial module that serially converts parallelized image data at a frequency obtained by multiplying an image data clock generated based on the reference clock, and the second parallel serial module. A control program that causes the imaging unit to execute a second output module that outputs serialized image data as the serial signal to the main body. In a control program executed by an image capturing processing system including an image capturing unit having a timing generator, an image sensor and its peripheral circuit, and a main body unit having a digital camera function IC,
A reference clock signal supplied to the timing generator is divided by a predetermined value, and this signal is used as a transfer clock to serialize a vertical synchronization signal, a horizontal synchronization signal, and a control signal for the peripheral circuit of the image sensor. A module for outputting to the imaging unit;
A module that receives serialized image data from the imaging unit, parallelizes the image data, and inputs an image data timing signal restored based on the received image data to the digital camera function IC; To the main body,
A signal obtained by dividing the reference clock signal input from the main body is restored, and the restored signal is multiplied by a predetermined value to create a synchronized clock signal synchronized with the reference clock signal, A module that synchronizes the synchronization clock signal with the vertical synchronization signal and the horizontal synchronization signal and supplies these synchronized signals to the timing generator;
A control program that uses the image data timing signal output from the timing generator as a transfer clock to the main unit, and causes the imaging unit to execute a module that serializes the image data and outputs it to the main unit. .

Images