KR20160027870A - Data interface and data transmit method - Google Patents

Abstract

The present invention provides data interface, and a method for transmitting data. The data interface comprises: a formatter for generating a first bit set including a first bit which is included in first image data and a third bit which is included in second image data, and generating a second bit set including a second bit which is included in the first image data and is an upper bit of the first bit, and a fourth bit which is included in the second image data, and is an upper bit of the third bit; a first serializer for serializing the first bit set; a second serializer for serializing the second bit set; a first output driver for converting the serialized first bit set into a first differential signal; a second output driver for converting the serialized second bit set into a second differential signal; and a clock generator for generating a plurality of clock signals which are transmitted to the formatter, the first and second serializers, and the first and second output drivers.

Description

[0001] The present invention relates to a data interface and a data transmission method,

The present invention relates to a data interface and a data transmission method.

The image pickup apparatus includes an image sensor. An image sensor is one of the semiconductor elements that convert optical information into an electrical signal. Such an image sensor can transmit optical information converted into an electric signal to an image signal processor (ISP). A data interface may be used in the process of transmitting optical information.

The data interface includes a serializer deserializer (SerDes), which serializes the data to transmit over a transmission channel and deserializes the received serialized data. In addition, the data interface restores the frequency of the received data using a clock data recovery (CDR) circuit and operates the sampler circuit with the clock of the recovered frequency. Therefore, the receiving side can continuously receive data transmitted from the transmitting side operating at a frequency different from the reference clock frequency used as a reference at the receiving side. However, recently, the amount of data to be transmitted by the image sensor has been rapidly increased, so that power consumption has been increased. As a result, there has been a problem such as heat generation local image quality shading and battery life reduction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data interface capable of minimizing the number of CDRs in a data interface and reducing power consumption.

Another object of the present invention is to provide a data transmission method capable of reducing the power consumption by minimizing the number of CDRs in a data interface.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a data interface for generating a first bit set including a first bit included in first image data and a third bit included in second image data, And a second bit set included in the first image data and including a second bit which is an upper bit of the first bit and a fourth bit which is included in the second image data and is an upper bit of the third bit, A first serializer for serializing the first bit set, a second serializer for serializing the second bit set, a second serializer for converting the serialized first bit set into a first differential signal, 1 output driver, a second output driver for converting the serialized second set of bits to a second differential signal, and a second output driver for converting the formatter, the first and second serializers, Of the clock signal And a clock generator (clock generator) that generates.

In some embodiments of the present invention, the first differential signal may be transmitted on an HD (High Density) channel, and the second differential signal may be transmitted on a LD (Light Density) channel.

In some embodiments of the present invention, if there is no transition in the first or second bit set received from the formatter, the pre-logic that transforms the first or second set of bits into a bit set comprising one or more transitions (pre-logic).

In some embodiments of the present invention, the first and second image data comprise N (N is an even number) bits, wherein the first bit set is a lower N / 2 bit of the first and second image data And the second bit set may comprise the upper N / 2 bits of the first and second image data.

In some embodiments of the present invention, the formatter converts the first and second image data to a third bit set, wherein the third bit set is included in the first image data and the first bit and the second A fifth bit located between the bits and a sixth bit included in the second image data and located between the third bit and the fourth bit.

In some embodiments of the present invention, a third serializer for serializing the third bit set and a third output driver for converting the serialized third bit set to a third differential signal may be further included.

In some embodiments of the present invention, the formatter comprises: a plurality of toggle counters for counting the number of transitions included in the upper and lower bits of the first and second image data; A comparator for comparing the upper bit with the lower bit and comparing the number of transitions included in the upper bit and the lower bit with a transition of the upper bit and the lower bit to the first bit set, A plurality of multiplexers for assigning a small number of bits to the second bit set and a dummy bit generator for generating a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set, ).

In some embodiments of the present invention, the first bit set and the second bit set may further include a first dummy bit and a second dummy bit respectively generated in the dummy bit generator.

According to an aspect of the present invention, there is provided a data transmission method including: a first bit set including a first bit included in first image data and a third bit included in second image data; A second bit included in the first image data and being a higher bit of the first bit and a fourth bit being included in the second image data and being a higher bit of the third bit, The first and second sets of bits are received on a second channel, the first and second bit sets are sampled based on the clock signals provided by the clock generator, and the multi-phase clocks provided by the clock data recovery circuit (CDR circuit) Signal to adjust the sampling timing of each of the first and second bit sets.

In some embodiments of the present invention, a first bit set is generated that includes a first bit included in the first image data and a third bit included in the second image data, and the first bit set included in the first image data, Generating a second bit set comprising a second bit that is an upper bit of a first bit and a fourth bit that is included in the second image data and is an upper bit of the third bit, Serializing the 2-bit set, and converting the serialized first bit set and the second bit set into a first differential signal and a second differential signal.

The details of other embodiments are included in the detailed description and drawings.

1 is a block diagram of an image pickup apparatus according to an embodiment of the present invention.
2 is a block diagram of a data interface according to one embodiment of the present invention.
3 is a diagram for explaining the frequency of transitions of an input signal of a data interface according to some embodiments of the present invention.
4 is a diagram for explaining a data format changing method of a data interface according to some embodiments of the present invention.
5 is a conceptual diagram illustrating functions of a clock data recovery circuit of a data interface according to some embodiments of the present invention.
6 is a timing chart for explaining a sampling operation of the sampler according to some embodiments of the present invention.
7 is a block diagram of a data interface according to another embodiment of the present invention.
8 is a block diagram for explaining the structure of the prelogic circuit of FIG.
9 is a diagram for explaining the operation of the prelogic circuit of FIG.
10 is a block diagram of a data interface according to another embodiment of the present invention.
11 is a diagram for explaining a data format changing method of a data interface according to another embodiment of the present invention.
Figure 12 is a block diagram of a formatter in accordance with some embodiments of the present invention.
13 is a block diagram of an image pickup apparatus according to another embodiment of the present invention.
14 is a block diagram of an image pickup apparatus according to another embodiment of the present invention.
15 is a block diagram showing an example of application of the image pickup device according to the embodiments of the present invention to a computing system.
16 is a block diagram illustrating an example of an interface used in the computing system of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of the components shown in the figures may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout the specification and "and / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms " comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements in addition to the stated element.

Although the first, second, etc. are used to describe various elements or components, it is needless to say that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, it is needless to say that the first element or the constituent element mentioned below may be the second element or constituent element within the technical spirit of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a data interface according to an embodiment of the present invention and an image pickup device including the same will be described with reference to FIGS. 1 to 6. FIG.

1 is a block diagram of an image pickup apparatus according to an embodiment of the present invention.

1, an image capturing apparatus 10 according to an embodiment of the present invention includes an image sensor 11 (Image Sensor), an image signal processor 13 (image signal processor), data interfaces 1 to 3 ).

The image sensor 11 detects light and converts the electrical signal into an electrical signal, converts the electrical signal into an analog signal or a digital signal, and performs a filtering function for basic image processing (for example, .

The image sensor 11 may be variously changed according to the type of image sensor cells. For example, the image sensor 11 may include a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Semiconductor) image sensor. The CMOS image sensor uses a CMOS technology that can simultaneously integrate a control circuit (a control circuit) and a signal processing circuit (a signal processing circuit), which are peripheral circuits, to make MOS transistors as many as the number of pixels, A switching method can be adopted. The CMOS image sensor is composed of a photodiode including a plurality of image sensor cells and a plurality of MOS transistors. Basically, the CMOS image sensor converts light incident from front and rear of the image sensor chip, that is, visible light into an electrical signal, .

The CCD image sensor is a recording element that uses charge accumulation and transmission. The CCD image sensor can sequentially transfer the analog signal charge in a predetermined direction, and can convert an image into an electric signal by using the transfer function. Since the CCD image sensor has a relatively simple structure in which a thin oxide film is formed on a silicon substrate and a plurality of electrodes are arranged thereon, the CCD image sensor can include high-density integration and a low power consumption volatile device.

The image signal processing unit 13 processes the digital signal received by the image sensor 11 and converts it into an electrical signal suitable for a control unit (not shown) of the camera module, such as conversion of a color format, And can perform the function of transmitting and transmitting. The image signal processing unit 13 can output the processed image data to the display unit via the interface device. The image signal processing unit 13 can adjust the gain correction and the white balance of the light amount with respect to the electric signal output from the image sensor 11. [ The image signal processing unit 13 may output the processed image data to a control unit in an application processor.

The data interfaces 1 to 3 may include a transmitting unit 100 (Tx), a receiving unit 200 (Rx), and a channel 300 (channel). The transmitting unit 100 may transmit the digital signal output from the image sensor 11 to the receiving unit 200 using a plurality of channels included in the channel 300. A detailed description thereof will be given later.

2 is a block diagram of a data interface according to one embodiment of the present invention.

Referring to FIG. 2, a data interface 1 according to an embodiment of the present invention includes a transmitter 100, a receiver 200, and a channel 300. The transmitter 100 includes a formatter 110, a serializer 121, a data path 131, a data path 131, output drivers 141 and 143, A clock generator 180 (CLK_GEN), and a PLL (Phase Locked Loop) circuit 190.

The formatter 110 may change the format of the input bit set. Specifically, the formatter 110 receives a plurality of bit sets each including N (N is a natural number equal to or greater than 2) bits, and outputs a plurality of bit sets each including a LSB (Least Significant Bit) 1 bit set and a second bit set including the MSB (Most Significant Bit) of each of the plurality of bit sets.

For example, when the formatter 110 receives the bit set of the first pixel including the N bits and the image signal of the second pixel, the lower N / 2 bits of the bit set of the first and second pixels are And a second bit set comprising the upper N / 2 bits of the bit set of the first and second pixels. However, the present invention is not limited to this, and it is also possible to use the input three image signals to generate a first bit set including a least significant bit of each bit set, a second bit set including a most significant bit of each bit set , A third bit set may be generated that includes the bits located in the middle of each bit set. A detailed description thereof will be described later.

The first bit set generated by the formatter 110 may have a larger number of transitions than the second bit set. For example, the initial image may have a plurality of pixel data including RGB values that gradually change between adjacent pixels. Gradually varying pixel data may form relatively few transitions relative to the MSB bits, and relatively many transitions to the LSB bits. That is, when the bit changes from 1 to 0 or from 0 to 1, the transition corresponding to the first bit set may exist more in the first bit set than the second bit set. Therefore, the channel through which the first bit set moves becomes a high density (HD) channel with many transitions, and the channel through which the second bit set moves becomes a low density (LD) channel with a relatively small transition.

On the other hand, the transition pattern of LSB bits and MSB bits may be changed by the initial image data. For example, the initial image may have a check board pattern with a large number of edges, and the RGB data may change abruptly on the edges of the check board pattern. The abrupt change in RGB data on the edges may cause the transition of the MSB bits to be greater than the transition of the LSB bits. Therefore, in another embodiment of the present invention, the LD channel can transmit a bit set having a smaller transition from the first bit set and the second bit set, and the HD channel can transmit a bit having many transitions among the first bit set and the second bit set You can transfer the set.

The formatter 110 may be connected to the first serializer 121 and the second serializer 123. The first bit set including the LSB generated in the formatter 110 may be transmitted to the first serializer 121 and the second bit set including the MSB may be transmitted to the second serializer 123 have.

A plurality of toggle counters (not shown) for counting the number of transitions contained in the upper bit set and the lower bit set of the image data to select more or fewer transitions based on the first bit set and the second bit set , A comparator (not shown) for comparing the number of transitions included in the upper bit set and the lower bit set, and a comparator (not shown) for assigning the transition set to the first bit set and the less transition bit set to the second bit set And a plurality of dummy bit generators (not shown) for generating dummy bits indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set can do. However, the present invention is not limited thereto, and a detailed description thereof will be described later with reference to FIG.

There may exist free logic (151 and 153 in FIG. 7) between the formatter 110 and the first serializer 121 or between the formatter 110 and the second serializer 123. A detailed description thereof will be described later.

The serializers 121 and 123 may include a first serializer 121 and a second serializer 123. The serializers 121 and 123 can convert signals input in parallel into serial signals. For example, the serializers 121 and 123 can convert a signal input in parallel through ten lines into a serial signal output through two lines. That is, the serializers 121 and 123 are able to convert the ratio of input to output to 10: 2. At this time, the two output signals can be divided into an even signal and an odd signal and can be converted. However, the present invention is not limited thereto, and the ratio between input and output may be variously changed. For example, the ratio of input to output can be changed to n: m (where m is a natural number less than n)

The first and second serializers 121 and 123 may be connected to one clock generator 180. The first and second serializers 121 and 123 may receive the clock generated by one clock generator 180 and may convert the parallel signal into a serial signal using the clock. The first serializer 121 may be coupled to the first data path 131 and the second serializer 123 may be coupled to the second data path 133.

The data paths 131 and 133 may include a first data path 131 and a second data path 133.

The data paths 131 and 133 can allocate the serialized data and transfer the allocated serialized data to the output drivers 141 and 143. [ The data paths 131 and 133 can combine the plurality of signals received from the serializers 121 and 123 into one and transmit them to the output drivers 141 and 143. [ For example, the first and second serializers 121 and 123 may be configured to receive a signal from each received bit set to reduce the load associated with high-speed serial data transmission, By selecting an even signal and an even signal, each received bit set can be divided into an even signal and an odd signal. When the first data path 131 receives two signals including the even signal and the odd signal from the first serializer 121, the first data path 131 transmits the even signal and the odd signal to one signal And then transmitted to the first output driver 141. However, the present invention is not limited thereto. The second data path 133 may operate substantially the same as the first data path 131. [

The first and second data paths 133 may receive clocks generated by one clock generator 180 and may operate using the corresponding clocks. For example, the clock generator 180 may provide clocks of the same frequency to the first and second data paths 131 and 133. However, the present invention is not limited thereto.

The output drivers 141 and 143 amplify the data received by the first and second data paths 131 and 133 and then transmit the data through the channel 300. The output drivers 141 and 143 may include a first output driver 141 and a second output driver 143. [

The first output driver 141 may be coupled to the first data path 131 and the first channel 310 of the channel 300. The first output driver 141 may receive the first data (serial first bit set) received from the first data path 131 and may amplify and transmit the first data to the first channel 310. Similarly, the second output driver 143 may be coupled to the second data path 133 and the second channel 320 of the channel 300. The second output driver 143 may receive the second data (serialized second set of bits) received from the second data path 133 and may amplify and transmit the second data to the second channel 320.

Although not explicitly shown in the figure, the data outputted from the data paths 131 and 133 are deserialized again, and an error which determines whether or not an error has occurred by comparing the deserialized signal with a signal input to the serializers 121 and 123 And may further include a checker (not shown). The error checker (not shown) may be connected to the output ends of the data paths 131 and 133 and the input terminals of the serializers 121 and 123. In addition, an error checker (not shown) may be connected for each channel. However, the present invention is not limited thereto.

The first data may have a larger number of transitions than the second data. Accordingly, the first channel 310 of the channel 300 to which the first data is transmitted corresponds to the HD channel, and the second channel 320 of the channel 300 to which the second data is transmitted corresponds to the LD channel.

The PLL circuit 190 is a frequency-side feedback circuit configured to always keep the frequency of the output signal constant in accordance with the reference signal. Specifically, the PLL circuit 190 matches the input signal with the reference frequency, the output signal, and the frequency. The PLL circuit 190 detects the phase difference between the input signal and the output signal and can output a frequency signal accurately fixed by controlling the voltage controlled oscillator (VCO). The PLL circuit 190 can perform a function of forcibly holding an accurate fixed point so that the phase of the periodic signal does not fluctuate. The PLL circuit 190 includes a reference channel The PLL circuit 190 of the transmitter 100 may share a reference signal with the PLL circuit 290 of the receiver 200. The PLL circuit 190 may be connected to the clock generator 180, A reference signal can be provided.

The clock generator 180 may transmit a clock signal to the serializers 121 and 123 and the data paths 131 and 133 based on the reference signal of the PLL circuit 190. Specifically, the clock generator 180 receives a reference signal from the PLL circuit 190 and can generate a clock for controlling the serializers 121 and 123 and the data paths 131 and 133. The generated clock may be passed to the first and second serializers 123, the first and second data paths 133, However, the present invention is not limited thereto.

The channel 300 may include a first channel 310, a second channel 320, and a reference channel 340. The first channel 310 may be coupled to the first output driver 141 of the transmitter 100 and the first input driver 211 of the receiver 200 to transmit first data including a first bit set . The second channel 320 may be coupled to the second output driver 143 of the transmitter 100 and the second input driver 213 of the receiver 200 to deliver second data including a second bit set . The reference channel 340 may be connected to the PLL circuit 190 of the transmission unit 100 and the PLL circuit 290 of the reception unit 200 to transmit the reference signal.

The first data may have a larger number of transitions than the second data. Accordingly, the first channel 310 to which the first data is transmitted corresponds to the HD channel, and the second channel 320 to which the second data is transmitted corresponds to the LD channel.

The first channel 310 and the second channel 320 may be formed of a pair of lines. This is because the first channel 310 and the second channel 320 use a differential channel transmission scheme. In the differential channel transmission method, a positive signal and a negative signal are generated for one transmission signal, and a positive signal is transmitted to one of the pair of lines and a negative signal is transmitted to the other Signal is transmitted. The input drivers 211 and 213 of the receiving end can recover the original transmission signal using the deviation of the two signals. Since the differential channel transmission method utilizes the deviation of the two signals, the differential channel transmission method is more resistant to noise and interference than a case of transmitting signals in a single line.

Thus, the output drivers 141 and 143 can generate a clock edge modulated signal for differential channel transmission. Specifically, a channel driver (not shown) may generate a positive signal and a negative signal for one transmission signal and supply the same to the channel 300. For example, the first output driver 141 generates a positive signal and a negative signal for the first data that includes the first bit set, and the positive signal is the HDa channel of the first channel 310 And the negative signal may be transmitted through the HDb channel of the first channel 310. [ The second output driver 143 may also transmit to the second channel 320 in the same manner. However, the present invention is not limited thereto, and the first channel 310 and the second channel 320 may be formed as a single channel.

The receiver 200 includes input drivers 211 and 213 (reciever), samplers 221 and 223 (sampler), deserializers 231 and 233 (deserializer), a clock data recovery circuit 240 (CDR), a synchronization unit 250, a Reformatter 260, and a PLL circuit 290.

The input drivers 211 and 213 may include a first input driver 211 connected to the first channel 310 and a second input driver 213 connected to the second channel 320. The input drivers 211 and 213 may be connected to the samplers 221 and 223. Specifically, the first input driver 211 receives the first differential signal transmitted through the first channel 310 and transmits the first differential signal to the first sampler 221, and the second input driver 213 receives the first differential signal transmitted through the second channel 320, and transmit the second differential signal to the second sampler 223. The second sampler 223 may receive the second differential signal. The input drivers 211 and 213 can generate a single signal by combining a positive signal and a negative signal transmitted according to a differential channel transmission scheme into a single signal have. Each of the first and second differential signals may include a pair of positive and negative signals. The input drivers 211 and 213 can convert the received differential signal into data for providing a bit set to the samplers 221 and 223.

The input drivers 211 and 213 may include a preamplifier (preamplifier) (not shown) or an equalizer (not shown). The preamplifier (not shown) and the equalizer (not shown) compensate the data size and delay characteristics of the serial data stream received through the channel 300 and output the compensated data to the first and second samplers 221 and 223 . Specifically, a preamplifier (not shown) and an equalizer (not shown) receive a serialized data stream through a transmission line, amplify the voltage of the received data, equalize the amplified data to generate jitter of received data, The distortion of the data signal due to the Inter Symbol Interference (ISI) can be compensated. However, the present invention is not limited thereto.

The samplers 221 and 223 may include a first sampler 221 and a second sampler 223. The samplers 221 and 223 can sample the data received from the input drivers 211 and 213 based on the sampling clock provided by the clock generator 208. The first and second samplers 221 and 223 may obtain serialized data (e.g., sampled data) through sampling from the received data. The first sampler 221 and the second sampler 223 may share one clock data recovery circuit 240.

The first sampler 221 may receive the first reception data from the first input driver 211. [ The first sampler 221 may sample the first received data using the clock input from the clock generator 280 and output the first sampled data.

The second sampler 223 can receive the second received data from the second input driver 213. [ The second sampler 223 may sample the second received data using the clock input from the clock generator 280 and output the second sampled data.

The deserializer 231, 233 may include a first deserializer 231 and a second deserializer 233. The first deserializer 231 may convert the first sampling data generated by the first sampler 221 into the first deserialized data. The ratio of conversion from the first sampling data to the first deserialization data may be 1: n. The output of the first sampler 221 may be coupled to the first deserializer 231. The output signal of the first deserializer 231 may be transmitted to the clock data recovery circuit 240.

The second sampler 223 may be coupled to the second deserializer 233. The second deserializer 233 may convert the second sampling data generated by the second sampler 223 into second deserialized data. The ratio of conversion from the second sampling data to the second deserialization data may be 1: n. The output of the second sampler 223 may be coupled to the synchronization unit 250. The output signal of the second deserializer 233 may be passed to the synchronization unit 250.

The clock data restoration circuit 240 outputs the output signal of the first deserializer 231 to the sampling clock phase of the first sampler 221 based on the edge information included in the output signal of the first deserializer 231 Can be received as phase feedback to adjust. The first sampler 221 can sample the first received data while maintaining the proper sampling timing by repeating the above-described series of feedback processes.

The second sampler 223 may share the first sampler 221 and the clock data recovery circuit 240. The sampling clock for determining the sampling timing of the second sampler 223 can be adjusted by the phase feedback of the clock data recovery circuit 240 according to the output signal of the first deserializer 231.

The clock data recovery circuit 240 may provide the first phase feedback to the clock generator 280 based on the edge information of the first deserialized data provided by the first deserializer 231. [ The clock generator 280 may adjust the sampling timing of the first sampler 221 and the second sampler 223 using the first phase feedback. The clock data recovery circuit 240 provides the second phase feedback to the clock generator 280 based on the edge information of the second deserialized data provided by the second deserializer 233 or the synchronization unit 250 . The clock generator 280 may adjust the sampling clock phase of the first sampler 221 and the second sampler 223 using the second phase feedback. However, the present invention is not limited thereto.

The clock generator 280 generates a clock signal based on a signal from the PLL circuit 290 of the receiver 200 and a reference clock generated using the feedback provided from the clock data recovery circuit 240, 221 and the second sampler 223, as shown in FIG. In addition, the clock generator 280 may generate a clock provided to the first deserializer 231 and the second deserializer 233.

The clock generator 280 may include a phase detector (not shown), a PI controller (not shown), and a phase interpolator (not shown). However, the present invention is not limited thereto.

The phase interpolator (not shown) may adjust the phase of the clock input to each sampler 221, 223 by providing a multi-phase clock to the clock generator 280. For example, the phase interpolator receives four clocks of 0 degrees / 90 degrees / 180 degrees / 270 degrees from the PLL circuit 290, The phase of four clocks of 0 degrees / 90 degrees / 180 degrees / 270 degrees can be increased or decreased. However, the present invention is not limited thereto.

The synchronization unit 250 may provide phase feedback to the clock data recovery circuit 240 using the output signal of the second deserializer 233 so that the sampling timing of the second sampler 223 And the distortion of data reconstructed from the second deserializer 233 can be adjusted. The synchronization unit 250 may communicate with the clock data recovery circuit 240. That is, the synchronization unit 250 compares the output timings of the restored data from the clock data restoration circuit 240 and the second deserializer 233, and restores the restored data from the synchronization unit 250 and the clock data restoration circuit 240 The distortion of the output of the data can be controlled. The clock data restoration circuit 240 can adjust the sampling clock by comparing the output timings of the deserializers 231 and 233 based on the phase feedback of the first deserializer 231 and the synchronization unit 250.

As a result, the formatter 110 of the transmission unit 100 of the data interface 1 according to the embodiment of the present invention receives the first and second image data from the image sensor 11, 2 image data into a first or a second bit set. Wherein the first bit set includes a first bit that is a lower bit included in the first image data and a third bit that is a lower bit included in the second image data, A second bit included in the first image data and being a high-order bit of the first bit, and a fourth bit included in the second image data and being a high-order bit of the third bit.

The first serializer 121 serializes the first bit set received from the formatter 110 and the second serializer 123 serializes the second bit set received from the formatter 110, .

The first channel 310 of the channel 300 then transmits the serialized first bit set to the first input driver 211 of the receiver 200 using the differential channels 311 and 313, The channel 320 may transmit the serialized second set of bits to the second input driver 213 of the receiver 200 using the differential channels 321 and 323.

The first sampler 221 of the receiver 200 samples the first bit set received from the first input driver 211 and the second sampler 223 receives the first bit set from the second input driver 213 The second set of bits received can be sampled.

The first deserializer 231 parallelizes the first bit set sampled from the first sampler 221 and the second deserializer 233 parallelizes the first bit set sampled from the second sampler 223, The second bit set can be parallelized.

The clock data recovery circuit 240 and the clock generator 280 adjust the clocks input to the first and second samplers 221 and 223 using the output of the first deserializer 231, The sampling timing of the first and second bit sets can be adjusted. At the same time, the synchronization unit 250 provides feedback to the clock data recovery circuit 240 on the basis of the output of the second deserializer 233 to generate first and second image data for restoring the first and second image data, The distortion of the second bit set can be adjusted.

The reformatter 260 may then extract the first and second image data from the first and second bit sets. The reformatter 260 may be coupled to the synchronization unit 250 and the clock data recovery circuit 240. The reformatter 260 receives the first bit set and the second bit set included in the outputs of the first and second samplers 221 and 223 from the synchronization unit 250 and the clock data recovery circuit 240, The first and second image data can be extracted by moving the operations performed by the formatter 110 in the reverse order. That is, the formatter 110 and the reformer 260 can perform complementary functions.

Then, the first and second image data output from the reformer 260 can be transmitted to the image processing apparatus 13. However, the present invention is not limited thereto.

The data interface 1 according to the present invention can be applied to a data communication system having a sampler and a clock data restoration circuit. However, the data interface 1 according to the present invention is not limited to a data communication system having a serializer-deserializer. In a data communication system having samplers 221 and 223 and a clock data recovery circuit 240, It is needless to say that the present invention is also applicable to the case where the devices 121 and 123 and / or the deserializers 121 and 123 are not included.

3 is a diagram for explaining the frequency of transitions of an input signal of a data interface according to some embodiments of the present invention.

Referring to FIG. 3, FIG. 3 is a graph showing the frequency of transition of a 10-bit input signal to data interfaces 1 and 2 according to some embodiments of the present invention.

According to the graph, assuming that the frequency of the transition of the least significant bit of the input signal is 1, the frequency of the transition of the 6th bit of the input signal is about 0.031. That is, assuming that the number of transitions of the least significant bit is 100, the number of transitions of the sixth bit may occur about 3 times. The number of transitions can be exponentially reduced from lower bits to higher bits. For example, the initial image may have a plurality of pixel data including RGB values that gradually change between adjacent pixels. Gradually varying pixel data may form relatively few transitions relative to the MSB bits, and relatively many transitions to the LSB bits.

On the other hand, the transition pattern of LSB bits and MSB bits may be changed by the initial image data. For example, the initial image may have a check board pattern with a large number of edges, and the RGB data may change abruptly on the edges of the check board pattern. The abrupt change in RGB data on the edges may cause the transition of the MSB bits to be greater than the transition of the LSB bits.

Therefore, the LD channel can transmit a bit set having a small transition among the first bit set and the second bit set, and the HD channel can transmit a bit set having many transitions from the first bit set and the second bit set. On the basis of the first bit set and the second bit set, the formatter 110 includes a plurality of registers (not shown), a set of upper and lower bits of the image data A plurality of toggle counters (not shown) for counting the number of transitions included, a comparator (not shown) for comparing the number of transitions contained in the upper bit set and the lower bit set, and a comparator A plurality of multiplexers (not shown) for assigning a bit set having a small transition to a second bit set and a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set And a plurality of dummy bit generators (not shown) for generating the dummy bits. However, the present invention is not limited thereto, and a detailed description thereof will be described later with reference to FIG.

4 is a diagram for explaining a data format changing method of a data interface according to some embodiments of the present invention.

4, the formatter 110 converts the received first image data P1 and the first image data P2 into a first bit set P1 'and a second bit set P2' A data formatting process can be performed.

The first bit set P1 'includes a first bit included in the first image data P1 and a third bit included in the second image data P2, and the second bit set P1' P2 ') includes a second bit which is included in the first image data (P1) and which is an upper bit of the first bit and a fourth bit which is included in the second image data (P2) and which is an upper bit of the third bit . ≪ / RTI >

For example, when the first image data P1 and the second image data P2 are composed of 10 bits, the lower five bits of the first image data P1 and the lower five bits of the second image data P2 Bits to form a first bit set P1 '. In the same way, the upper 5 bits of the first image data P1 and the upper 5 bits of the second image data P2 can be combined to form the second bit set P2 '.

Since the first bit set P1 'is composed of the lower five bits, it can include a larger number of transitions than the second bit set P2'. Accordingly, the first channel 310 transmits a first bit set P1 'of high density and the second channel 320 transmits a second bit set P2' of an LD (high density) .

The first bit set P1 'may not perform additional lind-coding because a sufficient transition is ensured. When line coding is performed, a separate additional bit for decryption is required. Therefore, when line coding is not performed, it is possible to further secure a band width of an additional bit required for line coding. For example, when a 10-bit input signal is line-coded, a 2-bit additional bit is required. In this case, when the line coding is eliminated, an additional bandwidth of about 20% can be ensured.

Since the frequency of the transition is considerably lower than the frequency of the first bit set P1 ', the second bit set P2' may be stored in the first bit set P1 ' It may suffice to perform sampling using the clock data restoration circuit 240 used and then synchronize the clock.

Accordingly, it is possible to share one clock data restoration circuit 240 in two channels without using the clock data restoration circuit 240 for each channel. Thus, the size and complexity of the data interface can be reduced. In addition, since the clock data recovery circuit 240 consumes a large amount of power, when the number of the clock data recovery circuits 240 used is reduced, the power and cost used in the clock data recovery circuit 240 are reduced .

Further, in the case of the elements such as the second serializer 123, the second deserializer 233, the second sampler 223 connected to the channel through which the second bit set P2 'passes, .

On the other hand, as mentioned above, the transition pattern of LSB bits and MSB bits may be changed by the initial image data. The LD channel may transmit a bit set having a smaller transition among the first bit set and the second bit set, and the HD channel may transmit a bit set having a transition from the first bit set and the second bit set. On the basis of the first bit set and the second bit set, the formatter 110 includes a plurality of registers (not shown), a set of upper and lower bits of the image data A plurality of toggle counters (not shown) for counting the number of transitions included, a comparator (not shown) for comparing the number of transitions contained in the upper bit set and the lower bit set, and a comparator A plurality of multiplexers (not shown) for assigning a bit set having a small transition to a second bit set and a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set And a plurality of dummy bit generators (not shown) for generating the dummy bits. A detailed description thereof will be given later in Fig.

5 is a conceptual diagram illustrating functions of a clock data recovery circuit of a data interface according to some embodiments of the present invention.

Referring to FIG. 5, the samplers 221 and 223 may sample input reception data to obtain data at a specific instant. The sampling timings of the samplers 221 and 223 can be adjusted by the sampling clocks input to the samplers 221 and 223. The arrows indicate the sampling points of the samplers 221 and 223.

A plurality of transitions may occur in an input signal. The samplers 221 and 223 can perform sampling a plurality of times in one cycle (T) according to an oversampling scheme. For example, the samplers 221 and 223 may perform sampling eight times on the basis of the multi-phase clock provided by the clock generator 280. However, the present invention is not limited thereto.

The clock data recovery circuit 240 receives the phase difference information from the samplers 221 and 223 and / or the deserializer 231 and 233, analyzes the phase difference information, Can be adjusted. The clock data recovery circuit 240 may transmit a feedback signal to the clock generator 280 so that the sampling timings of the samplers 221 and 223 may be at the center of one period. Q denotes the middle between the edges of the received data. The clock generator 280 may generate a multi-phase clock based on the received feedback signal. However, the present invention is not limited thereto.

6 is a timing chart for explaining a sampling operation of the sampler according to some embodiments of the present invention.

6, the clock data recovery circuit 240 synchronizes the output of the restored data from the first channel 310 (e.g., the HD channel) and the second channel 320 (e.g., the LD channel) And may provide timing feedback to the synchronization unit 250. < RTI ID = 0.0 > In order to synchronize the output of the recovered data, the synchronization unit 250 may adjust the skew of the output of the second deserializer 233. A circuit delay may occur in the output of the first deserializer 231 in the process of reaching the reformer 260 through the clock data recovery circuit 240. The synchronization unit 250 can adjust the distortion from the second deserializer 231 to the reformer 260 based on the timing feedback from the clock data recovery circuit 240.

7 is a block diagram of a data interface according to another embodiment of the present invention. 8 is a block diagram for explaining the structure of the prelogic circuit of FIG. 9 is a diagram for explaining the operation of the prelogic circuit of FIG. For the sake of convenience of description, the same elements as those of the above-described embodiment will be described below with the exception of duplicate descriptions.

7, the data interface 2 according to another embodiment of the present invention includes a transmitter 100, a receiver 200, and a channel 300, and the transmitter 100 includes pre-logic 151 and 153 ). ≪ / RTI > The receiving unit 200 may further include post logics 261 and 263. The data interface 2 according to another embodiment of the present invention can be formed substantially the same as the data interface 1 described with reference to Fig.

The transmitter 100 may include a formatter 110, free logic 151 and 153, serializers 121 and 123, data paths 131 and 133, and output drivers 141 and 143. The formatter 110 receives the first and second image data from the image sensor 11 and can convert the first and second image data into a first or a second bit set. The first bit set may include a first bit included in the first image data and a third bit included in the second image data. The second bit set may include a second bit that is included in the first image data and is a higher bit of the first bit and a fourth bit that is included in the second image data and is a higher bit of the third bit have. For example, when the first and second image data have N (N is even) bits, the first bit set includes the lower N / 2 bits of the first and second image data, The second set of bits may comprise the upper N / 2 bits of the first and second image data. However, the present invention is not limited to this. Even when the first and second image data have an odd number of bits, the upper bit and the lower bit may be divided and applied in the same manner.

8 through 9, the pre-logic 151 and 153 may be configured to convert the first or second bit set into one or more bits if there is no transition in the first or second bit set received from the formatter 110. [ It can be converted into a bit set including a transition. The pre-logic 151 and 153 include a first pre-logic 151 that operates when there is no transition in the first bit set and a second pre-logic 153 that operates when there is no transition in the second bit set can do. The first free logic 151 and the second free logic 153 may be connected to the same formatter 110. The first prelogic 151 may receive a first bit set from the formatter 110 and the second prelogic 153 may receive a second bit set from the formatter 110 that has fewer transitions than the first bit set, Lt; / RTI > However, the present invention is not limited thereto.

The pre-logic 151, 153 may include an inverter 1510 (invertor) and NOR gates 1511-1519.

The inverter 1510 inverts the least significant bit D0 of the first bit set or the second bit set and the NOR gates 1511 to 1519 receives two consecutive bits as inputs and outputs the least significant bit D0 ) To the upper bits D1 to D9. For example, referring to FIG. 8, in the case of the pre-logic 151 and 153 receiving 10 bits as an input, one inverter 1510 and nine NOR gates 1511 to 1519 may be included. The inverter 1510 inverts the D0 bit, and the first NOR gates 1511 to 1519 receive the D0 bit and the D1 bit as inputs and generate the output of the D1 'bit. Similarly, the second NOR gate 1511 receives the D1 bit and the D2 bit as inputs and generates an output of D2 'bits.

Referring to FIG. 9, the pre-logic 151, 153 monitors the bit sets entering the formatter 110. (N + 1) th bit set B1 (N + 1), B2 (N + 1)) is input to the Nth bit set B1 If inputs without a transition are input in succession, the pre-logic (151, 153) can operate. For example, the input of '0000000000' or '1111111111' is input to the Nth bit set B1 (N), B2 (N) The pre-logic 151 and 153 can operate when the same '0000000000' or '1111111111' input is input to the (N + 1) th bit set B1 (N) and B2 (N). In this case, the inverter 1510 of the pre-logic 151 and 153 inverts the least significant bit of the (N + 1) th bit set B1 (N + 1) and B2 (N + 1) . If a signal with no transition continues to be received, sampling timing may be out of order or the edge may be missed when sampling is performed at the receiving end. The pre-logic 151 and 153 are devices for transforming signals B1 '(N + 1) and B2' (N + 1) containing a transition to prevent this. The pre-logic 151 and 153 operate and the converted bit can be restored to the original signal through inverse transformation at the receiving end.

Referring again to FIG. 7, the first serializer 121 is coupled to the first pre-logic 151 and may serialize the first bit set received from the first pre-logic 151. [ The second serializer 123 may be coupled to the second prelogic 153 and may serialize the second bit set received from the second prelogic 153.

The data paths 131 and 133 may include a first data path 131 and a second data path 133. The datapaths 131 and 133 can transfer the received serialized data to the driver. The first serializer 121 may be coupled to the first data path 131 and the second serializer 123 may be coupled to the second data path 133.

The first and second serializers 121 and 123 and the first and second data paths 131 and 133 may receive the clock generated by one clock generator 280 and operate using the corresponding clock . For example, the clock generator 280 may provide clocks of the same frequency to the first and second data paths 133. However, the present invention is not limited thereto.

The output drivers 141 and 143 amplify the data received from the first and second data paths 131 and 133 and then transmit the data through the channel 300. The output drivers 141 and 143 may include a first output driver 141 and a second output driver 143. [ The first output driver 141 may be coupled to the first data path 131 and the first channel 310 of the channel 300. The first output driver 141 may receive the first data (serial first bit set) received from the first data path 131 and may amplify and transmit the first data to the first channel 310. Similarly, the second output driver 143 may be coupled to the second data path 133 and the second channel 320 of the channel 300.

The data interface 2 further adds the prelogic logic 151 and 153 to the data interface 1 according to an embodiment of the present invention so that the formatter 110 generates a first bit set and a second bit set It is possible to solve the problem that a signal without a transition is continuously transmitted in the course of transmission.

The reformer 260 may be coupled to the first and second post logic 261, 263. In addition, the reformer 260 may be coupled to the first and second synchronization units 251 and 253 (see FIG. 10), respectively. The post logic 261, 263 may perform the operations performed by the pre-logic 151, 153 in reverse order to extract the first and second bit sets from the first through third bit sets. However, the present invention is not limited thereto.

On the basis of the first bit set and the second bit set, the formatter 110 includes a plurality of registers (not shown), a set of upper and lower bits of the image data A plurality of toggle counters (not shown) for counting the number of transitions included, a comparator (not shown) for comparing the number of transitions contained in the upper bit set and the lower bit set, and a comparator A plurality of multiplexers (not shown) for assigning a bit set having a small transition to a second bit set and a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set And a plurality of dummy bit generators (not shown) for generating the dummy bits. A detailed description thereof will be given later in Fig.

10 is a block diagram of a data interface according to another embodiment of the present invention. 11 is a diagram for explaining a data format changing method of a data interface according to another embodiment of the present invention. For the sake of convenience of description, the same elements as those of the above-described embodiment will be described below with the exception of duplicate descriptions.

Referring to FIGS. 10 and 11, the data interface 3 according to another embodiment of the present invention may be formed substantially the same as the data interface 1 described with reference to FIG. The data interface 3 according to another embodiment of the present invention includes a transmitting unit 100, a receiving unit 200 and a channel 300. The transmitting unit 100 includes a third serializer 125, Paths 131 and 133, and third output drivers 141 and 143, respectively.

The formatter 110 may convert the first and second image data into first to third bit sets. The first bit set may include a first bit included in the first image data and a third bit included in the second image data. The second bit set may include a second bit that is included in the first image data and is a higher bit of the first bit and a fourth bit that is included in the second image data and is a higher bit of the third bit have. Wherein the third bit set comprises a fifth bit included in the first image data and located between the first bit and the second bit and a fifth bit included between the third bit and the fourth bit, Lt; RTI ID = 0.0 > 6 < / RTI > That is, the third bit set may be composed of the center bits of the input image signal.

Such conversion may be performed by combining two or more input image signals. For example, referring to FIG. 11, when the first through third image signals P1 through P3 of 12 bits are input, the first bit set P1 is made up of a combination of the least significant 4 bits, The bit set P2 may be a combination of the four most significant bits. The third bit set P3 may be a combination of the remaining four bits. The first bit set P1 'may include the most transitions among the set, and the second bit set P3' may include the fewest transitions. The third bit set P2 'may have a transition between the first bit set P1' and the second bit set P3 '.

Referring again to FIG. 10, the first bit set generated in the formatter 110 is transmitted to the first serializer 121, and the second bit set is transmitted to the second serializer 123. The subsequent process is the same as the data interface 1 described with reference to Fig. The third set of bits is passed to the third serializer 125. The third bit set is passed through the third data path 135 to the third output driver 145 after serialization. The third output driver 145 may transmit the third set of bits to the receiver 200 over the channel 300.

Although not explicitly shown in the figure, if the third bit set received from the formatter 110 does not have a transition, the transmitter 100 converts the third bit set into a bit set including one or more transitions And a third free logic (not shown).

The channel 300 may further include a third channel 330. The third channel 330 may comprise a pair of differential channels 331, 333.

The receiving unit 200 may further include a third input driver 215, a third sampler 225, a third deserializer 235, and a second synchronizing unit 253. The third input driver 215 may receive the signal transmitted through the third channel 330 and transmit it to the third sampler 225. The third input driver 215 may generate a signal by combining a pair of positive and negative signals transmitted in accordance with the differential channel transmission scheme.

The third sampler 225 may sample the signal received from the third input driver 215 according to the sampling timing. The third sampler 225 can obtain serialized data through sampling. The third sampler 225 may share one clock data recovery circuit 240 with the first and second samplers 221 and 223. The third sampler 225 may be coupled to the third deserializer 235.

The third deserializer 235 may convert the serialized sampled data of the third sampler 225 into parallel data of 1: n ratio to output the deserialized data.

The third sampler 225 and the third deserializer 235 may operate based on the clock generated by the clock generator 280.

The synchronization unit 250 may include a first synchronization unit 251 and a second synchronization unit 253. The first synchronization unit 251 may be connected to the second deserializer 233 and the second synchronization unit 253 may be connected to the third deserializer 235. [

The first synchronization unit 251 communicates with the clock data recovery circuit 240 and may provide feedback to the clock data recovery circuit 240 to adjust the sampling timing of the second sampler 223.

The second synchronization unit 253 communicates with the clock data recovery circuit 240 and may provide feedback to the clock data recovery circuit 240 to adjust the sampling timing of the third sampler 225. That is, the sampling timings of the samplers 221, 223, and 225 are the same as those of the first non-serializer 231 and the first and second synchronization units 251 and 253, Can be controlled by a clock. The first and second synchronization units 251 and 253 have substantially the same structure and can operate substantially the same as the synchronization unit 250 described with reference to Fig.

The reformer 260 may be connected to the first and second synchronization units 251 and 253 and the clock data recovery circuit 240. The reformatter 260 can extract the first and second image data by moving the operations performed by the formatter 110 in the reverse order from the first to third bit sets.

The data interface 3 further increases the number of transmission channels by adding one additional channel sharing the clock data recovery circuit 240 to the data interface 1 according to an embodiment of the present invention in Fig. The bandwidth of the mobile terminal 300 can be improved. Also, it is possible to reduce the number of the clock data restoration circuit 240 and the clock generator 280, thereby further reducing the power, complexity, and size of the circuit.

Based on the first bit set and the second bit set, the formatter 110 includes a plurality of registers, a set of high-order bits of image data, and a set of low- A comparator for comparing the number of transitions included in the upper bit set and the lower bit set, a comparator for comparing the number of transitions included in the lower bit set to the first bit set, And a plurality of dummy bit generators for generating a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set . A detailed description of the formatter 110 according to an embodiment of the present invention will be described later with reference to FIG.

Figure 12 is a block diagram of a formatter in accordance with some embodiments of the present invention.

12, the formatter 110 includes a plurality of registers 101, a plurality of counters 103 and 104 for counting the number of serial transitions contained in upper and lower bits of the image data, A comparator 105 for comparing the number of serial transitions included in the bit and a plurality of multiplexers 108 and 109 for assigning many transitions to the first bit set and assigning the less transposed bits to the second bit set, And a plurality of dummy bit generators 106 and 107 for generating a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set.

Each of the first register 101 and the second register 102 can receive and store upper and lower bits respectively in the first image data and the second image data. The first image data and the second image data may be RGB data of a pixel of the image sensor. Each of the counters 103 and 104 may be connected between the first and second registers 101 and 102 and the comparator 105 and may store the upper and lower bits stored respectively in the first and second registers 101 and 102, The number of serial transitions included in the serial number can be counted. The comparator 105 can receive the first counter value and the second counter value from the first counter 103 and the second counter 104 and compare the received first counter value with the second counter value. If the first counter value is greater than or equal to the second counter value, the comparator 105 may output a low logic signal to the multiplexers 108 and 109, thereby allowing the lower bits to be output to the LD channel And the upper bits can be output to the HD channel. The dummy bit generator 106, 107 may add an additional bit 0'b to the lower bit and add an additional bit 1'b to the upper bit to indicate which bit set is an upper bit or a lower bit. If the first image data and the second image data are 10-bit image data, the output of the image data of the HD channel and the LD channel may be 11-bit image data due to an additional dummy bit.

The reformatter 260 may extract or remove dummy bits attached to the upper and lower bits, respectively, based on the first image data and the second image data.

13 is a block diagram of an image pickup apparatus according to another embodiment of the present invention.

Referring to FIG. 13, the image pickup device 800 according to another embodiment may include an image sensor 811 and an image signal processing unit 813. The image sensor 811 includes an Active Pixel Sensor (APS) array 810, a timing generator 820, a row decoder 810, and a row decoder 810. The Active Pixel Sensor (APS) array 810 includes pixels arranged in a two- a row decoder 830, a row driver 840, a correlated double sampler (CDS) 850, an analog to digital converter (ADC) 860, a latch unit latch 870, a column decoder 880, and the like.

The APS array 810 includes a plurality of unit pixels arranged two-dimensionally. The plurality of unit pixels serve to convert the optical image into an electrical output signal. The APS array 810 can be driven by receiving a plurality of driving signals such as a row selection signal, a reset signal, and a charge transfer signal from the row driver 840. In addition, the converted electrical output signal may be provided to the correlated dual sampler 850 via a vertical signal line.

The APS array 810 may include image pixels of the CMOS type. Although not explicitly shown in the drawings, the pixels disposed in the APS array 810 may be arranged in a Bayer pattern or a chess mosaic form. When employing the Bayer pattern technique, the pixels in the active APS array 810 may be arranged to receive red light, green light and blue light, respectively. However, the spirit of the present invention is not limited thereto, and the configuration for a plurality of active pixels arranged in the APS array 810 can be modified in any way. For example, in some other embodiments of the present invention, a plurality of active pixels disposed in the APS array 810 may be configured to emit magenta (Mg) light, yellow (Y) light, Cy light, and / It may be arranged to receive light.

Timing generator 820 may provide timing and control signals to row decoder 830 and column decoder 880

The row driver 840 may provide a plurality of driving signals to the active pixel sensor array 810 to drive a plurality of unit pixels according to the decoded result in the row decoder 830. [ Generally, when unit pixels are arranged in a matrix form, a driving signal may be provided for each row.

The correlated dual sampler 850 can receive and hold and sample the output signal formed on the active pixel sensor array 810 via the vertical signal line. That is, it is possible to sample a specific noise level and a signal level by the output signal, and to output a difference level corresponding to the difference between the noise level and the signal level.

The analog-to-digital converter 860 can convert an analog signal corresponding to the difference level into a digital signal and output it.

The latch unit 870 latches the digital signal and the latched signal is sequentially transmitted to the image signal processor (ISP) 813 according to the decoding result in the column decoder 880.

The image signal processing unit 813 can be formed substantially the same as the image signal processing unit 13 described with reference to Fig. The image signal processing unit 813 can adjust the gain correction and the white balance of the light amount with respect to the electric signal output from the image sensor 811. [ The image signal processing unit 813 receives exposure data (i.e., an image signal) of the photographed image, and can remove noise included in the received image signal through correction.

The data interface 801 is positioned between the image sensor and the image signal processing unit and can transmit the first and second image data received from the image sensor 811 to the image signal processing unit 813. The data interface 801 may operate substantially the same as the data interfaces 1 to 3 described above.

Wherein the first image data comprises a first bit and a second bit which is an upper bit of the first bit and the second image data comprises a third bit and a fourth bit which is an upper bit of the third bit can do.

The data interface 801 includes a transmitter for transmitting a first bit set including the first bit and the third bit and a second bit set including the second bit and the fourth bit, And a clock data recovery circuit (CDR) for adjusting the sampling timing of the first and second bit sets by sampling the first and second bit sets, respectively, by adjusting a clock used during sampling.

In this case, the first and second image data may be input as a parallel signal to the transmitter, and the transmitter may convert the first and second bit sets into a serial signal and transmit the serial signal to the receiver.

14 is a block diagram of an image pickup apparatus according to another embodiment of the present invention.

14, an image pickup device 900 according to an embodiment of the present invention includes a zoom lens 902, a diaphragm 904, a focus lens 906, driving devices 902a, 904a, 906a, a CMOS A CDS (Correlated Double Sampling) circuit 910, an A / D converter 912, an image input controller 914, an image signal processing section 916, a compression processing section 920 An on-screen display (OSD) 921, a liquid crystal display (LCD) driver 922, an LCD 924, a timing generator 926, a CPU (Central Processing Unit) 928, Button 933, a memory 934, a VRAM (Video Random Access Memory) 936, a media controller 938, a recording medium 940, motor drivers 942a, 942b and 942c, .

The zoom lens 902 is a lens whose focal length continuously changes by moving back and forth in the direction of the optical axis by the driving device 902a, and can be photographed while varying the size of the subject. The iris 904 can adjust the amount of light entering the CMOS element 908 by the driver 904a when capturing an image. The focus lens 906 can adjust the focus of the subject by moving back and forth in the direction of the optical axis by the driving device 906a.

14, only one zoom lens 902 and one focus lens 906 are shown. The number of the zoom lenses 902 may be two or more, and the number of the focus lenses 906 may be two or more .

The CMOS device 908 is an element for converting the light incident from the zoom lens 902, the diaphragm 904 and the focus lens 906 into an electric signal. In this embodiment, the time for extracting the electric signal is controlled by controlling the incident light by the electronic shutter. The time for extracting the electric signal can be adjusted by controlling the incident light using a mechanical shutter. In an embodiment of the present invention, the image pickup section can be constituted by the zoom lens 902, the diaphragm 904, the focus lens 906 and the CCD element 910. [ The set of image pickup units is not limited to this and may not include the zoom lens 902 or the diaphragm 904.

Some embodiments of the present invention use a CMOS device 908 and the CDS circuit 910 includes a CDS circuit that is a type of sampling circuit that removes noise from the electrical signal output from the CMOS device 908, And an amplifier for amplifying the electric signal after removing it. However, the present invention is not limited to this. In the present embodiment, the digital photographing apparatus 900 is configured by using a circuit in which the CDS circuit and the amplifier are integrated, but the CDS circuit and the amplifier can be configured as separate circuits have.

The A / D converter 912 can convert the electric signal generated by the CMOS element 908 into a digital signal to generate RAW data of an image.

The image input controller 914 can control the input of the RAW data of the image generated by the A / D converter to the memory 934.

The image signal processing unit 916 can adjust the gain correction and the white balance of the light amount with respect to the electrical signal output from the CMOS element 908. [ The image signal processing unit 916 acquires exposure data of the photographed image. The exposure data may include a focus evaluation value (AF evaluation value) or an AE (Auto Exposure) evaluation value. The image signal processing unit 916 can calculate the in-focus evaluation value and the AE evaluation value.

Although not explicitly shown in the drawing, the image signal processing unit 916 can receive the RAW of the image generated from the image input controller 914 using the data interface 1 to 3 according to some embodiments of the present invention . However, the present invention is not limited thereto, and data interfaces 1 to 3 may be used in communication between all the modules in the image pickup apparatus 900. [

The compression processing unit 920 can perform compression processing for compressing the image processed by the image signal processing unit 916 into image data of a proper format. The compression format of the image may include a reversible format or a non-reversible format. As an example of a suitable format, it can be converted to JPEG (Joint Photographic Experts Group) format or JPEG 2000 format.

The OSD 921 can display the setting screen of the digital photographing apparatus 900 on the LCD 924. [ The LCD 924 can display a live view before performing a photographing operation, various setting screens of the image capturing apparatus 900, and a captured image. However, the present invention is not limited thereto. The display of the image data and various kinds of information of the image capturing apparatus 900 on the LCD 924 can be performed through the LCD driver 922. [

The timing generator 926 inputs a timing signal to the CMOS device 908. The shutter speed is determined by the timing signal from the timing generator 926. [ That is, the driving of the CMOS element 908 is controlled by the timing signal from the timing generator 926, and the video light from the subject is incident within the driving time of the CMOS element 908, A signal can be generated.

The CPU 928 can issue a command of a signal system to the CMOS element 908 or the CDS circuit 910 or the like and execute an instruction of the operation system for the operation of the operation unit 932. [ In the present embodiment, only one CPU is included, but commands of the signal system and commands of the operating system can be executed by different CPUs.

The operation unit 932 may be provided with a member for performing operations of the image capturing apparatus 900 or performing various settings at the time of photographing. (Not shown) for selecting a photographing mode or a photographing drive mode and a cross key (not shown) for setting a soft focus effect, a selection button (not shown), and the like are disposed in the member disposed on the operation portion 932 . The shutter button 933 is used to perform a photographing operation, and the subject can be imaged in a fully pressed state while the subject is in a half-pressed state.

The memory 934 is an example of an image storage unit, and can temporarily store a photographed image or an image synthesized by the image synthesis unit 918. [ The memory 934 can have a storage capacity sufficient to store a plurality of images. The reading and writing of the image into the memory 934 can be controlled by the image input controller 914. [ Also, data transfer to memory 934 can be made using data interfaces 1-3 according to some embodiments of the present invention.

The VRAM 936 holds contents to be displayed on the LCD 924. The resolution and the maximum number of colors of the LCD 924 depend on the capacity of the VRAM 936. [

The recording medium 940 can record a photographed image as an example of an image recording section. The input / output to / from the recording medium 940 can be controlled by the media controller 938. As the recording medium 940, a memory card which is a card-type storage device for recording data in the flash memory can be used.

The motor drivers 942a, 942b and 942c can control the driving devices 902a, 904a and 906a for operating the zoom lens 902, the diaphragm 904 and the focus lens 906. [ By operating the zoom lens 902, diaphragm 904 and focus lens 906 using the motor drivers 942a, 942b, and 942c, the size, light amount, and focus of the subject can be adjusted.

The flash 944 can brightly illuminate a subject at the time of shooting at nighttime outdoors or in a dark place. The CPU 928 causes the flash unit 944 to emit light and the flash unit 944 emits light in accordance with the light emission command from the CPU 928 so that the flash 944 emits light The subject may be brightly illuminated.

15 is a block diagram illustrating an example of application of an image device according to embodiments of the present invention to a computing system.

15, a computing system 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and an image sensor 1060 can do.

Here, as the image sensor 1060, an image sensor 811 according to the embodiments of the present invention described above may be used.

14, the computing system 1000 may communicate with a video card, a sound card, a memory card, a USB device, or the like, or may communicate with other electronic devices. The data interfaces 1 to 3 according to some embodiments of the present invention can be used as such communication means.

Processor 1010 may perform certain calculations or tasks. Here, the processor 1010 may include the image signal processor 220 according to the embodiments of the present invention described above. According to an embodiment, the processor 1010 may be a micro-processor, a central processing unit (CPU).

The processor 1010 is capable of communicating with the memory device 1020, the storage device 1030, and the input / output device 1040 via an address bus, a control bus, and a data bus. have.

In accordance with an embodiment, the processor 1010 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

Memory device 1020 may store data necessary for operation of computing system 1000.

For example, the memory device 1020 may be implemented as a DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and / or MRAM. The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

The input / output device 1040 may include input means such as a keyboard, a keypad, a mouse and the like, and output means such as a printer and a display. The power supply 1050 can supply the operating voltage required for operation of the electronic device 1000. [

The image sensor 1060 can communicate with the processor 1010 via busses or other communication links to perform communication. The data interfaces 1 to 3 according to some embodiments of the present invention can be used as such communication means. The image sensor 1060 may be integrated with the processor 1010 on one chip or may be integrated on different chips, respectively.

Here, the computing system 1000 should be interpreted as any computing system that uses an image sensor. For example, the computing system 1000 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, a tablet PC, and the like.

In addition, in some embodiments of the invention, computing system 1000 may be implemented in a variety of computing environments including, but not limited to, an Ultra Mobile PC (UMPC), a workstation, a netbook, a portable computer, a wireless phone, mobile phone, e-book, portable game machine, navigation device, black box, 3-dimensional television, digital audio recorder, A digital picture recorder, a digital picture player, a digital video recorder, a digital video player, and the like.

16 is a block diagram illustrating an example of an interface used in the computing system of FIG.

16, the computing system 1100 may be implemented as a data processing device capable of using or supporting a MIPI interface and may include an application processor 1110, an image sensor 1140 and a display 1150, have.

The CSI host 1112 of the application processor 1110 can perform serial communication with the CSI device 1141 of the image sensor 1140 through a camera serial interface (CSI). The data interfaces 1 to 3 according to some embodiments of the present invention may be used with the camera serial interface.

In some embodiments of the invention, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the application processor 1110 can perform serial communication with the DSI device 1151 of the display 1150 through a display serial interface (DSI). Data interface 1 to 3 according to some embodiments of the present invention may be used with a display serial interface.

In some embodiments of the invention, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). Further, the computing system 1100 may further include a Radio Frequency (RF) chip 1160 capable of communicating with the application processor 1110. The PHY 1113 of the computing system 1100 and the PHY 1161 of the RF chip 1160 can perform data transmission and reception according to a Mobile Industry Processor Interface (MIPI) DigRF. The PHY 1113 of the computing system 1100 and the PHY 1161 of the RF chip 1160 may also perform data transmission and reception using the data interfaces 1-3 according to some embodiments of the present invention.

In addition, the application processor 1110 may further include a DigRF MASTER 1114 for controlling data transmission / reception according to the MIPI DigRF of the PHY 1161. The computing system 1100 includes a Global Positioning System (GPS) 1120, a storage 1170, a microphone 1180, a Dynamic Random Access Memory (DRAM) 1185, and a speaker 1190 . In addition, the computing system 1100 may utilize an Ultra Wide Band (UWB) 1210, a Wireless Local Area Network (WLAN) 1220, and a Worldwide Interoperability for Microwave Access (WIMAX) So that communication can be performed. However, the structure and interface of such a computing system 1100 are merely examples, and the present invention is not limited thereto.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

11: image sensor 13: image signal processor
100: transmitting unit 200: receiving unit
300: channel

Claims (10)

Generating a first bit set including a first bit included in the first image data and a third bit included in the second image data,
Generating a second bit set included in the first image data and including a second bit that is an upper bit of the first bit and a fourth bit that is included in the second image data and is an upper bit of the third bit Formater;
A first serializer for serializing the first bit set;
A second serializer for serializing the second bit set;
A first output driver for converting the serialized first bit set into a first differential signal;
A second output driver for converting the serialized second bit set into a second differential signal; And
And a clock generator for generating a plurality of clock signals delivered to the formatter, the first and second serializers, the first and second output drivers. The method according to claim 1,
The first differential signal is transmitted in an HD (High Density) channel,
And the second differential signal is transmitted on an LD (Light Density) channel. The method according to claim 1,
Logic for converting the first or second bit set to a bit set that includes one or more transitions when there is no transition in the first or second bit set received from the formatter Data interface. The method according to claim 1,
Wherein the first and second image data include N (N is an even number) bits,
Wherein the first bit set comprises lower N / 2 bits of the first and second image data,
And wherein the second bit set comprises the upper N / 2 bits of the first and second image data. The method according to claim 1,
Wherein the formatter converts the first and second image data into a third bit set,
Wherein the third bit set comprises a fifth bit included in the first image data and located between the first bit and the second bit and a fifth bit included between the third bit and the fourth bit, And a sixth bit located at a second bit position. 6. The method of claim 5,
A third serializer for serializing the third bit set,
And a third output driver for converting the serialized third bit set into a third differential signal. The method according to claim 1,
The above-
A plurality of toggle counters for counting the number of transitions included in upper and lower bits of the first and second image data,
A comparator for comparing the upper bit of the first and second image data with the number of transitions included in the lower bit;
The plurality of multiplexers allocating a transition-rich bit among the upper bit and the lower bit to the first bit set and allocating a bit with a lower transition among the upper bit and the lower bit to the second bit set;
And a dummy bit generator that generates a dummy bit indicating whether the first bit set or the second bit set is an LSB bit set or an MSB bit set. 8. The method of claim 7,
Wherein the first bit set and the second bit set further comprise a first dummy bit and a second dummy bit generated by the dummy bit generator, respectively. A first bit set including a first bit included in the first image data and a third bit included in the second image data is received on the first channel,
A second bit set included in the first image data and including a second bit which is a higher bit of the first bit and a fourth bit which is included in the second image data and which is an upper bit of the third bit, Channel,
Sampling the first and second bit sets based on the clock signal provided by the clock generator,
And adjusting the sampling timing of each of the first and second bit sets by adjusting a multi-phase clock signal provided in a clock data recovery circuit (CDR circuit). 10. The method of claim 9,
Generating a first bit set including a first bit included in the first image data and a third bit included in the second image data,
Generating a second bit set included in the first image data and including a second bit that is an upper bit of the first bit and a fourth bit that is included in the second image data and is an upper bit of the third bit ,
Serializing the first bit set and the second bit set,
And converting the serialized first bit set and the second bit set into a first differential signal and a second differential signal.

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