CN110941577A

CN110941577A - SATA interface link layer function realization method based on FPGA

Info

Publication number: CN110941577A
Application number: CN201911078439.5A
Authority: CN
Inventors: 杜鹃; 胡茂海
Original assignee: Nanjing University of Science and Technology
Current assignee: Nanjing University of Science and Technology
Priority date: 2019-11-06
Filing date: 2019-11-06
Publication date: 2020-03-31

Abstract

The invention discloses a method for realizing functions of a SATA interface link layer based on FPGA, wherein a SATA3.0 protocol link layer is responsible for data coding, data verification, frame boundary addition and flow control for frame data from a transmission layer, the link layer executes original data or frame data to be transmitted under the control of an upper layer, and the participation process of the link layer in SATA communication is as follows: the transmission layer module transmits the FIS data packet to the link layer, the link layer calculates the CRC value and the scrambling code of the FIS data packet, adds the primitive and encapsulates the CRC value and the scrambling code into a frame, the frame is transmitted to the physical layer, and 8b/10b coding is carried out on the physical layer. Compared with the existing design, the invention realizes higher-level logic encapsulation, provides a simpler and more convenient operation interface for a user, and the user can realize the function of the SATA link layer only by operating the simple interfaces in the forms of FIFO, RAM, register and the like provided by the invention.

Description

SATA interface link layer function realization method based on FPGA

Technical Field

The invention belongs to an interface implementation technology, and particularly relates to a SATA interface link layer function implementation method based on an FPGA.

Background

How to guarantee that data can be accessed and controlled by a storage device serving as a data storage carrier enables the storage device to still guarantee that the stored data is not acquired by illegal users even in the states of loss, uncontrolled control and the like, and becomes one of important contents of data security research. SATA is an abbreviation for Serial Advanced Technology Attachment, and is a bus for realizing high-speed data transmission between a computer motherboard and a large number of storage devices (such as hard disks and optical disk drives), and has the advantages of high transmission rate, high reliability, simple connection, and the like. SATA is classified into three specifications, SATA1.5Gbit/s, SATA 3Gbit/s, and SATA 6 Gbit/s. However, due to the reasons that the SATA protocol is high in implementation complexity and the security technology hardware is difficult to implement, only a few scientific research institutes in China have developed secure storage control research based on the SATA interface, and most of the related research is based on complete forwarding of control primitives and data, the implementation is simple, interaction with a host or a hard disk cannot be automatically completed, it is difficult to quickly respond to changes and abnormalities in transmission state, and the reliability is low.

With the continuous deepening of the aerospace detection field, people are more and more urgent to acquire data in unknown fields, and the requirement on high performance of an imaging system is higher and higher. At present, a large number of high-speed and large-capacity recording devices such as multispectral cameras, hyperspectral cameras, large-area array CCD cameras and the like exist, and data generated by the image recording devices have the characteristics of wide section, rich details, high transmission rate, high resolution and the like. The unmanned aerial vehicle dynamic shooting and real-time data storage that uses during large capacity, low-power consumption, the required storage system of portable, SATA interface hard disk storage system, it is for current storage medium capacity, and transmission rate is high, and is cheap, and power saving data does not lose and many other advantages. Therefore, it is well suited for onboard portable image storage.

A Charge Coupled Device (CCD) is a new semiconductor integrated photoelectric device developed in the early 70 s of the 20 th century. Over 30 years, research on CCD devices and their application techniques has progressed tremendously, especially in the fields of image sensing and non-contact measurement. Because the CCD camera image has the characteristics of high resolution, large amount of information, etc., how to record the original image data in real time at high speed becomes an increasingly troublesome problem in realizing engineering applications. The traditional solution is to use multiple processors in parallel to realize data acquisition and recording of a high-frame-frequency large-array CCD camera, however, the system of the solution has complex structure, heavy weight, large occupied volume, inflexibility, high requirement on working environment, and is difficult to be applied to occasions with limited environment and space.

The system adopts a V5 chip of Xilinx company as a platform, designs and realizes the function of a SATA link layer, and stores image data of a large-area array CCD camera based on a CameraLink interface into a SATA3.0 solid-state storage disk.

Disclosure of Invention

The invention aims to design and realize a method for realizing the function of a SATA interface link layer based on an FPGA (field programmable gate array), and can solve the problem of data storage of the existing SATA interface hard disk.

The technical solution for realizing the purpose of the invention is as follows: a SATA interface link layer function realizing method based on FPGA, SATA3.0 protocol link layer is responsible for data coding, data verification, adding frame boundary and providing flow control for frame data from transmission layer, the link layer executes original data or frame data to be transmitted under upper control, the process of the link layer participating in SATA communication is as follows: the transmission layer module transmits the FIS data packet to the link layer, the link layer calculates the CRC value and the scrambling code of the FIS data packet, adds the primitive and encapsulates the CRC value and the scrambling code into a frame, the frame is transmitted to the physical layer, and 8b/10b coding is carried out on the physical layer;

the link layer inserts various primitives for flow control, waits for the response of the other side after successful transmission of effective data, and transmits the result to the transmission layer;

when the link layer receives effective data which is coded by 10b/8b from the physical layer, the link layer strips the primitive from the data, and after descrambling and CRC check the data of the stripped primitive, one frame is kept and cached in one FIFO module, the next frame is cached in the other FIFO module, frame data is cached alternately, and the data in the FIFO module is transmitted to the transmission layer alternately.

Compared with the prior art, the invention has the remarkable advantages that:

(1) the invention uses Verilog code to write logic, can be completely and comprehensively realized, has high flexibility and portability, and can be used on various FPGA devices.

(2) The invention has very simple function mode for realizing the link layer, and based on the basic FIFO, RAM and register interface, a user can use the invention to realize the complete function of the SATA link layer on the FPGA device without learning the SATA protocol.

(3) The SATA protocol storage system is excellent in performance and exquisite in design, and is beneficial to a user to build other SATA protocol storage schemes by using the SATA protocol storage system.

Drawings

Fig. 1 is a structural flow chart of an overall implementation method of SATA link layer functions implemented based on FPGA according to the present invention.

Fig. 2 is a jump flow chart of a bus controller in the method for implementing SATA link layer function implemented based on FPGA of the present invention.

FIG. 3 is a statistical diagram of FPGA resource consumption required for link layer implementation.

Detailed Description

The present invention is described in further detail below with reference to the attached drawing figures.

The invention follows two core design ideas during design:

(1) the structure clearly realizes the complete function of the SATA protocol link layer module, and the 8B/10B coding is directly realized by a development board through a physical layer, thereby reducing unnecessary resource occupation.

(2) In the implementation scheme of the SATA protocol link layer module, two FIFO modules are skillfully used for alternately caching a data packet which cannot distinguish complete frame information after primitive stripping, descrambling and CRC check, so that the realization of the link layer function is more concise.

(3) After multiple experiments, the implementation method is stable in operation, the effective transmission rate is close to 500MB/s, and the method is greatly improved compared with other schemes.

(4) The simple interface is provided for the user, and the user can be helped to carry out further development and design by operating the simple interface in the forms of FIFO, RAM, register and the like provided by the invention.

The Virtex5 series FPGA device (model number XC5VFX70T-1ff1136) of Xilinx company is used as a development platform. The SATA link layer is coded by using Verilog language and is realized by using resources such as registers in the FPGA after logic synthesis. Finally, after the SATA link layer is integrated by Xilinx corporation development software ISE 14.7, the statistics of the consumed resources are shown in fig. 3. The invention realizes 8B/10B coding by physical layer through development board, and alternatively caches data packet of one frame of information after primitive stripping, descrambling and CRC check by two FIFO modules, so as to realize link layer function more simply and reduce unnecessary resource occupation. The simple interfaces in the forms of FIFO, RAM, register and the like provided by the invention can help users to carry out further development and design.

As shown in fig. 1, the present invention provides a method for implementing SATA interface link layer function based on FPGA, where the link layer 1 includes a sending module and a receiving module, where the sending module includes a FIS buffer 101, a scrambler 102, a primitive generator 103, a dual port RAM106, and a bus controller 105; the receiving module comprises a receiving controller 107, a primitive stripper 108 and a data buffer 109, and the specific implementation steps are as follows:

step 1, encapsulating various FIS data packets sent by a transmission layer 2, storing the FIS data packets in a FIS buffer 101, generating scrambling codes by a scrambler 102 and generating primitives by a primitive generator 103, writing the FIS data packets, the scrambling codes and the primitives into a dual-port RAM106 through a bus 104 under the control of a bus controller 105, and turning to step 2.

Step 2, the read and write clocks of the dual-port RAM106 are the same, during writing, the first Word to the fourth Word are initialized into two ALIGN primitives, and the FIS data packet, the scrambling code and the primitives are written from the 5 th Word to the 512 th Word; when reading, the Word is sequentially read circularly from the first Word to the 512 th Word and sent to the physical layer 3, and the process goes to step 3.

Step 3, when the receiving controller 107 receives valid data which is subjected to 10b/8b coding from the physical layer 3, the primitive stripper 108 is controlled to capture complete frame data (namely starting with an SOF primitive and ending with an EOF primitive), the frame data stripping primitive is transmitted to the data buffer 109, two FIFO modules are arranged in the data buffer 109, after descrambling and Cyclic Redundancy Check (CRC) are carried out on the data of the stripping primitive, one frame is kept to be buffered into one FIFO module, the next frame is buffered into the other FIFO module, the frame data are alternatively buffered, and the data in the FIFO modules are alternatively transmitted to the transmission layer 2.

The CRC check adopts a CRC-32 bit mode, and the calculation formula meets the CRC calculation formula required by the SATA protocol specification, namely:

g (x) ^32+ x ^26+ x ^23+ x ^16+ x ^12+ x ^11+ x ^10+ x ^8+ x ^7+ x ^5+ x ^4+ x ^2+ x +1, and the calculation initial value is set to 0x 52325032.

The scrambling code generated by the scrambler 102 and the descrambling in the primitive stripper 108 both adopt scrambling code calculation formulas meeting the requirements of the SATA protocol specification, that is: g (x) x ^16+ x ^15+ x ^13+ x ^4+1, and the calculation initial value is set to 0xF0F 6.

As shown in fig. 2, the bus controller 105 in the SATA link layer sending module is essentially a state machine, and implements state jumping according to primitive information and control signals received by the link layer receiving module, so as to achieve the purpose of managing the bus 104. The state machine includes two parts of a host-to-client data transmission stream and a client-to-host data reception stream.

The state machine is in an idle IDEL state, a bus 104 is delivered to a scrambler 102 and a primitive generator 103, and SYNC primitives and scrambling codes are written into a dual-port RAM 106; when the transmission layer 2 sends a request for transmitting the FIS data packet and the physical layer is ready, namely PHYRDY & TransBegin high level, the state machine starts to send data, enters a SendChkRdy state, and sends an X _ RDY primitive and a scrambling code; when receiving the R RDY primitive, the state machine enters a SendData state, reads the FIS data packet packaged in the FIFO module and writes the FIS data packet into the dual-port RAM 106; when FIFOEmptv is at a high level, the state machine enters a Wait state, the bus 104 sends a WTRM primitive and a scrambling code until the received R OK primitive enters an LDEL state, and one FIS data packet sending is completed. Similarly, when the state machine is in an idle IDEL state and receives an X RDY primitive, the state machine starts to enter a state of receiving a FIS data packet RcvWait; descrambling the received FIS data packet and receiving an X _ RDY primitive, and enabling the state machine to enter an RcvChkRdy state; continuing to receive FIS data packets until the SOF primitive is received, and enabling the state machine to enter an RcvData state; and when the EOF primitive is received, the state machine enters a SendOK state until the SYNC primitive is received and enters an IDEL state, and FIS data packet receiving is completed once.

As shown in Table 1, the host SATA3.0 interface design was implemented using the present invention, experiments were conducted with a capacity of 240GB using SATE3.0 solid state disk with ARC100 with client OCZ. The experimental results show that: the SATA3.0 link layer implementation method designed in the text can accurately carry out large-data-volume and long-time reading and writing operations on the memory.

Table 1 link layer implementation port signal definition table

Port name	Direction of rotation	Bit width	Function(s)
				clk75	Input device		1	Link layer clock
reset	Input device		1						Reset
				TxDataIn	Input device	32	Data sent by transport layer to link layer
TxDataInvalid	Input device		1					Indication that data sent by transport layer to link layer is valid
				StartIn	Input device	32	Starting data transmission from transmission layer to link layer, sending command
ReadyOut	Output of	1	Link layer ready to send transport layer data
				RxDataOut	Output of	32	Data sent by link layer to transport layer
RxAValidOut	Output of	1	Two frames of data A which are descrambled and buffered in FIfo after crc are effective
				RxBValidOut	Output of	1	Two frames of data B buffered to FIfo after descrambling and crc are valid

				ReadyIn	Input device		1	Handshake and signature successful signal transmitted from physical layer
TxDataOut	Output of	16	Data sent by link layer to physical layer
				TxChariskOut	Output of	1	The primitive judges whether the data sent to the physical layer is k characters, if so, the high level
RxDataIn	Input device	16	Data sent by the physical layer to the link layer
				RxChariskIn	Input device		1	The primitive judges whether the data sent from the physical layer is k characters, if so, the high level is given

				mylinkstate	Output of	16	Link layer state machine for debugging

Claims

1. A SATA interface link layer function realization method based on FPGA is characterized in that: the SATA3.0 protocol link layer is responsible for data encoding, data verification, adding frame boundaries, and providing flow control for frame data from the transport layer, the link layer performs original data or frame data to be transmitted under upper layer control, and the link layer participates in SATA communication as follows: the transmission layer module (2) transmits the FIS data packet to the link layer (1), the link layer (1) calculates the CRC value and the scrambling code of the FIS data packet, adds the primitive and encapsulates the CRC value and the scrambling code into a frame, the frame is transmitted to the physical layer (3), and 8b/10b coding is carried out on the physical layer (3);

the link layer (1) inserts various primitives for flow control, and after successful transmission of effective data, the link layer (1) waits for the response of the other party and transmits the result to the transmission layer (2);

when the link layer (1) receives effective data which is coded by 10b/8b from the physical layer (3), the data is stripped from the primitive, and after descrambling and CRC (cyclic redundancy check) are carried out on the data stripped from the primitive, one frame is kept and cached in one FIFO module, the next frame is cached in the other FIFO module, frame data is cached alternately, and the data in the FIFO modules are transmitted to the transmission layer (2) alternately.

2. The method for implementing the link layer function of the SATA interface based on the FPGA according to claim 1, wherein: the link layer (1) comprises a sending module and a receiving module, wherein the sending module comprises a FIS buffer (101), a scrambler (102), a primitive generator (103), a dual-port RAM (106) and a bus controller (105); the receiving module comprises a receiving controller (107), a primitive stripper (108) and a data buffer (109);

FIS cache (101): various FIS data packets sent by the transmission layer (2) are packaged and stored;

scrambler (102): generating a scrambling code, and writing the scrambling code into a dual-port RAM (106) through a bus (104) under the control of a bus controller (105);

primitive generator (103): generating a primitive, and writing the primitive into the dual port RAM (106) through the bus (104) under the control of the bus controller (105);

bus controller (105): controlling the FIS buffer (101) to write various FIS data packets into the dual-port RAM (106) through the bus (104);

dual port RAM (106): the read and write clocks are the same, when writing, the first Word to the fourth Word are initialized into two ALIGN primitives, and the FIS data packet, the scrambling code and the primitives are written from the 5 th Word to the 512 th Word; during reading, the words are sequentially read circularly from the first Word to the 512 th Word and are sent to the physical layer (3);

reception controller (107): when receiving valid data which is subjected to 10b/8b coding from the physical layer (3), after controlling descrambling of the primitive stripper (108) and the data buffer (109) and CRC checking, the data is transferred to the transmission layer (2);

primitive stripper (108): capturing complete one frame data of the data which is subjected to 10b/8b coding in the physical layer (3), and stripping the data from a primitive;

data buffer (109): the two FIFO modules are arranged, the data are stripped from the primitive, the data stripped from the primitive are descrambled and CRC checked, one frame is kept to be cached in one FIFO module, the next frame is cached in the other FIFO module, frame data are cached alternately, and the data in the FIFO modules are transmitted to the transmission layer (2) alternately.

3. The method for implementing the link layer function of the SATA interface based on the FPGA of claim 2, wherein: the CRC check adopts a CRC-32 bit mode, the calculation formula meets the CRC calculation formula required by the SATA protocol specification,

namely: g (x) ═ x³²+x²⁶+x²³+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+ x +1, and the calculation initial value is set to 0x 52325032.

4. The method of claim 2The SATA interface link layer function realization method based on FPGA is characterized in that: the scrambling code generated by the scrambler (102) and the descrambling in the primitive stripper (108) adopt a scrambling code calculation formula meeting the requirements of the SATA protocol specification, namely: g (x) ═ x¹⁶+x¹⁵+x¹³+x⁴+1, and the calculation initial value is set to 0xF0F 6.