CN103268278A - SRAM (Static Random Access Memory) controller for supporting multi-core processors and tracking information processing method thereof - Google Patents
SRAM (Static Random Access Memory) controller for supporting multi-core processors and tracking information processing method thereof Download PDFInfo
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Abstract
The invention discloses an SRAM (Static Random Access Memory) controller for supporting multi-core processors and a tracking information processing method thereof. An SRAM is respectively connected with a plurality of processors through a first data path and a second data path, and the SRAM controller is also connected with the SRAM through the first data path. The SRAM controller comprises a filtering module, a mixing module, an SRAM read-write control module, a plurality of control registers and a plurality of status registers, wherein the filtering module, the mixing module and the SRAM read-write control module are sequentially connected, and the control registers and the status registers are respectively connected with the filtering module, the mixing module and the SRAM read-write control module. The SRAM controller filters and mixes tracking information sent by the multiprocessors, so that the data volume of the tracking information needed to be stored is effectively reduced, the use ratio of memory cells of the SRAM during storing the tracking information of the multiprocessors is increased, and the purpose that the SRAM memory cells in limited chips store the tracking information of more multiprocessors is achieved.
Description
Technical field
The application relates to SRAM controller and technical field of data processing thereof, relates in particular to a kind of SRAM controller and trace information disposal route thereof of supporting polycaryon processor.
Background technology
The middle and high end processor mostly can be when normal executive utility, and output is through the track record information of coding.These track record information after being saved, through with decoding and the processing of the supporting debugging acid of processor, can be with the in addition truly reduction of the instruction execution flow of processor inside, thus reach the effect of the processor running status being carried out track record.The preservation of track record information and extraction, for the debugging exploitation in early stage of application program, and the real-time monitoring of program when practical application, all have great significance.
Be used for preserving the track record information through coding that processor sends, both can have adopted the integrated memory module of chip internal, also can adopt the supporting independent storage devices of chip exterior.Adopt the chip exterior independent memory device to store track record information, its advantage is that memory capacity is big.Its shortcoming is the output interface that need increase by a cover track record information at chip, and the transmission speed of this socket needs and can be complementary with the travelling speed of processor, to reach the purpose of real-time output.Adopt the chip internal integrated memory modular to store track record information, its advantage is that storage speed is fast, and saves corresponding chip output interface.Its shortcoming is inner integrated memory module finite capacity, the whole track record information in the time of can't recording processor work.
Along with improving constantly of middle and high end processor speed, and increase chip pin and the continuing to increase of the chip manufacturing that causes and packaging cost, the method that adopts the chip exterior memory device to preserve track record information becomes and is difficult to further realize.Adopt the integrated memory module of chip internal to keep in processor track record information, become the preferred option of high speed processor gradually.In recent years, integrated a plurality of processors in a chip, namely multi core chip becomes the new trend that processor develops.The polycaryon processor chip is doubled and redoubled the data volume of the processor track record information that needs preservation, the integrated memory module of chip internal in addition, capacity is subjected to the physical constraints of chip area and power consumption, that can't do is very big, how to make that with less memory module storage track record information as much as possible becoming one that processor chips design has one of problem to be solved.
The processor of different families, as the series processors of Britain ARM company, the series processors of American I ntel company etc., the track record information of its output has nothing in common with each other.Every company all can carry out in various degree compression at the track record information of its processor, forms the data stream that a cover is used for output and storage.Some patents that track record is compressed are disclosed in the prior art, for example, US Patent No. 7058859 " Trace Reporting Method and System (track record method and system) ", US Patent No. 6918065 " Method for Compressing and Decompressing Trace Information (method of compression and decompression trace information) ", US Patent No. 7209058 " Trace Receiver Data Compression (track receiver data compression) " etc.Above-mentioned technical scheme all is the compression methods towards the track record data stream, thereby reaches the effect that the track record data volume that makes output reduces as far as possible.
Be example with the C*Core series processors, the track record inter-area traffic interarea of output every fixing processor clock cycle, overlaps parallel data bus line by one of fixing bit wide, with one group of track record information packet, delivers in the integrated SRAM of chip internal.This packet comprises two kinds of track record information: effective track record information and invalid trace information.Be responsible for the SRAM of storage trace information, with same fixing processor clock cycle at interval, each packet of receiving deposited in the storage unit, no matter whether this packet comprises valid data.When the processor operate as normal, the packet proportion in the entire packet of output that contains effective track record information is less, that is to say that a large amount of invalid trace informations are deposited in the SRAM.In multi core chip, this phenomenon is just more obvious.Because the finite capacity of the SRAM that chip internal is integrated, valuable SRAM storage unit has not only been wasted in the preservation of invalid trace information in a large number, has also increased the unnecessary power consumption expense of SRAM.
The storer of original storage trace information, another problem of existence is: under the multiprocessor memory module, whole storage space will be divided into some zones.The number of processors that the number in zone equals to need in the chip to preserve trace information.The track record information of each processor can only leave in the own corresponding storage area.When the chip operate as normal, the track record information that certain processor can occur is stained with own corresponding storage area, cause the recorded information partial loss, and the storage area of another processor correspondence also has very big vacant situation to take place.The method of this multiprocessor mean allocation storage space, feasible valuable trace information operating factor of memory space step-down.The processor that needs to preserve track record information in the chip is more many, the just more easy generation of this situation, and the utilization factor of SRAM is just more low.
In sum, be necessary to provide a kind of SRAM controller of supporting polycaryon processor and trace information disposal route thereof to address the above problem.
Summary of the invention
In view of this, the invention provides a kind of SRAM controller and trace information disposal route thereof of supporting polycaryon processor.
To achieve these goals, the technical scheme that provides of the embodiment of the present application is as follows:
A kind of SRAM controller of supporting polycaryon processor, described SRAM link to each other with some processors with second data path by first data path respectively, and the SRAM controller also links to each other with the SRAM storer by first data path, and described SRAM controller comprises:
Filtering module, in the packet that sends for detection of each processor trace information whether need to preserve and trace information whether effective, if trace information need not to preserve or trace information is invalid, then abandon this packet;
Mixing module, described mixing module links to each other with filtering module, is used for the packet of filtering module output is mixed by the packet of the parallel sequencing that arrives with multichannel, converts the effective data packets of single channel to, and sends this effective data packets;
SRAM reads and writes control module, described SRAM read-write control module links to each other with mixing module, be used for receiving the effective data packets of mixing module, and mixed effective data packets is write the SRAM storer, also be used for reading stored valid data bag from the SRAM storer;
Some control registers, described control register links to each other with filtering module, mixing module and SRAM read-write control module respectively, and control register comprises stored configuration unit and the startup of control SRAM controller and the switch control unit of time-out for configuration needs storage trace information processor;
Some status registers, described status register link to each other with filtering module, mixing module and SRAM read-write control module respectively, and status register comprises the packet number status unit that is stored to SRAM storer effective data packets number for sign.
As a further improvement on the present invention, described control register also comprises the information indicating unit, and needs are preserved and the packet of effective trace information indicates for each processor is contained.
As a further improvement on the present invention, described mixing module comprise some data buffers and with a data buffer read-out control circuit that links to each other with the total data impact damper, described data buffer is used for the storage effective data packets and stores buffered data packet number information, and described data buffer read-out control circuit is used for providing control information to data buffer.
As a further improvement on the present invention, the number of described data buffer is identical with integrated number of processors.
As a further improvement on the present invention, described status register also comprises for indicating each data buffer whether being filled with the data buffer status unit of the situation of overflowing.
Correspondingly, a kind of trace information disposal route of supporting the SRAM controller of polycaryon processor said method comprising the steps of:
S1, processor send the packet that comprises trace information;
The filtration of S2, trace information, filtering module detects in each packet whether trace information needs to preserve and whether trace information is effective, if trace information need not to preserve or trace information is invalid, then abandon this packet, if trace information need be preserved and trace information is effective, then send this packet, execution in step S3;
The mixing of S3, trace information, mixing module mixes the packet of filtering module output by the packet of the parallel sequencing that arrives with multichannel, convert the effective data packets of single channel to, and send this effective data packets;
S4, receive the effective data packets in the mixing module, and mixed effective data packets is write the SRAM storer.
As a further improvement on the present invention, described step S2 also comprises:
Needs are preserved and the packet of effective trace information indicates to containing in each processor.
As a further improvement on the present invention, described step S3 also comprises:
The data buffer read-out control circuit provides control information to data buffer;
Obtain data buffer storage effective data packets and store buffered data packet number information;
Select the data buffer that the buffered data packet number is maximum to read.
As a further improvement on the present invention, described step S3 also comprises:
Sign is stored to the number of effective data packets in the SRAM storer;
Indicate each data buffer and whether be filled with the situation of overflowing.
The present invention has following beneficial effect:
The present invention supports the SRAM controller of polycaryon processor and trace information disposal route thereof to filter by the trace information that multiprocessor is sent and mix, effectively reduce the trace information data volume that needs storage, and the storage unit utilization factor when having improved SRAM memory stores multiprocessor trace information, to reach the purpose with the multiprocessor trace information as much as possible of SRAM cell stores in the limited chip.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, the accompanying drawing that describes below only is some embodiment that put down in writing among the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the module diagram of the present invention's one preferred implementation chips;
Fig. 2 is the module diagram of SRAM controller in the present invention's one preferred implementation;
Fig. 3 is the workflow diagram of filtering module in the present invention's one preferred implementation;
Fig. 4 is the module diagram of mixing module in the present invention's one preferred implementation;
Fig. 5 is the particular flow sheet of SRAM controller trace information disposal route in the present invention's one preferred implementation.
Embodiment
In order to make those skilled in the art person understand technical scheme among the application better, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all should belong to the scope of the application's protection.
The invention discloses a kind of SRAM controller of supporting polycaryon processor, SRAM links to each other with some processors with second data path by first data path respectively, and the SRAM controller also links to each other with the SRAM storer by first data path, and the SRAM controller comprises:
Filtering module, in the packet that sends for detection of each processor trace information whether need to preserve and trace information whether effective, if trace information need not to preserve or trace information is invalid, then abandon this packet;
Mixing module, mixing module links to each other with filtering module, is used for the packet of filtering module output is mixed by the packet of the parallel sequencing that arrives with multichannel, converts the effective data packets of single channel to, and sends this effective data packets;
SRAM reads and writes control module, SRAM read-write control module links to each other with mixing module, be used for receiving the effective data packets of mixing module, and mixed effective data packets is write the SRAM storer, also be used for reading stored valid data bag from the SRAM storer;
Some control registers, control register links to each other with filtering module, mixing module and SRAM read-write control module respectively, and control register comprises stored configuration unit and the startup of control SRAM controller and the switch control unit of time-out for configuration needs storage trace information processor;
Some status registers, status register link to each other with filtering module, mixing module and SRAM read-write control module respectively, and status register comprises the packet number status unit that is stored to SRAM storer effective data packets number for sign.
Correspondingly, the invention also discloses a kind of trace information disposal route of supporting the SRAM controller of polycaryon processor, may further comprise the steps:
S1, processor send the packet that comprises trace information;
The filtration of S2, trace information, filtering module detects in each packet whether trace information needs to preserve and whether trace information is effective, if trace information need not to preserve or trace information is invalid, then abandon this packet, if trace information need be preserved and trace information is effective, then send this packet, execution in step S3;
The mixing of S3, trace information, mixing module mixes the packet of filtering module output by the packet of the parallel sequencing that arrives with multichannel, convert the effective data packets of single channel to, and send this effective data packets;
S4, receive the effective data packets in the mixing module, and mixed effective data packets is write the SRAM storer.
Ginseng Figure 1 shows that the module diagram of the present invention's one preferred implementation chips, and this chip has the SRAM controller of supporting polycaryon processor.
Chip internal integrated some processors 10 (processor 1, processor 2 ... processor n), one is used for the SRAM storer 20 of storage trace information and the SRAM controller 30 of a correspondence.Each processor 10 has a parallel data path (first path) to be connected to the SRAM controller, and first path is responsible for transmitting the trace information of each processor 10 to SRAM controller 30.A plurality of processors 10 are shared a parallel bus data path (alternate path) and are connected to SRAM controller 30.The trace information that the SRAM controller is responsible for each processor that first path is transmitted filters and hybrid processing, then writes in the SRAM storer.The SRAM controller also will be responsible for replying the read data request that alternate path transmits, and obtains data from SRAM storer appropriate address and return to the processor that sends read request.The SRAM controller also should comprise some control registers and status register, and each processor can be read and write these control registers and status register by alternate path.
The SRAM controller should comprise following functional circuit at least among the present invention: multiprocessor trace information filtering module, multiprocessor effective trace information mixing module, SRAM read and write control module, control and status register administration module.
Particularly, join shown in Figure 2ly, SRAM controller 30 comprises in the present embodiment: filtering module 31, mixing module 32, SRAM read and write control module 33, some control registers 34 and some status registers 35.Wherein:
In the packet that filtering module 31 sends for detection of each processor 10 trace information whether need to preserve and trace information whether effective, if trace information need not to preserve or trace information is invalid, then abandon this packet.
Join shown in Figure 3ly, store the trace information of certain processor if desired, and this trace information comprises valid data, then this trace information packet can be spliced a processor beacon information, and sends to follow-up mixing module; If the trace information that certain processor sends does not need to preserve, perhaps trace information does not contain effective data, and this packet will be dropped.
Whether the trace information of judging certain processor needs to preserve, and is that the specific control bit by specific control register determines.How to judge whether trace information contains effective information, trace information data packet format declaratives are done to explain in detail hereinafter.
The present invention has increased the filtering function to effective track record information to the optimization that the integrated SRAM controller of original chip internal carries out.Invalid information will no longer be deposited in the SRAM storage unit, thereby saved a large amount of SRAM storage spaces after being identified by the SRAM controller.
Mixing module 32, mixing module links to each other with filtering module, is used for the packet of filtering module output is mixed by the packet of the parallel sequencing that arrives with multichannel, converts the effective data packets of single channel to, and sends this effective data packets.
Join shown in Figure 4, in the present embodiment mixing module 32 comprise some data buffers 321 and with a data buffer read-out control circuit 322 that links to each other with the total data impact damper, data buffer 321 is used for the storage effective data packets and stores buffered data packet number information, and data buffer read-out control circuit 322 is used for providing control information to data buffer.Wherein, the number of data buffer is identical with integrated number of processors.
Mixing module is responsible for the trace information packet that has the processor beacon information with filtering module output, by the sequencing that arrives, converts the parallel multichannel data bag that arrives to the single channel packet, sends to SRAM read-write control module again.Because the parallel multichannel effective data packets that arrives is little when big during its data volume, and send to the single channel packet of SRAM read-write control module, its bandwidth is fixed.
Uniting with 4 karyonides is example, and 4 tunnel parallel valid data paths insert mixing modules, and the effective data packets of every road input can be regarded as at random from the time.Under the worst case, 4 tunnel effective data packets are input to mixing module simultaneously, and output to the packet of SRAM read-write control module, one at the most of per clock period.
Input traffic is greater than the problem of output stream in this local time in order to solve, and this module should comprise the first-in first-out data buffer of some enough degree of depth, and the number of data buffer is identical with number of processors.In the clock period, each data buffer can deposit an effective data packets in, can read an effective data packets simultaneously.Each data buffer should comprise the information of a current packet number that has cushioned, inquires about for the data buffer read-out control circuit.Each clock period of data buffer read-out control circuit is selected a data impact damper from all data buffers, read an effective data packets and send to SRAM read-write control module.Its screening rule is to select the data buffer that the buffered data packet number is maximum to read.
The present invention does not adopt the subregion storage mode, and adopt to mix storage mode, all need preserve the whole SRAM storage unit of processors sharing of trace information, the sequencing that sends by the effective trace information packet, deposit among the SRAM successively, thereby realize the maximized purpose of SRAM memory by using rate.
SRAM reads and writes control module 33, SRAM read-write control module links to each other with mixing module, be used for receiving the effective data packets of mixing module, and mixed effective data packets is write the SRAM storer, also be used for reading stored valid data bag from the SRAM storer.
Control register 34 specifically comprises:
Being used for configuration needs the stored configuration unit of storage trace information processor;
The startup of control SRAM controller and the switch control unit of time-out;
To containing the information indicating unit that needs are preserved and the packet of effective trace information indicates in each processor.
Be used for indicating the packet number status unit that is stored to SRAM storer effective data packets number;
Be used for indicating the data buffer status unit whether each data buffer is filled with the situation of overflowing.
SRAM controller in the present embodiment can receive to many 8 trace informations that the C*Core series processors is sent simultaneously, the automatic fitration gibberish, only store the data of usefulness, and store with the mixing storage mode of subregion not, reach the maximized purpose of storage space utilization factor.
Different processor families, the trace information packet that its processor sends is different.In order to improve the storage space utilization factor, the compression that some processor can carry out the trace information that sends is in various degree handled, the trace information that is saved, it both can be the data stream through overcompression, also can be the data stream without overcompression, what adopt among the present invention be the processing mode of filtering and mixing.
Ginseng Figure 5 shows that the particular flow sheet of the trace information disposal route of the SRAM controller of supporting polycaryon processor in the present embodiment, may further comprise the steps:
S1, processor send the packet that comprises trace information;
The filtration of S2, trace information, filtering module detects in each packet whether trace information needs to preserve and whether trace information is effective, if trace information need not to preserve or trace information is invalid, then abandon this packet, if trace information need be preserved and trace information is effective, then send this packet, execution in step S3.Comprise also in this step that needs are preserved and the packet of effective trace information indicates to containing in each processor;
The mixing of S3, trace information, mixing module mixes the packet of filtering module output by the packet of the parallel sequencing that arrives with multichannel, convert the effective data packets of single channel to, and send this effective data packets;
S4, receive the effective data packets in the mixing module, and mixed effective data packets is write the SRAM storer.
Wherein, step S3 also comprises:
The data buffer read-out control circuit provides control information to data buffer;
Obtain data buffer storage effective data packets and store buffered data packet number information;
Select the data buffer that the buffered data packet number is maximum to read.
The processor trace information packet of indication in the present embodiment refers in particular to the parallel trace information data that per clock period of series processors of C*Core company sends.So-called effective data packets is refered in particular to non-0 trace information packet.Certainly also can be other trace information data in other embodiments, effective data packets also can be carried out different settings according to the difference of data.
By technique scheme as can be seen, the present invention supports the SRAM controller of polycaryon processor and trace information disposal route thereof to filter by the trace information that multiprocessor is sent and mix, effectively reduce the trace information data volume that needs storage, and the storage unit utilization factor when having improved SRAM memory stores multiprocessor trace information, to reach the purpose with the multiprocessor trace information as much as possible of SRAM cell stores in the limited chip.
Device embodiments described above only is schematic, wherein said unit as the separating component explanation can or can not be physically to separate also, the parts that show as the unit can be or can not be physical locations also, namely can be positioned at a place, perhaps also can be distributed on a plurality of network element.Can select wherein some or all of module to realize the purpose of present embodiment scheme according to the actual needs.Those of ordinary skills under the situation of not paying creative work, namely can understand and real the application can be used for numerous general or special purpose computingasystem environment or the configuration in.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and under the situation that does not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, therefore is intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in the scope.Any Reference numeral in the claim should be considered as limit related claim.
In addition, be to be understood that, though this instructions is described according to embodiment, but be not that each embodiment only comprises an independently technical scheme, this narrating mode of instructions only is for clarity sake, those skilled in the art should make instructions as a whole, and the technical scheme among each embodiment also can form other embodiments that it will be appreciated by those skilled in the art that through appropriate combination.
Claims (9)
1. SRAM controller of supporting polycaryon processor, described SRAM links to each other with some processors with second data path by first data path respectively, the SRAM controller also links to each other with the SRAM storer by first data path, it is characterized in that described SRAM controller comprises:
Filtering module, in the packet that sends for detection of each processor trace information whether need to preserve and trace information whether effective, if trace information need not to preserve or trace information is invalid, then abandon this packet;
Mixing module, described mixing module links to each other with filtering module, is used for the packet of filtering module output is mixed by the packet of the parallel sequencing that arrives with multichannel, converts the effective data packets of single channel to, and sends this effective data packets;
SRAM reads and writes control module, described SRAM read-write control module links to each other with mixing module, be used for receiving the effective data packets of mixing module, and mixed effective data packets is write the SRAM storer, also be used for reading stored valid data bag from the SRAM storer;
Some control registers, described control register links to each other with filtering module, mixing module and SRAM read-write control module respectively, and control register comprises stored configuration unit and the startup of control SRAM controller and the switch control unit of time-out for configuration needs storage trace information processor;
Some status registers, described status register link to each other with filtering module, mixing module and SRAM read-write control module respectively, and status register comprises the packet number status unit that is stored to SRAM storer effective data packets number for sign.
2. SRAM controller according to claim 1 is characterized in that, described control register also comprises the information indicating unit, and needs are preserved and the packet of effective trace information indicates for each processor is contained.
3. SRAM controller according to claim 1, it is characterized in that, described mixing module comprise some data buffers and with a data buffer read-out control circuit that links to each other with the total data impact damper, described data buffer is used for the storage effective data packets and stores buffered data packet number information, and described data buffer read-out control circuit is used for providing control information to data buffer.
4. SRAM controller according to claim 3 is characterized in that, the number of described data buffer is identical with integrated number of processors.
5. SRAM controller according to claim 3 is characterized in that, described status register also comprises for indicating each data buffer whether being filled with the data buffer status unit of the situation of overflowing.
6. the trace information disposal route of the SRAM controller of a support polycaryon processor as claimed in claim 1 is characterized in that, said method comprising the steps of:
S1, processor send the packet that comprises trace information;
The filtration of S2, trace information, filtering module detects in each packet whether trace information needs to preserve and whether trace information is effective, if trace information need not to preserve or trace information is invalid, then abandon this packet, if trace information need be preserved and trace information is effective, then send this packet, execution in step S3;
The mixing of S3, trace information, mixing module mixes the packet of filtering module output by the packet of the parallel sequencing that arrives with multichannel, convert the effective data packets of single channel to, and send this effective data packets;
S4, receive the effective data packets in the mixing module, and mixed effective data packets is write the SRAM storer.
7. disposal route according to claim 6 is characterized in that, described step S2 also comprises:
Needs are preserved and the packet of effective trace information indicates to containing in each processor.
8. disposal route according to claim 6 is characterized in that, described step S3 also comprises:
The data buffer read-out control circuit provides control information to data buffer;
Obtain data buffer storage effective data packets and store buffered data packet number information;
Select the data buffer that the buffered data packet number is maximum to read.
9. disposal route according to claim 8 is characterized in that, described step S3 also comprises:
Sign is stored to the number of effective data packets in the SRAM storer;
Indicate each data buffer and whether be filled with the situation of overflowing.
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| CN103268278B (en) | 2016-12-28 |
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