CN101594201B - Method for integrally filtering error data in linked queue management structure - Google Patents

Abstract

The invention discloses a method for integrally filtering error data in a linked queue management structure, which belongs to the technical field of computer networks. The method is characterized in that for a structure allowing for queue management in a linked list mode of external memory space, a novel error data filtration mechanism supporting error data filtration under the condition of alternate arrivals of data packets at different queues is designed according to the operation characteristic that a linked list can recovery a plurality of linked list units by using few pointers in a recovery operation process. The method has the characteristics of short delay, little expenditure and excellent expandability.

Description

The method of integrally filtering error data in linked queue management structure

Technical field

Queue management is one of key technology of the applications of computer network (like router, in the nucleus equipments such as switch and fire compartment wall).The task of queue management is through corresponding architecture, according to the corresponding identification information of packet; Realization is to the branch formation storage and output of packet, and the method for integrally filtering error data in linked queue management structure of the present invention belongs to technical field of the computer network.

Background technology

Along with further developing of internet, new Network continues to bring out.The various network services that comprises voice service, VPN is had higher requirement to network service quality.Because the burst characteristic of network traffics, the excessive reservation of employing bandwidth can not effectively guarantee the service quality of network.Meanwhile, the Internet Service Provider also hopes through providing differentiated service to increase income.

Through service can realize network service quality preferably to the professional execution of various network corresponding priority level.And, just must realize queue management to packet in order to realize priority service, specifically be divided into queuing storage and scheduling output again.The main task of storing of lining up is to store the packet of input respectively according to correspondence sign (like stream number), differentiation formation, and in each formation, safeguards FIFO (First In First Out, FIFO) structure according to the sequencing of packet arrival.Scheduling output then is the SO service order that draws according to dispatching algorithm, the packet of specified queue head of the queue is seen off, and upgrades the respective queue state.

Along with the quick raising of network link transmission rate, the queue management that realizes through software mode can not meet the demands, and relies on its huge performance advantage to occupy the high-end applications field gradually through hard-wired queue management chip.Through design relevant hardware chip; Cooperate and adopt dynamic random access memory (DynamicRandom Access Memory; DRAM), (Static Random Access Memory SRAM) waits the external memory chip can realize at a high speed and cheap queue management system to static random access memory.At certain applications occasion (in switching network), packet possibly present the phenomenon that alternately arrives between each logic query.Because possibly there be the unusual of partial data in various unpredictable factors, packet inside or lose.How to filter this part misdata bag and be one of problem that queue management system need solve.

To the filtration problem of misdata bag, general solution is that two-level cache is filtered.The i.e. extra level cache that is provided with in the porch, each complete packet of buffer memory is let pass to the next stage buffer memory after the data to be tested bag is errorless more in advance.Since possibly exist between packet the phenomenon that alternately arrives (as, receive the packet header of A packet earlier, and receive the packet header of B packet, just receive A packet bag tail then), first order buffer memory need be safeguarded a large amount of logic queries.Each formation simultaneously need be reserved the memory space of at least one complete data packet again.This mode storage overhead is big, autgmentability is poor, and bigger delay has been introduced in an in fact extra queue management of carrying out again.

Various problems to the conventional method existence; The advance and the novelty of the technical method of present patent application are embodied in: in the reclaimer operation process, only need revise the operating feature that a small amount of pointer is recyclable a plurality of linked list units through chained list; Designed new filtering error data mechanism, its delay is low, expense is few, favorable expandability.

Summary of the invention

The invention is characterized in that this is a kind of based on the method for integrating filtering error data in the switching network of chained list, in a kind of buffer queue management system, realizes according to the following steps successively:

Step (1). make up a queue management system that is used for the many buffer queue management of said switching network; Said system contains: the SRAM that the DRAM of fpga chip, data cached bag and data cached bag description control information are used; Described fpga chip is Altera Stratix EP1S80F1508C5; The model of DRAM is MT49H 16M 18C, and the model of SRAM is CY7C1370C, wherein:

Fpga chip contains: queue management module and on-chip memory, wherein

Queue management module is provided with: packet input port and packet output port,

On-chip memory MRAM, with said queue management module interconnection,

The DRAM of data cached bag; With the interconnection of said queue management module, the DRAM of said data cached bag is a kind of DRAM that postpones compression, with 16 cycles minimum time unit that is read-write operation; Actual disposition is 64Bx512k; Have the data/address bus that read/write is separated, but read and write a multiplexing cover address and a control bus

The SRAM that data cached bag description control information is used, model is CY7C1370C, has the multiplexing DCB of a cover read-write, actual disposition is 32bits * 512k;

Step (2). the common linked list units of forming one " data field separates with control domain " of selected DRAM and SRAM; Described each linked list units comprises the data field of a 64B and the control domain of a 32bits; Said DRAM and SRAM by having identical high address form

Step (3). in said FGPA, set up the idle managerial structure of a chain type and realize management: the pointer end to end of each logic query of additional maintenance in the on-chip memory MRAM of this FPGA 512 said linked list units; Corresponding to the external memory address of linked list units end to end; Again through one be provided with idle queues end to end the separate queue Freelist of pointer realize management to the idle chain table unit; Simultaneously on this on-chip memory MRAM, add 50bits information and be used for wrong detection and recovery for each formation; Wherein, comprising:

Two 19bits amount to the recovery pointer information of 38bits, storage be the tail pointer of formation under the last correct situation and in order to store new cell newly assigned linked list units address,

1bit parity check sign representes whether all corresponding cells of current data packet check errors occurred, and wherein, mistake appears in " 1 " expression, and " 0 " expression is correct, with the correctness of detection packet content,

1bit sequence of cells checking mark, all cells that the expression current data packet is corresponding whether reach sequence correct, with the packet header of detecting packet, the correctness that the bag tail tag is known, mistake appears in " 1 " expression, " 0 " expression is correct,

Step (4). obtain after compressing the control information of many buffer queues in the said switching network to greatest extent: stream number Flow No; Account for 16bits, segment information Seg.Info accounts for 2bits, and cell length length accounts for 5bits; Total length of data packets Total Length accounts for 9bits, wherein:

Stream number Flow No, high bit representation purpose line card number Card No,

Segment information Seg.Info, comprising: four kinds of states: " 01 " expression data packet head, " 00 " expression packet stage casing, " 10 " expression packet tail, " 11 " expression independent data bag,

Then; Said 16bits stream number of storage and 9bits data source total length information in first linked list units; The said segment information Seg.Info of storage in the subsequent cell of follow-up linked list units; So that the control information of when said DRAM is operated, obtaining next linked list units among the said SRAM

Step (5). the administration module of said formation judges according to the following steps successively whether the packet join the team is correct, when data-bag lost cell or parity errors are mistaken the execution error recovery operation:

Step (5.1). according to the beginning cell of each packet of segment information location, and upgrade said recovery pointer information, the parity check sign, sequence of cells checking mark, and cell number quantitative character,

Step (5.2). afterwards, for the operation described in each the cell execution in step (5.1) that arrives,

Step (5.3). when navigating to the end cell of this packet according to segment information, institute's information recorded judges whether this packet is correct in integrating step (5.1) and the step (5.2):

If the proper data bag then arrives to this packet of scheduler module report,

If error data packets, (5.3) execution error recovery operation set by step,

Step (5.4). said queue management module execution error recovery operation:

Return to this misdata bag of reception correct status before to the formation of said misdata bag with recovering pointer; Simultaneously point to the next hop address for the linked list units address of this packet packet header distribution of being preserved in the said recovery pointer information head of current free pointer; Be this linked list units address setting idle chained list initial address again; Then, reclaim all misdatas in this misdata bag through the modification of pointer again.

The flow process of above operating procedure is as shown in Figure 1.

Fig. 2 has illustrated the system block diagram of queue management, packet generally outside storage chip DRAM rank and buffer memory, the formation descriptor that packet constitutes can be stored in external memory chip DRAM/SRAM or the FPGA sheet stored.Because of the DRAM limited bandwidth, generally extra descriptor is placed in SRAM or the sheet stored as far as possible.

The objective of the invention is to design an effective filtering error data scheme.This scheme is abandoned the two-level cache strobe utility, introduces the filtering error data mechanism filter false data based on chained list.

General chain type managerial structure; All packet is divided into the cell of fixed length, is stored in the external memory, link to each other with indicator linking between the cell; The packet of same formation also links to each other with indicator linking; The tail cell of promptly going up a packet links with pointer with a cell of next packet, and pointer information both can leave among the external memory DRAM with cell, also can leave in the sheet separately or SRAM that sheet is outer in.

This invention emphasis of design is: in the space management process, except in each logic query, safeguarding list structure, system also organizes and manages the idle chain table unit through a separate queue.

The maximum benefit of this structure is in reclaiming the chained list operating process, can once reclaim a plurality of linked list units through simple operations, thereby reach the purpose of filter false packet.The pointer information that when at every turn receiving data packet head, writes down current corresponding formation is then constantly checked in the operating process of packet as recovering pointer.When receiving the packet tail, judge the integrality and the correctness of corresponding data bag, under the situation of packet error, utilize the recovery pointer that recovery operation is carried out in former formation.Simultaneously, because inner each linked list units of misdata bag presents continuous list structure,, can realize disposable recovery, thereby realize the filtration of misdata a plurality of linked list units through revising the mode of idle chain list index.And the influence that chained list distributes and removal process is not alternately arrived by many formations.

Describe in conjunction with object lesson.

Fig. 3 has shown how be numbered three correct cells of 1,2,3 is stored and to be maintained as corresponding list structure respectively.In this process, safeguarded certain control information simultaneously.

Initial condition: have two A of logic query, B in the system; The packet that has only a cell has been stored in two formations; And the tail of the queue unit of a free time is all arranged, when newly to a cell, can at first distribute the tail of the queue storage to cell; Then to new free cells of formation application, be assumed to the address of cell memory cell below the cell.When initial, the current correct status tail of the queue address of A is 0x02 (being the memory address of next first cell of packet), and the address of first next jumping of cell of next packet is not also arranged; The current correct status tail of the queue address of B is 0x08, and the address of first next jumping of cell of next packet is not also arranged.

Give cell 1 memory allocated unit: cell 1 be first cell of new packet, belongs to the A of logic query, be stored among the 0x02 1, and be that formation A newly applies for a free block 0x03; The current correct status tail of the queue address of A still is 0x02, and the address of first next jumping of cell of next packet is 0x03; The state of B does not change;

Give cell 2 memory allocated unit: cell 2 belongs to a packet together with cell 1, is second cell of this packet, be stored among the 0x03 2, and be free block 0x04 of the new application of formation A; The current correct status tail of the queue address of A still is 0x02, and the address of first next jumping of cell of next packet still is 0x03; The state of B does not change;

Give cell 3 memory allocated unit: cell 3 be first cell of new data packets, belongs to the B of logic query, be stored among the 0x08 3, and be that formation B newly applies for a free block 0x05; The current correct status tail of the queue address of B is 0x08, and the address of first next jumping of cell of next packet is 0x05; The state of A is for changing.

After cell 1,2,3 is successfully stored, arrive new cell 4 counterlogic formation A, its arrival makes system awareness to the linked list units of must recovery having distributed to cell 1,2.Reason possibly be:

1, cell 4 is heads of second packet, and cell 2 is not the tail of packet;

2, cell 4 is tails of packet, but information recorded is inconsistent in data packet length after calculating and the data packet head cell 1;

3, cell 4 is tails of packet, and length is consistent.But finding has one or more cell to have parity error in the cell 1,2,4.

So; The information that system will preserve before is used for recovering; Way is as shown in Figure 4, the unit of the current tail of the queue address 0x04 of A is linked to each other with idle queues team leading address, with the address 0x03 of first next jumping of cell of next packet of A as the new team's leading address of idle queues; The tail of the queue address of upgrading A is the current correct status tail of the queue address 0x02 of A, though note next hop address and the non-NULL of 0x02, the free cells of 0x02 for can directly being used, this information can be upgraded after treating to store cell next time; And the current correct status tail of the queue address of replacement A is 0x02.

So wrong linked list units just has been recovered.Idle linked list order after please paying special attention to reclaim is III, IV, VI.And V has been assigned with away.Even the high flexible of chain table handling shows cell and between logic query, alternately arrives that system also can normal filtration misdata bag.

Effect of the present invention is, uses less storage cost (to each logic query, needing the recovery of stomge pointer), and simple recovery operation (only need revise indicator linking one time) just can be easy to when data make a mistake, filter with memory space and reclaim.

Description of drawings

Fig. 1 flow chart of the present invention.

The system block diagram of Fig. 2 queue management device.

Fig. 3 cell arrives back assigning process sketch map:

(a) initial condition,

(b) to after the cell 1 assignment logic formation,

(c) to after the cell 2 assignment logic formations,

(d) to after the cell 3 assignment logic formations.

The a plurality of linked list units process of the disposable recovery of Fig. 4 sketch map:

(a) to after the cell 3 assignment logic formations,

(b) mistake is recovered.

Fig. 5 chain type space management structural representation.

Embodiment

For summary of the invention better is described, this paper has proposed a concrete enforcement example to many buffer queues structure in the switching network.

The fpga chip model that adopts in the process is Altera Stratix EP1S80F1508C5, and the model of RLDRAM (Reduced Latency DRAM) is MT49H16M18C, and the SRAM model of employing is CY7C1370C.

RLDRAM is a kind of less DRAM memory that postpones, and the chip capacity of this use reaches 16M * 18bits, amounts to 288Mbits; Have 8 Bank; Running frequency is 166Mhz, and it has adopted DDR (Double Date Rate) technology, and equivalent running frequency is 333Mhz.Its maximum characteristic is to have the data/address bus that read/write is separated, but a multiplexing cover address and the control bus of read/write.

Parallel for the read/write that realizes RLDRAM, utilize bandwidth to the full extent, in the using of RLDRAM with the minimum time unit of 16 cycles as read-write operation.The maximum throughput that corresponding this 16 cycle can reach is 18bits * 2 * 16=576bits, and wherein to be used for the live part after the verification be 576bits * (16/18)=512bits=64B in eliminating.Then the actual disposition of RLDRAM is appreciated that and is 64B * 512K.

CY7C1370C is a high-performance SRAM that Cypress company produces.It has the multiplexing DCB of a cover read-write.All data manipulations all can only trigger at rising edge clock.Its configuration mode is 36bits * 512K, and capacity amounts to 18Mbits, and running frequency is 166Mhz.Consider that 4bits will be used for verification, real surplus space and configuration mode can only be 32bits * 512K, amount to 16Mbits.

Design one: realize the chain type space management.

Utilize RLDRAM identical with the SRAM logical address space (being 512K all), form " data field separates with control domain " linked list units structure jointly with SRAM by RLDRAM.In logic, be regarded as a complete linked list units to RLDRAM that has identical high address and SRAM.Corresponding each linked list units comprises the data field of a 64B and the control domain of a 32bits.

Realize management through chain type space management structure shown in Figure 5 to 512K linked list units.Wherein the pointer end to end of each logic query of additional maintenance in FPGA on-chip memory (MRAM) is realized the maintenance to the idle chain table unit and pass through a separate queue (Freelist).Illustrated the link information of three linked list units among the figure: the cell of data field storage that the address is respectively the 64B of 0x02,0x04, RLDRAM that 0x07 is corresponding has linking relationship; Address 0x02 is 0x04 corresponding to the information of control domain, and promptly data field next cell in presentation address 0x02 place is stored by address 0x04.

Design two: based on the filtering error data mechanism of chained list.

The filtering error data mechanism based on chained list has clearly been described in the description of explanation before and Fig. 3 and Fig. 4.Its concrete realization mainly is discussed here.

Can know that by Fig. 5 the sheet stored safeguarded the pointer information end to end of each logic query.Add 50bits information for each formation on this basis and be used for wrong detection and recovery.Specifically be divided into:

1, two 19bits amount to the recovery pointer information of 38bits.What recover the pointer information storage is the tail pointer of formation under the last correct status situation and for storing the newly assigned linked list units of new cell address.

2,1bit odd-even check sign.Whether all corresponding cells of its expression current data packet check errors occurred.Be used for detecting the correctness of packet content specially.

3,1bit sequence of cells check tag.Whether its expression current data packet cell arrives sequence correct.Be used for detecting the correctness that packet packet header bag tail tag is known specially.

4, two 5bits cell number quantitative characters.Each packet all can be divided into cell, and 1500 the longest byte data bags can be divided into 24 cells.Here store corresponding original cell number of current data packet and the cell number of having received respectively with two 5bits.Be used for detecting the long correctness of packet bag specially.

Concrete operating procedure is:

1, (packet is divided into cell through behind the switching network, need be reduced to packet, needs this moment an information to be used for instructing reorganization according to segment information.Segment information has identified which part of the corresponding former packet of current data.) can locate the beginning and the end of each packet.When each packet begins, upgrade and recover pointer information.Upgrade the odd-even check sign simultaneously, sequence of cells check tag, cell number quantitative character.

2, afterwards, each a cell just identifies odd-even check, the sequence of cells check tag, and the cell number quantitative character upgrades.

3, when receiving the end cell of a packet, just can combine information recorded to judge whether this packet is correct.

Be divided into two kinds of situation this moment again:

When 1) packet is correct, arrive to this packet of scheduler module report.

2) (losing cell or parity error) during packet error.The execution error recovery operation.

Recover the state of corresponding formation with the recovery pointer.So the formation of corresponding data bag just returns to and receives this packet state before, just correct status.

Simultaneously, with before the next hop address of the linked list units of distributing for this packet packet header of preserving in the step 1 point to current free pointer head.Address setting with this linked list units is the initial address of idle chained list again.

Because the link of the inner chained list of misdata bag is accomplished, at this moment, the modification through pointer just can in this process wrong data recovery.

It is complicated that this process seems, but because practical operation is a unit with the cell, and under the limiting case 16 cycles just have a new cell and arrive, it is very little to upgrade cost.

Conclusion, we adopt based on the fault recovering mechanism of chained list and support data to wrap in the filtering error data under the situation about alternately arriving between different queue, and are littler with respect to two-stage buffer structure expense, favorable expandability.Current other any technology are both at home and abroad led in global design.

Claims (1)

1. the method for integrally filtering error data in linked queue management structure is characterized in that, this is a kind of based on the method for integrating filtering error data in the switching network of chained list, in a kind of buffer queue management system, realizes according to the following steps successively:

Step (1). make up a queue management system that is used for the many buffer queue management of said switching network; Said system contains: the SRAM that the DRAM of fpga chip, data cached bag and data cached bag description control information are used; Described fpga chip is Altera Stratix EP1S80F1508C5; The model of DRAM is MT49H16M18C, and the model of SRAM is CY7C1370C, wherein:

Fpga chip contains: queue management module and on-chip memory, wherein

Queue management module is provided with: packet input port and packet output port,

On-chip memory MRAM, with said queue management module interconnection,

The DRAM of data cached bag; With the interconnection of said queue management module, the DRAM of said data cached bag is a kind of RLDRAM that postpones compression, with 16 cycles minimum time unit that is read-write operation; Actual disposition is 64Bx512k; Have the data/address bus that read/write is separated, but read and write a multiplexing cover address and a control bus

The SRAM that data cached bag description control information is used, model is CY7C1370C, has the multiplexing DCB of a cover read-write, actual disposition is 32bits * 512k;

Step (2). the common linked list units of forming one " data field separates with control domain " of selected RLDRAM and SRAM; Described each linked list units comprises the data field of a 64B and the control domain of a 32bits; Said RLDRAM and SRAM by having identical high address form

Step (3). in said FGPA, set up the idle managerial structure of a chain type and realize management: the pointer end to end of each logic query of additional maintenance in the on-chip memory MRAM of this FPGA 512 said linked list units; Corresponding to the external memory address of linked list units end to end; Again through one be provided with idle queues end to end the separate queue Freelist of pointer realize management to the idle chain table unit; Simultaneously on this on-chip memory MRAM, add 50bits information and be used for wrong detection and recovery for each formation; Wherein, comprising:

Two 19bits amount to the recovery pointer information of 38bits, storage be the tail pointer of formation under the last correct situation and in order to store new cell newly assigned linked list units address,

1bit parity check sign representes whether all corresponding cells of current data packet check errors occurred, and wherein, mistake appears in " 1 " expression, and " 0 " expression is correct, with the correctness of detection packet content,

1bit sequence of cells checking mark, all cells that the expression current data packet is corresponding whether reach sequence correct, with the packet header of detecting packet, the correctness that the bag tail tag is known, mistake appears in " 1 " expression, " 0 " expression is correct,

Step (4). obtain after compressing the control information of many buffer queues in the said switching network to greatest extent: stream number Flow No; Account for 16bits, segment information Seg.Info accounts for 2bits, and cell length length accounts for 5bits; Total length of data packets Total Length accounts for 9bits, wherein:

Stream number Flow No, high bit representation purpose line card number Card No,

Segment information Seg.Info, comprising: four kinds of states: " 01 " expression data packet head, " 00 " expression packet stage casing, " 10 " expression packet tail, " 11 " expression independent data bag,

Then; Said 16bits stream number of storage and 9bits data source total length information in first linked list units; The said segment information Seg.Info of storage in the subsequent cell of follow-up linked list units; So that the control information of when said DRAM is operated, obtaining next linked list units among the said SRAM

Step (5). the administration module of said formation judges according to the following steps successively whether the packet join the team is correct, when data-bag lost cell or parity errors are mistaken the execution error recovery operation:

Step (5.1). according to the beginning cell of each packet of segment information location, and upgrade said recovery pointer information, the parity check sign, sequence of cells checking mark, and cell number quantitative character,

Step (5.2). afterwards, for the operation described in each the cell execution in step (5.1) that arrives,

Step (5.3). when navigating to the end cell of this packet according to segment information, institute's information recorded judges whether this packet is correct in integrating step (5.1) and the step (5.2):

If the proper data bag then arrives to this packet of scheduler module report,

If error data packets, (5.4) execution error recovery operation set by step,

Step (5.4). said queue management module execution error recovery operation:

Return to this misdata bag of reception correct status before to the formation of said misdata bag with recovering pointer; Simultaneously point to the next hop address for the linked list units address of this packet packet header distribution of being preserved in the said recovery pointer information head of current free pointer; Be this linked list units address setting idle chained list initial address again; Then, reclaim all misdatas in this misdata bag through the modification of pointer again.

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