JP4480845B2 - TDM switch system with very wide memory width - Google Patents

Abstract

A switching system. The system includes I input port mechanisms which receive packets from a communication line and have a width, where I is greater than or equal to 1 and is an integer. The system includes O output port mechanisms which send packets to a communication line and have a width, where O is greater than or equal to 1 and is an integer. The system includes a carrier mechanism along which packets travel. The carrier mechanism has a width wider than the width of the input and output port mechanisms. The carrier mechanism is connected to each input port mechanism and each output port mechanism. The system includes a memory mechanism in which packets are stored. The memory mechanism is connected to the carrier mechanism. The system includes a mechanism for providing packets to the memory mechanism though the carrier mechanism from the input port mechanisms. The providing mechanism is able to transfer packets or portions of packets whose total width equals the width of the carrier mechanism in each transfer cycle to the memory mechanism. A switching system for packets. A method for switching packets. The method includes the steps of receiving a first packet and at least a second packet at a switch mechanism. The method includes the steps of transferring data of the first packet and the second packet to a memory mechanism via time division multiplexing of a bus having a width so data from the packets fills a predetermined portion of the width of the bus. The bus width is not necessarily equal to the packet size. <IMAGE>

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a time division multiplexing switch (TDM). More particularly, the present invention relates to time division multiplexing of switches, where the memory bus width is independent of any packet width.
[0002]
BACKGROUND OF THE INVENTION
Time division multiplexing is one technique used to implement a switch system. Consider a switch structure with N input ports each receiving packets at a rate of R and N output ports each sending packets at a rate of R, as shown in Figure 1. For one shared TDM switch system, one memory bus with a total bandwidth of 2 × N × R is required. Arriving packets are collected and written to memory. Once written to memory, the packet is read from memory and sent on the output port.
[0003]
The system will work correctly and without failure if the shared memory has enough bandwidth to service all the input and output ports. Memory bandwidth can be increased by increasing memory bus speed and memory bus width. Current memory bus speeds are technically limited to approximately 300 MHz using microprocessor synchronous cache memory. To further increase the memory bandwidth, the memory bus must be expanded further.
[0004]
Consider the example of a TDM switch system with four input ports and four output ports as shown in FIG. The input and output ports consist of a 1-bit wide data path and operate at a single fixed clock rate. This is the same for all ports and memory buses. Let's assume that all packets are 8 bits long. The structure can be implemented using an 8-bit wide TDM memory bus. Each input port is assigned one clock period and a packet (8 bits) is written to the memory during each period of 8 clock cycles or more, and each output port is assigned one clock period to send one packet from the memory. Read.
[0005]
There are a number of issues that complicate the design of a TDM switch system. Depending on the application of the switch system, the packets are usually resized. Changing the size of the packet reduces the performance of the TDM system due to fragmentation of the packet on the memory bus. If one packet does not use an integer multiple of the memory period, the memory bandwidth is wasted on the memory period when reading or writing data smaller than the memory width. Typically, TDM systems are run with a memory bandwidth greater than 2 × N × R to compensate for the inefficiencies associated with fragments.
[0006]
Fragment issues become critical as the memory width approaches or exceeds the minimum size data packet. Consider a system where the width of the memory bus is equal to twice the minimum packet length. While the length of all received packets is equal to the minimum packet length, the memory system bandwidth is reduced to 50% because all packets written to memory use only half the data bits of the memory bus. (Or 50% efficiency).
[0007]
Because of packet fragments on the memory bus, a typical TDM switch system uses a bus width that is at most as wide as the minimum length packet.
The total bandwidth of the TDM switch system shared memory is limited by the bandwidth of the memory bus. The bandwidth of a memory bus is determined by its speed (clock rate) and its width (number of bits). If the storage speed is fixed by available storage element technology, the total bandwidth of the TDM switch is constrained by the minimum packet size.
[0008]
SUMMARY OF THE INVENTION
The present invention relates to a switch system. The system has I input port units that receive packets from a communication line having a certain width (I is an integer of 1 or more). The system has O output port sections that send packets to a communication line having a certain width (O is an integer of 1 or more). The system has a carrier part on which packets move. The carrier part has a width wider than that of the input and output communication lines. The carrier part is connected to each input port part and each output port part. The system has a memory part in which packets are stored. In the system, there is a mechanism for supplying a packet from an input port unit to a memory unit via a carrier unit. The supply unit is in each transmission cycle: Them A packet or a portion of the packet whose total width is equal to the width of the carrier part can be sent to the memory part.
[0009]
The present invention relates to a packet switching system. The system has a central resource with a certain width and full bandwidth, an input port section for sending and receiving each packet, and an output port section. Central resources are divided by time slots assigned to input and output port sections. The width of the central resource is independent of any packet width, and the total bandwidth can grow without bound. The system has a memory part for storing packets, and the memory part is connected to a central resource.
[0010]
The present invention relates to a switch system. There is a time division multiplex bus in the system. The system has a memory portion connected to a bus accessed by time division multiplexing of the bus. The system has a mechanism for reading and writing packet data to the memory section through the bus without knowing the boundary of the data packet.
[0011]
The present invention relates to a switch system. The system has a time division multiple carrier part with a certain width. The system has a memory part connected to its carrier part. The system has an input unit having a certain width for supplying packet data to the memory unit so that the packet data satisfies the bus width by time division multiplexing. The bus width is a non-integer multiple of the packet width. The system has an output section with a certain width to supply packet data from the memory section.
[0012]
The present invention relates to a method for switching packets from an input section to an output section each having a certain width. The method is First At least with packets Second The packet is received by the switch unit. The method goes through the division multiplexing of a bus with a certain width, First Packets of Second The packet data is sent to the memory unit, whereby the data from the packet includes a step of filling a predetermined portion of the bus width. The bus width is not the same as the input and output widths.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
In the drawings, like reference numerals refer to like or like parts throughout the several views, more specifically, FIGS. A switch system (10) is shown. The system (10) has I input port sections (12) having a certain width for receiving packets from the communication line (16) (I is an integer of 1 or more). One input port section (12) preferably includes one input port. The system has O output ports (14) with a width of O that send packets to the communication line (16). One output port section (14) preferably includes one output port (O is an integer of 1 or more). The system has a carrier part (20) on which packets move. The carrier part (20) has a width wider than that of the input and output parts. The carrier section (20) is connected to each input port section and each output port section. The system (10) has a memory unit (22) in which packets are stored. The system has a mechanism for supplying packets from the input port unit (12) to the memory unit (22) via the carrier unit (20). The supply unit (20) is Them A packet or a part of the packet whose total width is equal to the width of the carrier part 20 can be sent to the memory part 22.
[0014]
The width of the carrier part (20) is preferably independent of the width of any input or output part. The input port mechanism preferably receives packets of various sizes. The output port section preferably sends out packets of various sizes to the communication line (16). The communication line 16 may be an ATM network.
[0015]
The supply unit (20) also preferably supplies a packet from the memory unit (22) to the output port unit (14) via the carrier unit (20). During the transmission cycle, the supply unit (20) Them Can be sent from the memory section (22).
[0016]
The supply unit (20) has an input stage of a queue group (24), which is connected to the carrier unit (20) and the input port unit (12) and is received by the input port unit. Stored packets. There is also an output stage of the queue group (26), which is connected to the supply unit (20) and the output port unit (14), and stores packets to be sent out from the output port unit. Each queue group corresponds to one packet.
The supply unit (20) includes a sorting unit (28) that arranges packets received by the input port unit at the input stage of the corresponding queue group, and the sorting unit (28) includes the input port unit (12). And connected to the input stage of the queue group (24). The supply unit (20) includes a processing unit (30) that arranges a packet in the output stage of the queue group to a corresponding output port unit (14), and this processing unit (30) includes an output port unit ( It is desirable to be connected to the output stage of 14) and the queue group (26).
[0017]
The sorting unit (28) includes a first write finite state machine (32) for writing a packet to a corresponding input queue, and the supplying unit (20) is a group of queues. A second finite state machine for writing (34) for writing from the input stage to the memory section (22) and a first finite state for reading to read packets from the memory section (22) to the output stage of the queue group Preferably, the processing unit 30 includes a second finite state machine 38 for reading from the output stage of the queue group to the network.
[0018]
The memory section (22) preferably includes a shared memory (40). It is desirable that the packet or a part of the packet moves the carrier part (20) based on time division multiplexing. The carrier part (20) preferably includes a bus (42). When the input stage of the queue group contains at least one cache line of data, the first finite state machine for reading (36) only transfers the packet data of the input stage of the queue group to the bus (42). Is desirable.
[0019]
The present invention relates to a packet switching system (10). The system has a central resource (44) with a certain width and a certain total bandwidth, with an input port section (12) for receiving packets and an output port section (14) for sending packets. . The central resource (44) is divided by time slots assigned to the input and output port sections (14). The width size of the central resource (44) is independent of any packet width size, and the total bandwidth can grow without bound. The system (10) has a memory unit (22) for storing packets, and the memory unit (22) is connected to a central resource (44).
[0020]
The central resource (44) preferably includes a memory bus (42). The central resource (44) preferably includes a group of queues to which packets are classified, and the packets are preferably read from the group of queues and written to the memory unit (22).
The present invention relates to a switch system (10). The system (10) has a time division multiplex bus (42). The system (10) has a memory unit (22) connected to the bus (42) accessed by time division multiplexing of the bus (42). The system has a mechanism for reading and writing the packet data to the memory unit (22) through the bus (42) without knowing the boundary of the data packet.
[0021]
The present invention relates to a switch system (10). The system has a time division multiple carrier section (20) having a certain width. The system has a memory part (22) connected to its carrier part (20). The system has a mechanism for supplying packet data from the input port unit to the memory unit (22) so that the packet data satisfies the width of the bus (42) by time division multiplexing. The width of the bus (42) is a non-integer multiple of the width of the input / output port section.
[0022]
The present invention relates to a method for switching packets from an input unit to an output unit. That way First At least with packets Second The step of receiving a packet of a packet by a switch unit having a certain width is included. In this method, the data of the first packet and the second packet are sent to the memory unit (22) by time division multiplexing of the bus (42) having a certain width, and the data from the packet is sent to the width of the bus (42). Including a step of filling a predetermined portion. The width of the bus (42) is not the same as the width of the input / output port section.
[0023]
The width of the bus (42) is preferably a positive multiple of the width of the input port section, and may be a non-integer multiple. The transmission process consists of placing the first packet and at least the second packet at the input stage of the queue group, and transferring the data at the input stage of the queue group between the time slots allocated on the bus (42). In addition, it is desirable to include a step of sending data to the memory unit (22) so that the data satisfies a predetermined ratio of the bus width (42).
[0024]
Before the data transmission process, determining whether a group of input queues has enough data to satisfy at least a predetermined percentage of the bus width (42) before the data is sent to the bus (42). It is desirable that there is. Preferably, prior to the data sending step, there is a step of determining whether the input stage of the queue group has at least one cache line.
[0025]
In the operation of the present invention, system (10), the memory width limitation of a typical TDM switch system is to sort the packets into the input stage of the queue group (24) and then to the input stage of the queue group (24). Is removed by reading data from and writing to memory. The memory width is independent of the minimum packet size, and the total bandwidth of the TDM switch system can be increased without limit.
[0026]
Packets arriving at the input port of the switch system (10) are classified into a certain number in the queue group (24). One queue is implemented in each group in three stages.
1. Input stage: The tail of the queue is implemented in the switch structure by a first finite state machine for writing (W-FSM).
2. Memory phase: The middle of the queue is implemented with shared memory.
3. Output stage: The head of the queue is implemented in the switch structure by a first finite state machine (W-FSM) for reading.
[0027]
Reading and writing to the shared memory is performed on the data in the queue group, and packet boundaries in the queue are not conscious. Access to the shared memory is assigned to the read / write FSM by time division multiplexing of the shared memory bus.
[0028]
W-FSM is implemented as follows:
The process that W-FSM stores in the queue:
After the packet arrives from the input port, it is classified and added to the tail of the queue group on the W-FSM.
The process by which W-FSM drains into the queue:
(When a time slot is assigned to the TDM bus)
(If W-FSM contains at least one data cache line)
Write the cache line at the beginning of the W-FSM to the end of the shared memory queue.
R-FSM is implemented as follows:
The process of R-FSM storing data in the queue
(In the time slot assigned to the TDM bus)
If (when R-FSM does not contain data)
If (if shared memory contains data for this queue group)
Read the cache line at the head of the shared memory queue and queue it at the end of the R-FSM queue.
If not (if shared memory does not contain data for this queue group)
Read any data from the top of the W-FSM queue to the end of the R-FSM queue (up to the cache line).
The process by which R-FSM drains data to the queue
Packets are taken from the top of the output stage of the R-FSM queue, processed, and forwarded to the output port.
[0029]
More specifically, one cell or one packet arrives at one input port of the switch (45). W-FSM (32) classifies packets into queue group (24). When other packets arrive at the input port of the switch (45), they are also classified by the W-FSM (32) into their corresponding queue group (24). Once classified into a queue group, they (packets) are added to the tail of the corresponding input stage queue group. Classification and storage of cells arriving at the input port of the switch (45) will continue, but for a certain input stage queue group (24), when one packet is classified, Added to the tail of the corresponding input stage queue group.
[0030]
The second finite state machine (34) for writing corresponding to the queue group (24) at the input stage records the number of packets in the queue group (24) at the input stage. When there are enough packets in the input stage queue group (24) for the data on the input stage queue group (24), the second finite state machine for writing (34) 24) Waiting for the arrival of the time slot assigned on the bus. When the assigned time slot arrives, there is not enough data in the input stage queue group (24) to fill the cache line, so data was previously released from the input stage queue group (24). Although there was not enough data to fill the cache line, the second finite state machine for writing (34) has now changed from the queue group (24) of the input stage to the queue group (24 Send enough data to fill the cache line during the time slot assigned to. The allocated time slot is a period sufficient to allow the data cache line to be sent from the input stage queue group (24) to the bus. When the data cache line from the input stage queue group (24) is sent on the bus, the data remaining in the input stage queue group (24) is moved to the head of the input stage queue group (24). . Further, the data moved to the head of the queue group (24) at the input stage creates room for the next packet or data to enter the queue group (24) at the input stage. It is possible that cells are placed at the tail of the input stage queue group (24) just as data is being sent to the bus from the input stage queue group (24).
[0031]
Depending on the size of the cache line, the data sent to the bus may be other than an integral multiple of the data held in the packet in the queue group (24) at the input stage. For example, the cache line has such a width that a part of the packet remains in the queue group (24) of the input stage after the data of the cache line is sent to the memory (40) on the bus. The second finite state machine for writing (34) is unaware of cell / packet boundaries, and only has to fill the cache line with data, regardless of the result of the integrity of the cell / packet. Therefore, the cells and packets are divided to adapt to the constraint that the data fills the cache line within the assigned time slot.
[0032]
When the data cache line arrives at the shared memory (40) from the bus, the controller (47) stores the data cache line in the shared memory (40) and caches it from the queue group (24) at the input stage. The address in the shared memory (40) is recorded in the order of the queue group (24) of the input stage that is the connection source of the line and the cache line. Thereafter, the data cache line sent from the queue group (24) of different input stages is stored in the shared memory (40) by the controller (47). The next cache line sent from the queue group (24) at the input stage is also stored in the shared memory (40). The controller (47) keeps track of the address where the cache line from the input stage of the queue group (24) is stored. Suppose the first cache line from the input stage queue group (24) has the first part of the cell, and the second cache line from the input stage queue group (24) has the second part of the cell. Even so, the next cache line from the input stage queue group (24) is not necessarily stored in the same address or stored in two addresses adjacent to each other.
[0033]
When a packet is sent out from an output port, the first finite state machine (36) for reading corresponding to the queue group (26) of a certain output stage is allocated on the bus to the queue group (26) of that output stage. Waiting for a given time slot. The first finite state machine for reading (36) keeps the data in the shared memory (40) read into the queue group (26) of the output stage. Since the first finite state machine for reading (36) is connected to the controller (47) and the first finite state machine for writing (32), which data is sent to the queue group (26) of the corresponding output stage. I understand. When the next assigned time slot arrives at the output stage queue group (26), the cache line in the shared memory (40) for the output stage queue group (26) is read first finite. It is read into the queue group (26) of the output stage by the state machine (36). The first finite state machine for reading (36) is connected to the controller (47), thereby knowing from which location the cache line should be read. The cache lines are read sequentially and placed in the output stage queue group (26), so when the output stage queue group (26) is recombined in the write stage to the shared memory (40), All split cells are also recombined. When the time slot allocated for the output stage queue group (26) arrives and there is no data, the first finite state machine for reading is directly cached from the input stage queue group (24). Data is read into the line, and the data is finally transmitted to the queue group (26) of the output stage.
[0034]
The second finite state machine for reading (38) keeps the information of the queues in the output stage queue group. The second finite state machine (38) for reading only reads a packet from the queue group (26) of the output stage to a predetermined quantity only when a predetermined amount is formed in the queue group (26) of the output stage in the packet, Send the packet out to the network.
[0035]
Since all reads and writes to the memory include all cache lines of data, the efficiency of the memory bus 42 is 100%. Small packets do not cause data fragmentation on the memory bus (42). Furthermore, the width of the memory bus can be increased without limit and is not limited by the size of the packet.
[0036]
The queue group model can be used to implement any queue structure. To implement an output queue, one queue group is assigned to each output port. The queue group includes an input stage queue group, a cache line stored in a shared memory, and an output stage queue group. The packet sorting unit inspects each packet at the time of input, and classifies the packet into an appropriate output queue. The packet is associated with an input stage queue group corresponding to the output stage queue group. The queue group (28) in the output stage is queued from memory to memory using W-FSM and R-FSM. After R-FSM, the packet is immediately queued to the output port.
[0037]
By associating one queue group (24) for each input port, an input queue is implemented using a simple packet sorting unit. The mechanism based on priority is implemented as follows. One queue group is defined for each of several priority levels. On input, one packet is sorted into one of the priority queue groups. Queues are queued in memory using W-FSM or R-FSM. After R-FSM, the packet is processed to determine the respective output port and sent out of the system.
[0038]
[Example]
A packet switch with four input ports and four output ports is implemented using the system (10). The system is totally synchronized and operates with a 20MHz clock period. The four inputs operate 8 bits wide and implement four 160Mbps interfaces. As shown in FIG. 5, the packet is delimited by a code word representing a packet start end (SOP) and a packet end end (EOP).
[0039]
This example assumes an output queue switch. Packets that arrive at the input port of the switch system (10) correspond to each output port, and are classified into four queue groups. Referring to FIG. 4, the output queue is implemented in each group of three subsystems:
1. The tail is implemented by a first finite state machine (W-FSM) for writing in the switch structure.
2. The middle is implemented in shared memory.
3. The top is mounted in the switch structure by the first finite state machine for reading (R-FSM).
[0040]
Reading and writing to the shared memory is implemented on the queue group data and is executed without being aware of the packet boundaries of the data in the queue. Access to the shared memory is assigned to the first finite state machine for reading and writing by time division multiplexing of the shared memory bus. The shared memory bus width is called a cache line.
[0041]
The head and tail of the queue group in the input stage / output stage of the present invention are directly implemented in the shift register (51). The shift register 51 has the same width as the incoming data interface and the same length as the memory cache line. The data path for a four port switch is shown in FIG.
[0042]
The cache line is 64 bits long and is 8 bytes itself. Data from each port is shifted 8 registers deep into a shift register with an 8-bit wide cache line. Not shown is a synchronous shift register before an 8-bit shift register, also 8 registers deep. As shown in FIG. 7, the memory bus is divided into eight time slots for each input / output port in a TDM (time division multiplexing) system. Because the example switch implements an output queue, the output queue is always drained at the same rate, and therefore always uses the same time slot on the bus. Since incoming packets are directed to any output port, the input stage queue can fill at any rate. Input stage queues are allocated as many input bus time slots as necessary. Since the total input rate does not exceed four time slots, it is sufficient for the input stage to arbitrarily adjust the four input stage time slots.
[0043]
The synchronization register is used to compensate that no data is lost. Typically, data is not stored in the synchronization register. All incoming packets are written directly to the cash register. If the cache register is filled before that time slot on the TDM bus, the sync register begins to store data, and once the cache line register is empty, the data from the sync register is pushed into the cache line register. If the cache line register is still full, adjust the next input bus cycle immediately. Only filled cache line registers regulate bus cycles.
[0044]
As shown in FIG. 8, the head and tail of the present invention (input and output stages) are implemented directly in the hardware FIFO queue. The middle part of the queue group is implemented in memory and stored in a cache line. In this example, a 256-layer memory that can read and write the entire cache line in only one clock cycle is used. Zero turn around memories (ZBT) is assumed, and writing follows direct reading.
[0045]
As shown in FIG. 9, five FIFO queues (57) are required to implement the middle part of the memory queue group. Four of the queues contain the addresses of cache lines contained in the memory, and the fifth queue is called a free list and contains the addresses of empty cache lines. By resetting the free list, the FIFO is initialized to include all the addresses of the cache lines included in the memory, and the channel address FIFO becomes empty.
The data path operates in one of eight states:
Ain, Bin, Cin, Din, Aout, Bout, Cout, Dout
[0046]
This state is determined by the time slot indicated by the memory framework. In this example, the four output queue groups use individual specified states. The input stage requires that any of the input states be used. The adjustment mechanism reveals which input stage uses the appropriate input time slot. All input (output) states operate in the same way. Consider an input state Ain where the input stage A is adjusting the input state well. In the first clock period of the TDM framework, Ain works as follows:
(In the time slot assigned to the TDM bus)
If the cache line register is full
-Use the address at the beginning of the free list to drive the memory bus.
-Write the data contained in the channel A cache line register to memory.
― Push the memory address of the free list.
― Push the memory address of the free list into the tail of channel A address FIFO.
[0047]
If the FIFO is empty at the memory address of the free list, the data located in the channel A cache line register is dropped. Care must be taken to identify dropped packets on channel A. Other input channels operate similarly in their own specified memory time slots. Consider the output state Aout in the TDM framework. In the fifth clock period, Aout operates as follows:
(In the time slot assigned to the TDM bus)
If (when R-FSM has no data)
If the shared memory contains data for this queue group
Read the cache line at the head of the shared memory queue to the tail of the R-FSM queue.
If not (if shared memory does not contain data for this queue group)
Read all data from the top of the W-FSM queue (up to the cache line) to the end of the R-FSM.
[0048]
For the draining process of the R-FSM queue, the packet is pushed out from the head of the R-FSM queue, transmitted, and sent to the output port. Since all reads and writes to the memory include all cache lines of data, the efficiency of the memory bus 42 is 100%. Small packets do not cause data fragmentation on the memory bus (42). Furthermore, the width of the memory bus can be increased without limit and is not limited by the size of the packet.
[0049]
Although the invention has been described in detail in the foregoing embodiments for purposes of illustration, this detailed portion is solely for this purpose (illustrated) and those skilled in the art will be able to claim the following claims. It should be understood that changes may be made without departing from the spirit and scope of the present invention, apart from those described in.
[Brief description of the drawings]
The accompanying drawings illustrate preferred embodiments of the invention and preferred methods of practicing the invention.
FIG. 1 is a schematic diagram of a time division multiplexing switch of the prior art.
FIG. 2 is a schematic diagram of a prior art time division multiplex switch with four inputs and four outputs.
FIG. 3 is a schematic diagram of the switch system of the present invention.
FIG. 4 is a schematic view of the switch system of the present invention.
FIG. 5 is a schematic diagram of symbolic words.
FIG. 6 is a schematic diagram of data paths of four port paths.
FIG. 7 is a schematic diagram of a memory bus divided by a TDM method.
FIG. 8 is a schematic view of a memory.
FIG. 9 is a schematic diagram of five FIFO queues.
[Explanation of symbols]
(10) Switch system
(12) Input port section
(16) Communication line
(20) Career Department
(22) Memory section
(24) Input stage queue group
(26) Output stage queue group
(28) Sorting department
(30) Processing section
(32) First finite state machine for writing
(34) Second finite state machine for writing
(36) First finite state machine for reading
(38) Second finite state machine for reading
(40) Memory
(42) Bus
(44) Central resources

Claims (21)

I input port sections (I is an integer of 1 or more ) having a certain width, each receiving a packet from the communication line ;
O output port sections (O is an integer of 1 or more ) having a certain width, each sending a packet to the communication line ;
A carrier unit that is connected to each input port unit and each output port unit and has a width larger than the width of the input / output port unit and carries a plurality of packets. A carrier part sent in a slot ;
A memory unit for storing a plurality of packets, and a memory unit connected to the carrier unit ;
A supply unit for supplying packet data from the I input port units to the memory unit via the carrier unit, and connected to the carrier unit and the I input port units. A plurality of queue groups in the input stage for storing received packets, and a plurality of queue groups in the output stage connected to the carrier section and the O output port sections for storing packets sent from the O output port sections. And a supply unit containing
Have
The supply unit sends the data of the plurality of packets to the memory unit in the allocated time slot only when the data of the plurality of packets in the queue group at the input stage is sufficient to satisfy the width of the carrier unit. If there is not enough data to fill the width of the carrier part, the queue group data is not sent to the memory part in the assigned time slot.
Switch system.   The switching system as defined in claim 1, wherein the width of the carrier portion is independent of the width of any packet.   The system as defined in claim 2, wherein the input port portion receives packets of various sizes.   4. The system as defined in claim 3, wherein the output port section sends packets of various sizes to the communication line. The supply unit also supplies packets from the memory unit to the O output port units via the carrier unit, and during each transmission cycle, a plurality of packets whose total width is equal to the width of the carrier unit. 5. A system as defined in claim 4, wherein portions of the plurality of packets can be sent to the memory portion. Supply unit, the packets received by the input port unit includes a sorting unit to place the queue group corresponding input stage, the sorting unit queue of the I input ports unit and a plurality of input stage 6. A system as defined in claim 5 connected to a group . The supply unit includes a processing unit that arranges the packets in the queue group of the output stage to the corresponding output port unit, and the processing unit includes O output port units and a plurality of output stage queue groups. The system as defined in claim 6 , wherein the system is connected to The sorting unit includes a first finite state machine for writing to write the packet to the corresponding queue group of the input stage , and the supplying unit for writing to write the packet from the queue group of the input stage to the memory unit A second finite state machine and a first finite state machine for reading the packet from the memory unit to the output stage queue group , and the processing unit reads the packet from the output stage queue group to the network. 8. A system as defined in claim 7 including a second finite state machine for reading. 9. A system as defined in claim 8 , wherein the memory portion includes a shared memory. The system as defined in claim 9 , wherein the packet or portion of the packet travels on a carrier part based on time division multiplexing. 11. A system as defined in claim 10 , wherein the carrier portion includes a bus. Queue group in the input stage, if it contains at least one cache line of data, the first finite state machine for reading sends the data of the queue group the input stage packet to the bus, as defined in claim 11 System. The system as defined in claim 12 , wherein the communication line is an ATM network. 14. A system as defined in claim 13, wherein the memory portion comprises packets stored without knowing packet boundaries. A time division multiplex bus having a width ;
A memory unit that is accessed by time division is connected to the multiplex bus, when time-division multiplexing division multiplexed bus,
The data of a plurality of packets, without knowing the boundaries of the packets of the data, reading the memory unit through division multiplex bus time, which comprises a reading and writing mechanism for writing,
The read / write mechanism sends the data of multiple packets to the memory unit in the allocated time slot only when the data of multiple packets is sufficient to fill the width of the time division multiplex bus. A switching system that does not send data of multiple packets in an assigned time slot when there is not enough data to satisfy the width of A time division multiple carrier part having a certain width ;
A memory unit that is accessed by time division is connected to the multi-carrier unit, when time division multiplexing of division multiplex carrier unit,
To meet the width of division multiplex carrier unit time by time-division multiplexing data of a plurality of packets, for supplying data packet in memory section, an input stage unit having a certain width, time division multiple carrier portion The width of the input stage is a non-integer multiple of the width of the input stage,
A supply unit that supplies data of a plurality of packets to the memory unit by time division multiplexing so that the data satisfies a width of the time division multiplexing carrier unit;
With
The input stage unit sends the data of the plurality of packets to the memory unit in the allocated time slot only when the data of the plurality of packets is sufficient to satisfy the width of the time division carrier unit, and the time division carrier A switch system that does not send the data in these buckets in the assigned time slot if it is not sufficient to fill the width of the part. A method for switching packets ,
A first packet, the steps that receive at least a second packet switching unit,
Only when the data of the first packet and the second packet is sufficient to fill the width of the bus, the first packet and the second packet are assigned to the assigned time slot by time division multiplexing of the bus. If there is not enough data to fill the bus width and fill the bus width, the first packet and second packet data are not sent in the assigned time slot;
With
Way not the width of the bus is also the function of the data contained in which packets. The width of the bus is a non-integer multiple of the width of the packet, as defined in claim 17 method. Placing the first packet and at least the second packet in the queue of the input stage, and the data in the queue group of the input stage between the time slots assigned by the bus , as satisfied, and a step of sending to the memory unit, as defined in claim 18 method. Before the step of sending the data, whether the queue group the input stage has enough data to fill at least a bus width, the data includes the step of determining before being sent to the bus, to claim 19 Prescribed method. 21. A method as defined in claim 20 , comprising prior to sending data, determining whether the queue of input stages has at least one cache line of data .

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